JPH0728009B2 - Gallium arsenide semiconductor memory integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a gallium arsenide semiconductor memory integrated circuit,
In particular, it relates to the memory cell structure.

[Conventional technology]

Figure 3 shows, for example, the 1981 IEDM (International Electron
Devices Meeting) is a diagram showing a circuit configuration of a memory cell in a conventional gallium arsenide memory integrated circuit described in Proceedings page 83. In this figure, 1 and 2 are normally-on type metal-semiconductor field effect transistors (hereinafter, the metal-semiconductor field-effect transistor is abbreviated as MESFET), and 3 to 6 are normally-off type MESFETs.

The normally-on type MESFET1 and the normally-off type MESFET3 constitute a first E / D inverter circuit in which the normally-on type MESFET1 is a load, the normally-off type MESFET3 is a driver, and the input is a node 9 and the output is a node 8 and is a normally-on type. MESFE
The drain of T1 is connected to the power supply node 7, and the gate and source of T1 are commonly connected to the drain of the normally-off type MESFET3. The normally-off type MESFET 3 has a gate connected to the input node 9 and a source connected to the ground potential. Similarly, normally-on type MESFET2 and normally-off type MESFET4
Loaded normally-on type MESFET2, normally-off type MESFET2
A second E / D inverter circuit having FET4 as a driver, an input as a node 8 and an output as a node 9 is constituted, and a normally-on type MESFET2 has a drain connected to a power supply node 7, a gate and a source in common, and a normally-off type. Connected to the drain of MESFET4. The normally-off type MESFET 4 has a gate connected to the input node 8 and a source connected to the ground potential. Further, the first and second E / D inverter circuits have their inputs and outputs cross-connected. Therefore, the nodes 8 and 9 become storage nodes for storing data.

Further, the normally-off type MESFET 5 is a transfer gate, which is connected between the storage node 8 and the bit line 10, and the gate becomes the word line 12. Similarly, the normally-off type MESFET6 is also a transfer gate and is connected between the storage node 9 and the bit line 11, and the gate is a word line.
Twelve.

Next, the operation will be described. When the memory cell is in the non-selected state, the word line 12 is at the Low level and both the transfer gates 5 and 6 are in the non-conductive state, so that the memory cell is disconnected from the bit lines 10 and 11. At this time, a pair of High and Low data is held in the memory cell by the following mechanism.

First, FIG. 4 shows the transfer characteristics of the first or second E / D inverter. In the figure, the solid line 13 is the transfer characteristic of the inverter, and the broken line 14 is a curve obtained by symmetrically folding the solid line 13 with respect to y = x. When the input is at low level, the driver FET becomes non-conductive, so the output is pulled up to high level by the load FET. If the potential of the power supply 7 is 1.5V, the output high level tries to be raised to 1.5V. However, since the output is actually input to the gate of the other inverter, the gate of the driver FET
Due to the presence of the parasitic shutter diode formed between the sources, the clamp is clamped at the shutter barrier height φB, which is usually about 0.6V. Next, when the input level to the inverter rises and exceeds the threshold voltage of the driver FET, the driver FET becomes conductive, and the current driving capacity of the normal driver FET is set to be several times larger than the current driving capacity of the load FET. Therefore, the output level rapidly drops to Low level. As the input level rises further, the output level is gradually raised, in turn due to the presence of a parasitic Schottky diode formed between the gate and drain of the driver FET. In this way, the first or second E / D
The transfer characteristic when the inverter is not selected is the solid line in Fig. 4.
It looks like 13.

Further, since the input and output of the first and second E / D inverters are cross-connected to each other, the potentials of the input node and the output node in the non-selected state are the intersection point (stable point) A of the solid line 13 and the broken line 14. , B is determined. That is, when one of the storage nodes 8 and 9 is at a high level of about 0.6 V, the other is at a low level and is substantially at the ground level.

Thus, when the memory cell is in the non-selected state, the storage nodes 8 and 9 hold a pair of data of High and Low.

Next, when the memory cell is in the selected state, the word line 12 becomes High level during reading, and the transfer gates 5, 6
The data which has been conducted and is held is read out to the bit lines 10 and 11. The data read to the bit line is further amplified by the circuit in the subsequent stage and output to the outside.

In addition, when writing data to the memory cell, the word line 12
After setting the memory cell to the High level and selecting the memory cells, set the bit lines 10 and 11 to the
By setting to Low, the data on the bit line is written to the storage node of the memory cell.

Generally, a MESFET has an active region containing impurities on a gallium arsenide semiconductor substrate, but when this active region is at a high potential, the electrons generated in the substrate by the incidence of α rays are at this high potential. Are collected in the active area of the. Therefore,
When α rays enter the active layer of the storage node on the High side of the memory cell, electrons are collected and the potential of this node drops. This drop is typically greater than 0.6V, so
The potential on the High side becomes lower than the potential on the Low side, and the data is inverted. It cannot be recovered until the next writing.

[Problems to be Solved by the Invention]

Since the memory cell in the conventional gallium arsenide memory integrated circuit has the above-mentioned configuration, the high level of the data held in the memory cell is limited by the height of the shutter barrier between the gate and the source of the driver FET 3 or 4. As a result, the voltage amplitude of the data becomes small and the soft error due to the incidence of α rays is likely to occur.

The present invention has been made to solve the above problems, and to obtain a gallium arsenide semiconductor memory integrated circuit having a memory cell having a high soft error resistance by expanding the voltage amplitude of data held in the memory cell. With the goal.

[Means for Solving the Problems]

A gallium arsenide semiconductor memory integrated circuit according to the present invention is
A resistance element is inserted between the input and the output of a pair of inverter circuits which are cross-connected to the memory cells.

[Action]

According to the present invention, the resistance element inserted between the input and the output of the pair of cross-connected inverter circuits expands the voltage amplitude of the storage node of the memory cell, and reduces the potential of the storage node due to α-ray incidence. Inversion of data is less likely to occur.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
In the figure, 1 and 2 are normally-on type MESFETs, 3 to 6 are normally-off type MESFETs, and R1 and R2 are resistance elements formed without using an active region on a substrate.

The normally-on type MESFET1 and the normally-off type MESFET3 constitute a first E / D inverter circuit in which the normally-on type MESFET1 is a load, the normally-off type MESFET3 is a driver, and the input is a node 21 and the output is a node 8 and is a normally-on type. MES
The drain of the FET1 is connected to the power supply node 7, and the gate and the source are connected in common to the drain of the normally-off type MESFET3. Further, the normally-off type MESFET 3 has a gate connected to the input node 21 and a source connected to the ground potential. Similarly, normally-on type MESFET2 and normally-off type M
The ESFET4 constitutes a second E / D inverter circuit in which the normally-on type MESFET2 is a load, the normally-off type MESFET4 is a driver, and the input is a node 22 and the output is a node 9, and the drain of the normally-on type MESFET2 is a power supply node 7 Normally-off type MESFET4 with common gate and source
Connected to the drain of. Also, normally-off type MESFET
The gate of 4 is connected to the input node 22, and the source thereof is connected to the ground potential.

Further, the normally-off type MESFET 5 is a transfer gate, which is connected between the storage node 8 and the bit line 10, and the gate becomes the word line 12. Similarly, the normally-off type MESFET6 is also a transfer gate and is connected between the storage node 9 and the bit line 11, and the gate is a word line.
Twelve.

Further, R1 and R2 are resistance elements formed of, for example, a high resistance material without using an active region, and R1 is an input node 21 of the first E / D inverter and an output node of the second E / D inverter. R2 is connected between the input node 22 of the second E / D inverter and the output node 8 of the first E / D inverter.

Next, the operation will be described. When the memory cell is in the non-selected state, the word line 12 becomes Low level and both the transfer gates 5 and 6 become non-conductive as described in the conventional example, so the memory cell is disconnected from the bit lines 10 and 11. Be done. At this time, the level of data held in the storage node of the memory cell is determined as follows.

Let us assume that the storage node 8 is at a low level.
At this time, the node 22 also becomes Low level, so the driver FET4
Becomes non-conductive. Therefore, the storage node 9 is loaded
It is pulled up by FET2. If the potential of the power supply node 7 is 1.5V, the level of the node 21 is about 0.6V because it is limited by the height of the parasitic barrier of the parasitic diode between the gate and source of the driver FET3.
At this time, there is a through current that flows from the power supply 7 to the ground potential through the load FET2, the resistor R1, and the gate-source Schottky diode between the driver FET3, and therefore the potential of the node 9 is higher than 0.6V of the node 21. Become. That is, the through current is _IL (A), and the resistance values of the resistors R1 and R2 are R
(Ω), the potential V (9) of the node 9 becomes V (9) = V (21) + I _L R ≈0.6 + I _L R (V), which is higher than the potential of the node 21 by I _L R. Further, the Low level of the node 8 is almost at the ground potential as in the case of the conventional example because the driver FET 3 is sufficiently conductive.

In this way, the level of retained data in the non-selected state is
High level is 0.6 + I _L R (V), Low level is almost 0 (V)
The voltage amplitude is I _L R (V) compared to the conventional memory cell.
Only expanded. Moreover, the voltage amplitude can be adjusted by changing the resistance value R. When the voltage amplitude is expanded, even if the potential of the storage node on the High side decreases due to the incidence of α rays, the probability that it drops below the potential on the Low side (almost ground potential) decreases, and therefore the memory cell The probability that the data in 1 is inverted is reduced.

Further, when the gate capacitance of the driver FETs 3 and 4 is C (F), the time constant of the potential change of the nodes 21 and 22 becomes RC (s), and accordingly, the potential change of the storage node 8 or 9 reaches the node 22 or 21. It takes about RC (s) time to be transmitted. The inversion of the data of the memory cell occurs when the potential change of the node 8 or 9 is transmitted to the node 22 or 21, but the α ray is incident due to the time constant RC (s) and the potential of the node 8 or 9 is changed. Since the node 22 or 21 does not change immediately even when the voltage drops, the probability that the level of the node 8 or 9 will be restored to the original level by the charging of the load FET 1 or 2 during that time increases. Since the resistors R1 and R2 are formed without using the active region in the substrate, the electrons generated in the substrate due to α-ray incidence are not directly collected in the nodes 21 and 22, and therefore the nodes The potential of 21,22 does not drop sharply.

As described above, by forming the resistors R1 and R2 without using the active region, the voltage amplitude of the held data can be expanded and the time constants of the gate nodes 21 and 22 of the driver FET can be increased at the same time. It is possible to increase resistance to soft errors due to lines.

Since the current consumption of the memory cell is determined by the current values of the load FETs 1 and 2, the insertion of the resistors R1 and R2 does not increase the power consumption.

Further, the operation of reading data from the memory cell and the operation of writing data to the memory cell are similar to those of the conventional circuit.

Further, in the above-mentioned embodiment, the memory cell in which the load is a normally-on type MESFET common to the gate and the source has been described, but this may be a resistance load type memory cell as shown in FIG. Has the same effect as.

〔The invention's effect〕

As described above, according to the gallium arsenide semiconductor memory integrated circuit of the present invention, since the resistance element is inserted between the input and the output of the pair of inverter circuits which are cross-connected, the voltage of the data held in the memory cell is reduced. The amplitude can be widened, the noise margin is widened, data inversion due to incidence of α rays is less likely to occur, and soft error resistance is improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a memory cell of a gallium arsenide semiconductor memory integrated circuit according to an embodiment of the present invention, and FIG. 2 is a circuit showing a memory cell of a gallium arsenide semiconductor memory integrated circuit according to another embodiment of the present invention. Configuration diagram, FIG. 3 is a circuit configuration diagram showing a memory cell of a conventional gallium arsenide semiconductor memory integrated circuit, and FIG. 4 is a diagram showing transfer characteristics of an E / D inverter in the memory cell of a conventional gallium arsenide semiconductor memory integrated circuit. Is. In the figure, 1 and 2 are normally-on type MESFETs, 3 to 6 are normally-off type MESFETs, 7 is a power supply node, 8 and 9 are storage nodes, 10 and 11 are bit lines, 12 is word lines, and 21 and 22 are driver FETs. The gate nodes, R1 to R4, are resistance elements. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A normally-off MESFET formed on a gallium arsenide semiconductor substrate and having a source connected to a second power supply, and a load element connected between the drain of the MESFET and the first power supply. And a flip-flop type circuit having a pair of inverter circuits each having a gate of the MESFET as its input node and a drain as its output node, and connecting one input node and the other output node of the pair of inverter circuits, respectively. In the gallium arsenide semiconductor memory integrated circuit which constitutes the memory cell, the resistance element is inserted between one input node and the other output node of the pair of inverter circuits, respectively. .