JPH0461095A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the probability of inverting a data since alpha-rays are made incident without increasing the number of elements and without increasing energy consumption by using elements having negative resistance as load element. CONSTITUTION:As the load elements of inverters INV1 and INV2, the negative resistance elements such as Esaki diodes 1 and 2, for example, are used. For the Esaki diode 1, the anode is connected to a second power source 7 and the cathode is connected to a memory node 8. For the Esaki diode 2, the anode is connected to the second power source 7 and the cathode is connected to a memory node 9. Thus, since the elements having a negative resistance characteristic are used as the load elements, without increasing the number of elements constituting a memory cell and without increasing the energy consumption, it is possible to the probability of inverting the data since the alpha-rays are made incident.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to the structure of a memory cell thereof.

[Prior Art] Conventionally, as a memory cell in a semiconductor memory device, a flip-flop consisting of two cross-connected inverters has been used.
international Electron De
It is described on page 83 of the proceedings of viceMeeting (IEDM). As shown in Figure 4, this is a normally-off metal-semiconductor field effect transaster (MES).
FET) as a driver, normally-on type MESFET
It has two inverters with a load of .

That is, 3 is a normally-off type MESF that is a driver.
The ET has its common electrode, e.g. source, connected to a first power supply, e.g. ground potential, and its output electrode, e.g. train, connected to output node 8. This output node 8
are connected to the source electrode and gate electrode of the normally-on MESFET 15 serving as a load. Also, this ME
The train of SFETs 15 is connected to a second power supply 7, e.g. +V
It is connected to the. These MESFETs 3.15 provide one enhancement/dupression (E/D
) An inverter INVI is configured, and an E/D inverter INV2 having an output node 9 is similarly configured by a normally-off type MESFET 4 serving as a driver and a normally-on type MESFET 16 serving as a load. The output node 8 of the inverter INV1 is connected to the control electrode, for example the gate, of the MESFET 4 connected to the input node of the inverter INV2,
The output node 9 of V2 is connected to the control electrode, eg, the gate, of MESFET 3, which is connected to the input node of the inverter INV, thereby forming a flip-flop. Hereinafter, the output node will be referred to as a storage node. In addition, in the same figure, 10. 1.1 is the bit line, 12 is the word line [5,
Reference numeral 6 denotes a transfer gate constituted by a normally-off type MESFET. Note that this memory cell is
It is formed on a gallium arsenide semiconductor substrate.

In this memory cell, in the non-selected state, the word line]2 or L level, transfer gates 5.6 are both non-conductive, and storage node 8.9 is electrically connected to bit line 10.11. It is difficult to cut. At this time, a pair of data at H and L levels is held in the memory cell in the following manner.

For example, when the input voltage to the gate of driver MESFET 3 is at L level, MESFET 3 becomes non-conductive, so the voltage at storage node 8 is pulled up to H level by load MESFET I5. For example, set +V to 1
v, the voltage of the storage node 8 is about to be raised to IV, but the voltage of the storage node 8 is increased by the voltage of the other inverter INv2.
4 (7) Since the gate voltage is supplied, the voltage of the storage node 8 is clamped to about the Schmittky barrier height Φ6 due to the presence of the parasitic Schottky diode formed between the gate and source of the MESFET 4. Usually, this clamp value is about 0.6v. Next, INV
The input voltage to I increases and the driver MESFET3
When the threshold value is exceeded, the driver MESFET 3 becomes conductive. Normally, the current driving capability of the driver MESFET 3 in the conductive state is set to be several times larger than the current driving capability of the load MESFET 15, so the voltage of the storage node 8 rapidly drops to the L level. When the input voltage increases further, the driver MESF
The parasitic Schottky tie formed between the gate of ET3 and the train starts conducting, and current starts to flow from the input node of INVI to the storage node 8.
voltage is gradually increased. In this way, the transfer characteristic of the inverter INVI in the non-selected state becomes as shown by the solid line 17 in FIG.
The transfer characteristics of No. 2 are also similar. However, inverter I
The storage node 8 of NVI is connected to the input node of inverter rNV2, and the input node of inverter 1NV2 is
The inverter I is connected to the storage node 8 of the inverter INVI, i.e. cross-connected to the inverter I
Assuming that the transfer characteristic of NVI is a solid line 17, the transfer characteristic of inverter INV2 is represented by a broken line 18 which is the solid line 17 folded back symmetrically with respect to y=x, and the voltage of storage node 8.9 in the non-selected state is at a stable point. The intersection points A and B of the solid line 17 and the broken line 18 are determined. That is, storage node 8
．． 9 holds data of a pair of H and L levels.

To read data from memory cells, set the word line I2 to H.
This is done by setting the memory cell in a selected state as a level, thereby making transfer gate 5.6 conductive, and outputting the held data to bit line 10.11. The data read onto the bit lines 10 and 11 is further amplified by a subsequent circuit (not shown) and output to the outside. To write data to a memory cell, the word line 12 is set to H level to put the memory cell in a selected state, and the bit lines 10 and 11 are set to H level and the other to L level by a write circuit (not shown). This is done by transmitting the data on bit line 10.11 to storage node 8.9 of the memory cell.

[Problem B to be Solved by the Invention] In the above memory cell, the H level of data held in the memory cell is limited by the Schottky barrier height Φ8 between the gate and source of the driver MESFET 3.4, The voltage will be approximately 0.6 V. Therefore, the voltage amplitude of the data held in the memory cell is small, and there is a problem that soft errors are likely to occur due to the incidence of alpha rays.

That is, in general, MESFETs have an active region in which impurities are mixed in a gallium arsenide semiconductor substrate, and when this active region is at a high potential, electrons generated in the semiconductor substrate by the incidence of alpha rays are absorbed by this high potential. collected in the active area of Therefore, when α rays are incident on the active region of the storage node at the H level of the memory cell, electrons are collected at this node and the potential is lowered. This reduction is usually 0.6
It becomes a value exceeding V, and is lower than the potential of the storage node which is at H level or the potential of the storage node which is at L level. As described above, the memory cell is constituted by a flip-flop, and if the above-mentioned potential reversal occurs even momentarily in such a flip-flop, the data will be inverted and cannot be recovered. Such data inversion will not recover until the next data is written, and will cause malfunction when actually used.

As a method for reducing the probability that data is inverted due to the incidence of α rays, for example, as shown in FIG.
．． It is known to add a capacitive element 19, 20 between the capacitor 9 and the ground potential. As a result, the capacitance value of the storage node 8.9 increases, and the decrease in the potential of the storage node due to electrons collected upon incidence of α rays can be reduced. However, by adding a capacitive element, the number of constituent elements of the memory cell increases, and the area of the memory cell also increases. Generally, in a memory chip, the memory cells occupy the largest area, so in order to reduce the chip area, it is necessary to reduce the area of the memory cells. However, adding a capacitive element as described above increases the chip area, which is undesirable from a manufacturing cost standpoint.
This becomes an obstacle to miniaturization.

As a method of increasing the resistance to α rays without increasing the number of elements, for example, increasing the current drive capability of the load MESFETs 15 and 16 can be considered. In other words, Figure 7 shows the load characteristics of the load MESFET 15.16, which is a normally-on type MESFET with a common gate and source.
Since the load is composed of SFETs, the load characteristics are saturated, as is clear from the figure, and this saturation current becomes the holding current of the memory cell. Load M E S F E T I5
．． If the holding current of 16 is increased, the ability to raise the potential of the storage node to a higher side will be improved, and the reduction in the level of the storage node will be alleviated against the collection of electrons due to the incidence of alpha rays, resulting in data inversion. The probability of However, this requires an increase in the holding current of the memory cell, which increases the power consumption of the memory cell. In general, in order to reduce the power consumption of a memory element, it is necessary to suppress the power consumption of each memory cell as much as possible. Therefore the load MESFET15
．． Increasing the current drive capability of 16 is not preferable from the viewpoint of reducing power consumption.

The present invention has been made to solve the above-mentioned problems, and is capable of inverting data due to incidence of alpha rays without increasing the number of elements or increasing power consumption. The purpose is to obtain a memory cell with reduced probability.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a memory cell having a flip-flop in which the input node and the output node of the first and second inverter circuits are respectively cross-connected. and the first and second inverter circuits each have a control electrode connected to the input node, an output electrode connected to the output node, and a common electrode connected to the first power source.
In a semiconductor memory device having a load element connected between the output node and a second power supply, an element having negative resistance is used instead of using I''ET as the load element. be.

[Function] According to the present invention, as described above, a load element having negative resistance characteristics is used. Therefore, the details will be described later, but whether the output node (storage node) of the inverter
At the high level, the voltage at the output node becomes a voltage near vH in the inverter load characteristic 13 of FIG. 3, and the holding current for maintaining the high level is very small. Further, when the output node of the inverter is at L level, the voltage at the output node becomes VL on the load characteristic 13 shown in FIG. 3, and the holding current for maintaining it at L level is also very small. Also,
In a state where the output node is at H level, when the potential of the output node decreases due to the incidence of alpha rays, the current increases in accordance with load characteristic 13, so the current drive capability increases, and the voltage at the output node goes to H level. maintained.

Embodiment As shown in FIG. 1, this embodiment has the same structure as the conventional one described above, except that the load element is changed to a negative resistance element, for example, an Esaki diode 1.2. Equivalent parts are given the same symbols.

The explanation will be omitted.

The Esaki diode 1 has its anode connected to the second power supply 7 , +V, and its cathode connected to the storage node 8 . Similarly, the Esaki diode 2 has its anode connected to the second power supply 7 and its cathode connected to the ta-It node 9.

By the way, the Esakita autos 1 and 2 have voltage-current characteristics as shown in FIG. 2, as is well known. That is,
When the forward voltage increases, a tunnel current initially flows and the current increases, but when the forward voltage reaches the peak voltage vP, for example 0.2 to 0.3V, The peak current becomes 1p, and if the forward voltage increases after this,
The current is decreasing. Furthermore, when the forward voltage increases and exceeds the valley point voltage vv, for example 0.3v, a diffusion current begins to flow, the current starts to increase again from the valley point current Iv, and thereafter increases monotonically. Therefore, the forward voltage exhibits a negative resistance characteristic in which the current decreases as the forward voltage increases from the peak voltage VP to the valley voltage Vv.

Esaki diode 1 having such negative resistance characteristics,
Inverter INV1.2 using INV1.2 as a load element. IN
The operation of V2 is determined by inverter INV1.V2 shown in FIG. ．．
INV2 load characteristic curve 13 and driver characteristic curve 14
This will be explained with reference to. Note that the load characteristic curve 13 is
This corresponds to the voltage-current characteristic shown in Figure 2, which is reversed.
The point of voltage VH in FIG. 3 corresponds to the origin at 8 in FIG. 2, and vL in FIG. 3 corresponds to the valley point voltage v in FIG.
Corresponds to v. Note that the voltage V. is equal to the power supply voltage +V.

Here, for example, when the storage node 9 is at the L level, the gate of the inverter INv1 node y<-MESFET3 is also at the L level, and this MESFET3 becomes non-conductive. At this time, the potential difference between both ends of the Esaki diode l is O
Therefore, the voltage at storage node 8 is raised to +V, that is, to V□ shown in FIG. This I is MESFET4
Since the value is higher than the Schottky barrier height Φ8, the storage node 8 maintains the H level even if the voltage of the storage node 8 is input to the gate of the MESFET 4.

Further, when the storage node 9 is at H level, the gate of MESFET 4 also goes to H level, MESFET 3 becomes conductive, and the driver characteristics shown by reference numeral 14 in FIG. 3 are obtained.

Here, the current drive capability of the driver MESFET 3 in the conductive state is expressed as the peak value current IP of the Esaki tie auto 1.
If it is set sufficiently larger, the voltage of the storage node 8 is determined to be the intersection of the driver characteristic 14 and the load characteristic 13, in this example, the valley point voltage of the Esaki diode l, and becomes vL, that is, the L level. becomes. The current at this time,
That is, the holding current can also be suppressed to a small valley point current Iv. In this way, when the input level is H level, the output level is L level, and when the input level is L level, the output level is H level, and the inverter characteristics are similar to the conventional inverter shown in FIG. Also, in the inverter INV2, when the storage node 8 is at the L level, the storage node 9 goes to the H level, and when the storage node 8 is at the H level, the storage node 9 goes to the L level. Such inverters INVI, I NV
The memory cell configured by cross-connecting two cells also has two stable points, as in the conventional one, and holds one pair of data at H and L levels. Furthermore, the holding current can be made similar to the conventional one by appropriately setting Iv. Reading and writing data to and from memory cells can also be performed in the same manner as in the prior art.

For example, if we consider the case where α rays are incident near the storage node 8 while the storage node 8 is at H level, the electrons generated by the incidence of the α rays will be used to store the high potential memory. The signal is collected to the node 8 and decreases from the H level of the storage node 8, that is, ①o. For example, if the voltage drops to V as shown in FIG. 3, the Esaki diode 1 will have ■□-v14. A forward voltage of is applied, and Esaki diode 1 causes a current of I□ shown in FIG. 3 to flow to storage node 8. Immediately, the current drive input increases, and as a result, the H level of storage node 8 is suppressed from decreasing. memory node 9
Even if α rays are incident when the H level is high, the decrease in the H level is similarly suppressed. Therefore, even if α rays are incident, the probability of data inversion occurring can be reduced.
It is possible to increase the resistance of memory to alpha rays.

In the above embodiment, an Esaki diode was used as the negative resistance element, but other negative resistance elements may be used as long as they have negative resistance characteristics. Further, in the above embodiments, the present invention was applied to a memory device formed on a gallium arsenide semiconductor substrate, but the present invention can also be applied to a memory device formed on other semiconductor substrates.

[Effects of the Invention] As described above, according to the present invention, by using a load element having negative resistance characteristics as a load element of a semiconductor memory device, consumption can be reduced without increasing the number of constituent elements of a memory cell. The probability of data inversion due to incidence of alpha rays can be reduced without increasing power.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a voltage-current characteristic diagram of an Esaki diode, and FIG. 3 is a diagram showing load characteristics and driver characteristics of an inverter circuit in this embodiment. , S4 is a circuit diagram of a memory cell of a conventional semiconductor memory device, FIG. 5 is a diagram showing the transfer characteristics of an inverter of a conventional memory cell, and FIG. 6 is a diagram of a conventional memory cell with a capacitance loaded. The circuit diagram, FIG. 7, is a diagram showing the load characteristics of a load FET in a conventional memory cell. 1.2...Esakita Auto, 3.4...ME
SFET (FET), 8.9...output node, I
NVI, 1NV2...Inverter. Leap

Claims (1)

[Claims] (1) Form a memory cell having a flip-flop in which the input node and the output node of the first and second inverter circuits are respectively cross-connected, and the first and second inverter circuits each connect the control electrode to the In the input node,
A semiconductor memory device comprising an FET having an output electrode connected to the output node and the common electrode connected to a first power source, and a load element connected between the output node and a second power source, wherein the load element is connected to the first power source. , a semiconductor memory device comprising an element having negative resistance.