JPH02177190A - Memory device - Google Patents

Abstract

PURPOSE:To reduce the size of a memory device and at the same time to improve the packing density with reduction of the total number of terminals by sharing the address and data terminals. CONSTITUTION:The data terminals D0 - D7 and the address terminals A0 - A7 are used as the address/data shared terminals 2. At the same time, the functions of the terminals 2 are switched synchronously with the signal received from a chip selection terminal (the inverse of CS) which urges the function of a static memory 1. In other words, the terminals 2 function as the address terminals in an inactive state where no chip selection signal, the inverse of CS is supplied. While the terminals 2 function as the data terminals in an active state where the signal, the inverse of CS is supplied. In such a constitution, the number of terminals in decreased to obtain a compact memory device together with improvement of the packing density.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device, and particularly to a memory device equipped with address terminals and data terminals.

[Conventional technology]

Conventionally, this type of memory device, whether static or dynamic, has dedicated terminals for address and data, respectively.

FIG. 7 is a terminal diagram of a static type memory device showing an example of such a conventional memory device.

As shown in FIG. 7, the static type memory device 1' has address terminals (A14 to o), data input/output terminals (D7 to
o), the power supply terminal (Vcc) and other various control terminals (WE, etc.) are also formed as single-function terminals 3.

For example, 262144 is a typical example of such a memory device.
Taking a bit static type memory device as an example, the number of terminals thereof has the following relationship.

(2 (number of address terminals)) × (number of data input/output terminals) -
(Total number of bits of memory device) ...(1) +17%
++ Note that here indicates a power.

The static memory device described above has data input/output (D
8 terminals for address input (A+) and 15 terminals for address input (A+), a total of 23 terminals are required, and the above (1
) also constructs the above-mentioned 262144-bit memory.

FIG. 8 is a circuit diagram of the memory device in FIG. 7.

As shown in FIG. 8, this memory circuit includes a static memory cell array 4, a column decoder 5 and a row decoder 6.
, read/write buffer 7, and memory cell array 4
-H latch of information to be accessed ii'8
8 A to 8C, output buffer, and address terminal A7
~0+A14~8 and data input/output terminal D7~. It also has WE, ○E terminals, etc. for writing and output control.

All input/output and control terminals in such a memory circuit are represented as single functional terminals 3 shown in FIG. Address information from address terminals A14-8 and A, -0 is sent to column decoder 5 and row decoder 6 via latch circuits 8A and 8B, respectively, and is applied to arbitrary memory cells in memory array 4 arranged two-dimensionally. used to select. In addition, in the write cycle, the address and data are latched in synchronization with the signal (WE>) that controls the write operation so that the write data and address do not change while the memory cell write operation is being performed. Note that the chip select signal (CS) is a signal for selecting whether or not to enable control by WE and OE, so it is omitted here.

Further, FIG. 9 is a terminal diagram of a dynamic memory device showing another conventional example.

As shown in FIG. 9, this dynamic memory device 5 adopts an address multiplex system, and the terminal arrangement of the memory device 10' is similar to the conventional example shown in FIG. , and the data terminal is arranged only for data. That is, each terminal is used as a single-function terminal 3.

For example, if we take a 262,144-bit address multiplex type dynamic memory device as a typical example of this memory device, since the address is time-divisionally input, the address terminals can be divided into 1/(the number of divisions). You can save money. In general, memory devices that use an address multiplexing method with many inputs divided into two addresses, such as 262144, which performs data input/output in units of 4 bits.
A BIT memory device requires a total of 12 terminals, 4 terminals for data input/output (Dl) and 8 terminals for address input (A1).

FIG. 10 is a circuit diagram of the memory device in FIG. 9.

As shown in FIG. 10, the circuit that is different from the circuit shown in FIG. 8 described above is a dynamic memory cell array 11, a sense amplifier/write buffer 12, a column address strobe signal (CAS), and address terminals A115. , D3~
0 and how to use the WE flaw signal.

In other words, when RAS falls, the lower address A7
~0 is latched, and then the upper addresses A15-B are latched at the same terminals A15-0 at the falling edge of <CAS. These addresses are sent to the row decoder 6 and column decoder 5, and are used to select arbitrary memory cells in the two-dimensionally arranged memory cell array. After latching this address, memory operations are performed by controlling WE in write cycles and by controlling OE in read cycles. In short, address terminal A15
~0 is used in two parts only when latching each address, but is not used until the end of the cycle thereafter.

Note that the above-mentioned state in which the address is latched means that the state of the input signal when latching is started continues to be output until the latching is released, and the state in which the address is not latched means that the state of the input signal when latching is started continues to be output until the latching is released. It is output in real time.

[Problems to be Solved by the Invention] Since the conventional memory device described above has dedicated address input terminals and data input/output terminals,
The disadvantage is that the number of terminals increases, making it difficult to downsize the entire device.

In particular, as the total number of bits of a memory device increases in the future, the number of terminals will also increase, so the package will inevitably become larger, and the problem of lowering the packaging density will become more prominent. This is a factor that prevents the goal of increasing the total number of bits of a memory device to improve packaging density.

An object of the present invention is to provide a memory device that reduces the number of such terminals, realizes miniaturization, and improves packaging density.

[Means to solve the problem]

A memory device according to the present invention has a function of inputting an arbitrary address and reading or writing data held by a memory cell corresponding to the address from among a plurality of memory cells. A shared terminal is provided that shares at least a part of the address terminal for reading or writing the data and at least a part of the data terminal for reading or writing the data, and the function of the shared terminal is switched in synchronization with an operation control clock. It is composed of

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a terminal diagram of a static memory device showing a first embodiment of the present invention.

As shown in FIG. 1, the static memory device 1 of this embodiment has the same memory capacity as the conventional example explained in FIG. 7, except for data terminals (Do to D?) and address terminals. (Ao to A7) are used as address/data common terminals 2, and switching of the terminal functions of the common terminals 2 is synchronized with a signal from a chip select terminal (CS) that prompts the operation of the memory device 1. That is, in an inactive state where this chip select signal (C3) is not supplied, it functions as an address terminal, and this C8
When a signal is supplied to the terminal and it is in the active state, it functions as a data terminal.

FIG. 2 is a circuit diagram of the memory device in FIG. 1.

As shown in FIG. 2, compared to the conventional memory circuit explained in FIG. 8B is driven by a chip select signal (CS). That is, address terminals AI4~
0 is used to select each memory cell of the memory cell array 4 as in the conventional example explained in FIGS. 7 and 8, but addresses A7-0 and data D7-. The shared terminal 2 latches the address at the falling edge of the chip select signal C8 that enables control by WE and OE, and thereafter functions as a data terminal until C8 rises. Other operations are similar to the conventional example explained in FIG.

FIGS. 3(a) and 3(b) are operation timing diagrams for explaining reading (read cycle) and writing (write cycle) of data in the memory circuit shown in FIG. 2, respectively.

As shown in FIG. 3(a), in the read cycle of such a memory circuit, an address (A o to 14) and a chip select signal are supplied at an appropriate time <1+), that is, at the fall time of C8 mentioned above, After that, the common terminal (A7
~O/D7~. )2 to high impedance (HI-Z)
shall be. Next, the output enable signal (OE
), data (D7-0) is output from the common terminal 2 at an appropriate time (t2).

Further, as shown in FIG. 3(b), in the write cycle, the address (A0~+4) and chip select signal are supplied at an appropriate time (t3), and then the common terminal (A7
~o/D7~. ) is write data (Do~7)
At time t4, the write enable signal (W
Writing to the static memory cell 4 is performed by supplying E).

FIG. 4 is a terminal diagram of a dynamic memory device showing a second embodiment of the present invention.

As shown in FIG. 4, the dynamic memory device 10 of this embodiment has the same memory capacity as the conventional example explained in FIG. (Ao=As> and address/data common terminal 2
In addition, the switching of the terminal function of the common terminal 2 is performed in synchronization with the RAS signal, CAS signal, etc. of the memory device 10. That is, in an inactive state where such a CAS signal is not supplied, it functions as an address terminal, and in an active state where such a CAS signal is supplied, it functions as a data terminal.

FIG. 5 is a circuit diagram of the memory device in FIG. 4.

As shown in FIG. 5, when compared with the conventional memory circuit explained in FIG.
s~o)/data (Ds"o) common terminal 2 is provided, and this is latched by CAS. In other words, the address terminals A6~3 after address latching are connected to the data terminal Do.
It is also used as ~3, and in the write cycle described later, RA
S.

Since the latch timing is determined by CAS and WE, these signals are controlled to switch the terminal function according to the address and write data given to the shared terminal 2.

FIGS. 6(a) and 6(b) are operation timing diagrams for explaining the reading (read cycle) and writing (write cycle) of data in the memory circuit shown in FIG. 5, respectively.

As shown in FIG. 6(a), in the read cycle of such a memory circuit, the address (A o
~3. A4-7) and row address strobe signal (
RAS), and then at time (t6) address (A
8 to 11+AI2 to 15) and a column address strobe signal (CAS). After that, at time t7, after setting the common terminals (Ao~, /Do~3) 2 to a high impedance state (HI-Z), when the output 1~ enable signal (OE) is supplied, the data (Do~3)
is output from the common terminal 2.

Further, as shown in FIG. 6(b), in the write cycle, the address (A o~3A4~7) and RAS are supplied at time (t8), and the address (A s~3A4~7) is supplied at time (t9).
, A12~,5) and the CAS signal is supplied to the common terminal (Ao~3/Do~3 at the subsequent time (t+o)).
)2 is switched to write data (Do to 3), and writing to each memory cell of the memory cell array 11 is performed by supplying a write enable signal (WE).

Two embodiments have been described above, and in these two embodiments, it is possible to realize a memory device with fewer terminals by 8 or 4 terminals, respectively, compared to a memory device that conventionally required 28 terminals or 18 terminals. . In addition,
Any combination of sharing an address terminal and a data terminal will not change the effect.

〔Effect of the invention〕

As explained above, by sharing address terminals and data terminals, the memory device of the present invention can reduce the total number of terminals, realize miniaturization of the device, and improve packaging density. There is an effect that it can be done. Note that there is no limit to the number of terminals, and this effect can be adjusted by determining the number of terminals to be shared as necessary.

[Brief explanation of the drawing]

FIG. 1 is a terminal diagram of a static memory device showing a first embodiment of the present invention, FIG. 2 is a circuit diagram of the memory device in FIG. 1, and FIGS. 4 is a terminal diagram of a dynamic memory device showing a second embodiment of the present invention, and FIG. 5 is an operation timing diagram for explaining the read cycle and write cycle of the memory circuit shown in FIG. Circuit diagram of the device, Figure 6 (a
＞, (b) are operation timing diagrams for explaining the read cycle and write cycle of the memory circuit shown in FIG. 5, respectively. FIG. 7 is a terminal diagram of a static type memory device showing an example of a conventional memory device. FIG. FIG. 7 is a circuit diagram of the memory device, FIG. 9 is a terminal diagram of a dynamic memory device showing another example of the prior art, and FIG. 10 is a circuit diagram of the memory device shown in FIG. 1.10...Memory device, 2...Address/data common terminal, 3...Single function element, 4.11...Memory cell array, 5...Column decoder, 6...Row decoder, 7...Read/write buffer, 8A to 8C...
- Latch, 9... Output buffer, 12... Sense amplifier/write buffer. Agent Patent attorney Susumu Uchihara (α) (b): + こいんな（い５、j (b) ta tq あ 6 丙 め 1 傑q じ t , ツ 工; floz

Claims (1)

[Claims] In a memory device having a function of inputting an arbitrary address and reading or writing data held by a memory cell corresponding to the address from among a plurality of memory cells, at least one of the address terminals for inputting the address is used. A memory device characterized in that a shared terminal is provided that shares at least a part of the data terminal for reading or writing the data, and the function of the shared terminal is switched in synchronization with an operation control clock.