JPH07281993A - DMA device - Google Patents

Abstract

(57) [Summary] (Correction) [Configuration] The decoding unit 8 identifies the type of each data based on the attribute data added to each data forming the data sequence of the received frame, and stores the data in the buffer memory 4 as a unit. Store in area. The status and error information are also identified based on the attribute data and stored in a dedicated area other than the main body data provided in the unit storage area of the buffer memory 4. The DMA main body unit 7 stores the address stored in the next area address storage unit of the current transfer destination unit storage area in the base register 71 at the end of the transfer of one reception frame, so that it is used in the transfer of the next reception frame. The starting address of the unit storage area can be set in the base register without the intervention of the CPU 3. Further, it becomes possible to reset the address in the base register when an error occurs without intervention of the CPU. [Effect] The intervention of the CPU during the communication processing is reduced, and the communication speed can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control system, and more particularly, to a communication system (for example, bit-oriented protocol) in which a frame delimiter cannot be recognized from octet data, and between the serial interface and other resources. Easy interface,
It realizes highly efficient data transfer.

[0002]

2. Description of the Related Art As a conventional communication control system, a character transfer method (BYSYNC: Binary Synchronous Comm.
unication (BSC) was the most common. This is to express a binary numerical value by various characters known as ASCII code, and frame and transfer one octet (8 bits) as one unit of data. In the case of this transfer method, the character code is standardized,
Since each code indicates a different communication symbol, the break of data can be surely determined. However, there is a problem in terms of communication speed because the CPU on the receiving side reads each code while decoding it by software. For example, this character transfer can support up to about 9600 bps, but today's popular LAN (10 Mbps).
At ~ 16 Mbps), there is a lot of data zeroing, and the processing cannot catch up.

Therefore, today, in order to be compatible with LAN, HDLC (High-level Data Link Control proced
The bit-oriented protocol including the (ure) method was developed. In this HDLC method, FIG.
As shown in, a data string having 1 octet as one unit of data constitutes one frame, and a predetermined 8-bit code “01111110” called a flag is connected to the beginning and the end of one frame, In the meantime, data consisting of a specific code will be connected.

FIG. 4 illustrates a conventional HDLC system configuration, and FIG. 5 illustrates an operating state thereof. In this figure, 301 is a data bus, 302 is an address bus, and these buses 301 and 302 are
The CPU 303, the buffer memory 304, the communication controller 305, and the DMA circuit 306 are connected. The communication controller 305 includes a data register 3051 and a status register 3052, and the data sequence of the received frame is sequentially stored in the data register 3051 and the status data is stored in the status register 3052. The DMA 306 includes an address register 3061 and a length register 3062. The address register 3061 stores the start address of the frame data storage area in the memory 304 by the CPU 303, and the length register 3062 stores a data string of the frame data. It has become so.

As shown in FIG. 4, the communication controller 30
The DMA transfer is performed in parallel with a slight delay after the reception of the frame of No. 5. When one DMA transfer is completed,
The CPU 303 executes the above-mentioned code conversion processing, error detection processing, length confirmation processing, and the like. After this processing is completed, the communication controller 305 shifts to the input of the reception frame 2, and the DMA transfer 2 is started after the start thereof.

That is, when the communication controller 305 detects the start delimiter of the received frame, it starts storing in the body data register 3051 for each data of the following access control, frame control, destination address, source address and information field, D
When the transfer to the register 3051 is possible up to the MA transferable amount, the DMA request signal DREQ is sent to the DMA circuit 306.
Give to. Next, the communication controller 305 will store the status of the received frame in the status register 3052.

The DMA circuit 306 is the communication controller 30.
When receiving the DMA request signal DREQ from 5, the communication controller 305 transmits the DMA permission signal DACK to the communication controller 305. After that, the DMA circuit 306 starts to transfer the data in the data register 3051 to the memory 304 as soon as the bus use right is secured. When the transfer of the data in the data register 3051 is completed, the DMA circuit 306 stores the data length counted during the transfer in the length register 3062, and finally transmits the EOP signal to the CPU 303.
Then, the CPU 303 performs necessary processing, and the reception processing for one frame ends.

In the case of the HDLC system, the data is stored in the memory as it is, so that the communication at a higher speed than that of the character system is possible.

However, the software processing by the CPU 303 causes a decrease in communication speed.

The processing of the CPU 303 is the following processing. (1) Status register 3 of communication controller 305
Read error information and status information from 052. (2) Data length register 30 in the DMA circuit 306
Read length data from 62. (3) Storing the start address of the unit storage area to be used next in the memory 304 in the base address register 3061. (4) When a DMA transfer error occurs, the base address register 3061 stores the unit storage area start address used in the transfer in which the error occurred. (5) Code conversion processing (delimiter processing) when there is data in the communication data that matches the flags (start delimiter, end delimiter) added to the front and rear ends. In other words, if the data that matches the flag is transferred as it is, it may be recognized as a flag. Therefore, the code is converted by a specific method and then sent, and the receiving side stores all the data in the memory and then stores it. The data is inspected by software, and when the specific conversion data exists in the data, a process of returning the specific conversion data to the same data as the above-mentioned flag is executed.

If such software processing is frequently performed, the communication speed is also lowered, and although it can support LAN, to some extent, the latest communication methods such as optical Ethernet (100 Mbps) and ATM (156 Mbps). ), There is a lot of money to get rid of, and I can't deal with it very much. In short, the CPU 303 uses the buses 301, 3
02, the communication controller 305 becomes a reception dead period, and during that period, the communication controller 30
Since No. 5 cannot receive a frame, this would reduce the communication speed. CPU
As the processing executed by 303, in addition to the code conversion described above, the status register 30 of the communication controller 305 is used.
Address information 3061 of DMA 306 for reading status information from 52 and re-receiving when an error occurs
1 to 3 or 4 types of processing such as resetting to data, reading data length information from the length register 3062, setting processing to the address 3061 of the DMA 306 regarding the start address of the unit area of the memory 304 to be used next, and the like. Since it is performed every time, the communication speed decreases. Also, CP
The processing capacity of U303 also becomes an overhead, and the effective data transfer capacity is also reduced. In particular, when short frames continuously arrive, the frequency of the resetting process increases, the CPU processing overhead increases in proportion to the frequency, and the effective performance remarkably decreases.

[0012]

As described above, the conventional H
When using the DLC method, the CPU is used every time a received frame is input.
However, in this case, the bus right is transferred from the communication controller to the CPU, the communication controller cannot use the bus, and the communication speed decreases.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide a DMA device capable of performing the above-mentioned processing without interposing CPU processing. To do.

That is, a specific object of the present invention is to, at the end of the transfer of one received frame, set the start address of the unit storage area used in the transfer of the next received frame in the buffer memory without the intervention of the CPU. Another object of the present invention is to provide a DMA device in which the base address register can be set.

Still another object is to, when an error occurs, set the head address of the unit storage area used in the transfer of the frame in which the error has occurred in the buffer memory to the CPU.
It is an object of the present invention to provide a DMA device that can re-set the base address register without any intervention.

Further, an object of the present invention is to perform a code conversion process (by the CPU) in the case where the communication data of the CPU has a match with the flags (start delimiter, end delimiter) added to the leading end and the trailing end. To make it unnecessary.

A further object of the present invention is to provide a DMA device capable of reading error information and status information from the status register of the communication controller without CPU intervention.

[0018]

The DMA device of the present invention is
A DMA main body that generates a transfer destination address corresponding to a data structure of a unit storage area provided in a predetermined capacity in the received frame storage buffer memory, and an attribute added to each data that forms the data string of the received frame The type of each data is identified by the data, and each data is stored in a predetermined area of the unit storage area based on the identification result, and after the end, the next area address of the current transfer destination unit storage area And a decoding unit for generating an access control signal to the DMA main unit so that the address data stored in the storage unit is written in the base address register.

The DMA main body section includes a base address register for storing the start address of the current transfer destination unit storage area which is the source of the transfer destination address, and the address stored in the next area address storage section of the current transfer destination unit storage area. It has a function of storing data in the base address register.

Further, the DMA main body unit includes an adder unit which outputs a predetermined value to the address value of the base register unit according to the access control signal to output as an address value corresponding to each area of the current transfer destination unit storage area. It can be configured to include.

The adder unit outputs a first adder which outputs an address value for a first area for storing a data string of a first field of a received frame in the unit storage area, and the reception in the unit storage area. Second of the frame
Second adder for outputting an address value for a second area for storing the data string of the field of
And an address switching unit for switching and outputting the output of the adder according to the memory access control signal, and a writing / reading control signal generating unit for outputting a writing / reading control signal for the buffer memory corresponding to the output of the address switching unit. It can be realized by

When the decoding unit identifies the first attribute data indicating the position of the body data of the received frame, the second memory access becomes the address output command and the write control signal output command of the body data storage area in the unit storage area. When the first control signal generating means for outputting a control signal and the second attribute data indicating the position of the status data of the received frame are identified, the address output of the status storage area and the length storage area in the current transfer destination unit storage area Second control signal generating means for outputting a second memory access control signal which is a command and write control signal output command, and a current transfer destination unit storage area used when storing a received frame next to the received frame in the buffer memory Next area address read control signal output command and write control signal output command Characterized in that a third control signal generating means for outputting a Seth control signal.

Further, the decoding unit detects the occurrence of an error in the data sequence forming the received frame, and at the time of detection, the start address of the current transfer destination unit storage area in the buffer memory is reset in the base address register. It is desirable to provide a fourth control signal generating means for providing a next area address read control signal output command and a write control signal output command in the unit storage area before the current transfer destination unit storage area.

The communication system of the present invention has a unit storage area provided by a predetermined capacity, and the unit storage area has a write area for each data type and a head address of the unit storage area immediately after the unit storage area in advance. A buffer memory having a stored read area and storing a data sequence of a received frame; and each of the data sequences that form the data sequence based on attribute data indicating the type of each data that constitutes the data sequence of the received frame. A communication controller for storing data in a data register provided for each type; and an address generating means for addressing each area of the unit storage area by adding a predetermined value to the stored value of the base register section, The base address is used so that the one or more unit storage areas are used according to the length of the data stored in the data register. Characterized in that it comprises a DMA controller for updating control register.

[0025]

In the DMA device of the present invention, since the type of each data is identified based on the attribute data added to each data forming the data sequence of the received frame, the data is the same as the flag. However, the code conversion processing by the CPU described above is unnecessary, and the communication speed can be improved accordingly.

Further, according to the present invention, the status and error information are also identified based on the attribute data and stored in a dedicated area different from the main body data provided in the unit storage area of the buffer memory. Therefore, the I / O reading process by the CPU is unnecessary, and the communication speed can be improved also from this point.

Further, when the transfer of one received frame is completed, the DMA main body section stores the address data stored in the next area address storage section of the current transfer destination unit storage area in the base address register. Therefore, at the end of the transfer of one received frame, the start address of the unit storage area used in the transfer of the next received frame in the buffer memory can be set in the base address register without CPU intervention.

Further, according to the present invention, it is possible to detect the occurrence of an error in the data sequence forming the received frame and reset the start address of the current transfer destination unit storage area in the buffer memory to the base address register at the time of detection. Therefore, when an error occurs, the start address of the unit storage area used in the transfer of the frame in which the error occurred in the buffer memory can be reset in the base address register without the intervention of the CPU. Therefore, the communication speed can be improved.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. 1 shows a configuration of a communication system having a DMA circuit according to an embodiment of the present invention.
Indicates the structure of transfer data to be processed. In this figure, 1 is a data bus, 2 is an address bus, and these buses 1 and 2 have a CPU 3 and a memory 4 respectively.
The communication controller 5 and the DMA circuit 6 are connected to each other, and the buses 1 and 2 are used as their shared buses. DMA
The circuit 6 has a built-in arbiter 54.
Is also a communication controller 5, a DMA circuit 6 and a CPU 4
It is supposed to arbitrate with the bus.

The CPU 3 controls the operation of the entire system in addition to this communication system, and is a PROM (not shown).
Various processes using the data in the memory 4 are executed according to the programs in the program. The memory 4 has a buffer area allocated for storing communication data, and each unit storage area has a buffer area next to the unit storage area as shown in FIG. 2A. A next area address storage unit 41 in which the start address is written, a status storage unit 42,
It has a length storage unit 43 and a main body data storage unit 44 for storing main body data, and the next area address storage unit 41, the status storage unit 42, and the length storage unit 43 have sufficient capacity to store each data. Then, the main body data storage unit 44 is set to a capacity such that all the data is stored as much as possible based on the average length of one frame and the surplus area does not become as large as possible, for example, about 256 bytes. .

Transfer data on the data bus 1 from another system is received by the communication controller 5. As shown in FIG. 2B, this transfer frame is composed of a reception data section and an attribute data section. The former is start delimiter information indicating the start of the frame, ADP (Automatic D).
ata Processing) access control information for the purpose of security that allows access only when it is legitimate, frame control information that is a transfer permission flag in the token passing method, destination address information indicating the transfer destination of the transfer frame, the transfer frame Address information indicating the transfer source of the data, an information field into which the main data is inserted, an error detection code for detecting an error such as garbled information field, end delimiter information indicating the end of the information field, data length and error It is composed of frame status information indicating a code and hardware status information indicating an operating state of the network, and these are connected in that order.
The attribute data part is composed of 2-bit data indicating the attribute of each data forming the data string of the main body data part,
"10" indicates that it is the head data of the data string following the start delimiter, and "00" indicates that it is continuous data connected between the head data and the tail data,
"01" indicates that it is the last data in the data string. Here, the attribute data “10” is added to the access control information, the attribute data “01” is added to the frame status information, and the attribute data “00” is added to other information.

The communication controller 5 has an attribute detecting section 55a.
To 55e and registers 51 to 53, the attribute detection unit 5
5a to 55e detect the type of the data string forming the received frame based on the attribute data in the received frame having the above-described configuration, and according to the result, sort the data and store it in the corresponding registers 51 to 53.

A data register 51, a status register 52 and a length register 53 are built in. When the communication controller 5 confirms the start delimiter information in this received frame, the access control data,
Frame control data, destination address data,
The source address data and the information field data are stored in the data register 51. Then, the communication controller 5
When detecting the end delimiter, stores the frame status data in the status register 52, and finally stores the length data of the data stored in the data register 51 in the length register 53.

As described above, the DMA circuit 6 stores the data of the registers 51 to 53 of the communication controller 5 in the unit storage area of the memory 4 via the data bus 1 after the reception frame input of the communication controller 5 is delayed.
The main body section 7 and the input decoding section 8 are generally configured. D
The MA main unit 7 plays the original role of the DMA, and includes a base register 71, an address counter 72, an adder 73,
75 and an address switching unit 74. The base register 71 includes the registers 51 to 51 of the communication controller 5.
The head address of the unit storage area when the data stored in 53 is stored in the memory 4 is stored. The adder 75 supplies a value obtained by adding “+3” to the address value of the base register 71 to the address counter 72 as a preset value. The address counter 72 increments this preset value. The adder 73 has internal DMA request signals DREQ2, -3,-from the input decoding unit 8 which will be described later.
In accordance with 4 and -5, "+1", "+2", "0", and "-256" are added to the output value of the base register 71, respectively. The address switching unit 74 outputs the output of the address counter 72 and the output of the adder 73 to the internal DMA request signal DREQ.
It is selectively sent to the address bus 2 in accordance with 1 to -5.

The input decoding unit 8 includes the communication controller 5
The DMA permission signal DACK0 is supplied to the communication controller 5 in response to the DMA request signal DREQ0. In response to the DMA permission signal DACK0, the communication controller 5 first refers to the contents of the data register 51 in the order in which they are written, and uses the first attribute data “10” of the received frame to indicate data 0 (access control). )
Recognizes that this is the first data of the received frame, and outputs the internal DMA request signal DREQ1. The DMA main body section 7 activates the write control signal WR in response to the internal DMA request signal DREQ1 to set the memory 4 in a writable state, and the address switching section 74.
Is set to the address output state from the address counter 72, and the DMA permission signal DACK1 is passed to the input decoding unit 8. The input decoding unit 8 receives the DMA permission signal DACK.
In response to 1, the DMA permission signal DACK0 is passed to the communication controller 5. Then, the input decoding unit 8 is the arbiter 5.
4 to send the bus request signal BREQ3.

The input decoding unit 8 decodes these pieces of information and outputs the internal DMA request signal DREQ1 when the received transfer frame is normal data for which reception is permitted.
Send to the MA body 7. Then, the DMA main body unit 7 sets the address switching unit 74 to transmit the address from the address counter 72, activates the write control signal WR to the memory 4 to prepare the data write preparation state, and then the internal DMA The permission signal DACK1 is supplied to the input decoding unit 8. The input decoding unit 8 is the DMA main unit 7
When the internal DMA permission signal DACK1 from the
The A permission signal DACK0 will be transmitted to the communication controller 5. Then, the DMA main body unit 7 supplies the address signal from the address counter 72 to the memory 4 via the address bus 2, reads the data from the data register 51 of the communication controller 5, and transfers this to the memory 4 via the data bus 1. It will be written.

When it is confirmed that all the data in the data register 51 is stored in the memory 4, the input decoding unit 8 subsequently confirms that the data is stored in the status register 52. Signal D
REQ2 is transmitted to the DMA main body section 7.

The input decoding unit 8 also outputs an internal DMA request signal DREQ2 to write the contents of the status register 52 in the memory 4. The DMA main body section 7 responds to the internal DMA request signal DREQ2, sets the address switching section 74 to the adder 73 side while maintaining the write control signal WR in the activated state, and at the same time, adds this adder 7
3 will be set to the addition state of "+1". As a result, the DMA main unit 7 transmits the “+1” output of the adder 73 to the address bus 2 and writes the contents of the status register 52 into the memory 4. Then, the input decoding unit 8 writes the contents of the length register 53 to the memory 4 by using the internal DM.
The A request signal DREQ3 is output. The DMA main body 7 is
The internal DMA request signal DREQ3 keeps the write control signal WR and the address switching unit 74 in the present state, and sets the adder 73 to the addition state of "+2". As a result, the DMA main body unit 7 transmits the address obtained by adding “+2” to the value of the base register 71 to the address bus 2,
The contents of the length register 53 will be written to the memory 4 through the data bus 1. Finally, the input decoding unit 8 outputs the internal DMA request signal DREQ4 in order to rewrite the base register 71. In response to the internal DMA request signal DREQ4, the DMA main body section 7 activates the read control signal RD while keeping the address switching section 74 in the output transmission state of the adder 73 to put the memory 4 into the read state and to the base register. 71 is set to the write enable state, and the adder 7
3 is set to the addition state of "+0". As a result, the base address data stored in the unit area of the memory 4 is stored in the base register 71 through the data bus 1. As a result, the DMA main unit 7
Means that the transfer processing of one received frame is ended, and at the end of the transfer processing, the input decoding unit 8 notifies the CPU 3 of the end of transfer of one frame by the EOP signal.

Next, the operation of the communication system configured as described above will be described in detail.

(1) When the data fits in the unit storage area (see FIG. 3A) When the communication controller 5 detects the start delimiter of the received frame, the communication controller 5 identifies the start delimiter and DMA that the received frame is input. The input decoding unit 8 of the circuit 6 is notified. After that, the communication controller 5 performs access control, frame control, destination address,
Each data of the sender address and the information field will be stored in the register 51.

Subsequently, the input decoding section 8 supplies the DMA request signal DREQ1 to the DMA main body section 7 in response to the notification.

The DMA main body section 7 sets the address switching section 74 to the address counter 72 side and activates the write control signal WR to prepare for data transfer to the memory 4, and then sets DACK1 to the input decoding section 8. Will be given. Then, the input decoding unit 8 outputs the bus request signal BREQ3 to the arbiter 54. The arbiter 54 alternately sets the bus right with the communication controller body 50,
Bus permission signal BACK to the communication controller body 50
2 and the bus permission signal BACK3 to the DMA circuit 6 are alternately output. And this bus permission signal BA
When CK3 is activated, the DMA main unit 7 reads the data of the data register 51 through the data bus 1. At this time, as shown in FIG.
Assuming that the unit storage area A1 is used, its head address is set in the base register 71.

Thereafter, the communication controller 5 and the DMA circuit 6
And 5 operate in parallel, and at this time, the arbiter 54 alternately sets the bus use right to the communication controller 5 and the DMA main body 6. Communication controller 5
The operations of the DMA circuit 6 and the DMA circuit 6 are as follows.

The communication controller 5 stores the received data string on the data bus 1 in the data register 51, the status register 52, and the length register 53 in the order of reception. That is, when the start delimiter is detected, as described above, the input decoding unit 8 thereafter causes the attribute data “0”.
While recognizing "0", the data is continuously fetched to the data register 51. In parallel, the DMA circuit 6 also continuously transfers the data of the data register 51 to the unit storage area A1 of the memory 4. It will be.

The input decoding section 8 of the DMA circuit 6
When recognizing the attribute data “01”, outputs an internal DMA request signal DREQ2 to the DMA main body section 7. Then D
While the MA main body section 7 maintains the write control signal WR in the active state, the address switching section 74 is set to the adder 73 side and the data of the status register 52 of the communication controller 5 is stored in the unit storage area A1 of the memory 4. Store in the department. The DMA body unit 7 notifies the input decoding unit 8 of the end. The input decoder unit 8 outputs the internal DMA request signal DREQ3 in response to the end notification. The data of the length register 53 is stored in a predetermined area in the unit storage area A1 of the memory 4. At the end, the DMA main body section 7 issues an end notification to the input decoding section 8, and the input decoding section 8 outputs the internal DMA request signal DREQ4 in response to the end notification. DMA body 7
Responds to the internal DMA request signal DREQ4, the address switching unit 74 keeps the adder 73 "+" as it is.
In addition to the 0 "addition state, the read control signal RD is activated to bring the memory 4 into the read enable state. This causes the base address data stored in advance in the next area address storage section in the unit storage area A1 to become the base address data. It is stored in the register 71, and the unit storage area A2 is prepared as shown in FIG. 3 (a) -2 so that the next frame can be received.

(2) When data does not fit in one unit storage area (when a plurality of unit storage areas are connected and used) The DMA main body section 7 has access control, frame control, destination address, sending When the original address and the data of the information field cannot fit in the unit storage area, the address where the subsequent data is stored is stored in the base register 71.

That is, as shown in FIG.
If the unit storage area B1 is used first and its data storage section is full, the DMA main body section 7 determines that the start address of the unit storage area B2 stored in the next area address storage section of the unit storage area B1. Is the base register 71
Stored in. As a result, the unit storage area B2 is used after the unit storage area B1, and the body data following the data stored in the unit storage area B1 is stored in the next unit storage area B2. When the storage of data in the unit storage area B2 is completed, the data stored in the next area address storage unit of the unit storage area B2 is received by the base address register for receiving the next frame as in the case of (1). The setting is set to 71, and the transfer of the received frame is ended.

When reading the data stored in this way, the CPU 1 first reads the data in the main body data storage section of the unit storage area B1 and then reads the unit storage area B1.
When the length is 256 bytes, which is the maximum length, the data in the unit storage area B2 is read by referring to the next area address storage in the unit storage area B1. It will be. That is, the CPU 1 knows that there is continuous data of the same frame based on the length data of the unit storage area before the succeeding unit storage area, and the subsequent unit storage area based on the next area address data of the same unit storage area. It will be possible to link with.

(3) When an error occurs The input decoding unit 8 also has a DMA transfer error detection function, and the status register 52 of the communication controller 5 is included.
The error detection code stored in is decoded, and if an error is detected, the internal DMA request signal DREQ5
To the DMA body 7. Then, the DMA main body section 7 activates the read control signal RD and sets the adder 73 to the "-256" addition state. Then, the start address of the currently used unit storage area is reset in the base register. As a result, the same frame can be received again.

As described above, according to this embodiment, the information indicating the attribute is added to the data sequence of the transfer frame, the start position and the end position of the data are displayed by this attribute information, and the error detection code is used as the status information. And the length information are added and supplied to the input decoding unit 8 of the DMA circuit 6, and the input decoding unit 8 sends the internal DMA request signal DRE to the DMA main unit 7 in response to the detection of the information.
Q1 to Q5 are sequentially output, and these internal DMA request signals D
A predetermined area allocated for each unit area of the memory 4 is addressed according to the REQ 1 to 5, and the communication controller 5
Since the contents of each of the registers 51 to 53 are stored in the memory 4, the communication controller 5 and the DMA circuit 6 can continuously receive the communication frames without the intervention of the CPU processing for receiving the communication frames. And L
Not to mention AN, optical Ethernet (100 Mbps), AT
It becomes possible to support high-speed communication methods such as M (156 Mbps).

[0051]

According to the present invention, the type of each data is identified based on the attribute data added to each data forming the data sequence of the received frame. Even if there is, the above-mentioned code conversion processing by the CPU is unnecessary, and the communication speed can be improved accordingly.

Further, according to the present invention, the status and error information are also identified based on the attribute data and stored in a dedicated area different from the main body data provided in the unit storage area of the buffer memory. Therefore, the I / O reading process by the CPU is unnecessary, and the communication speed can be improved also from this point.

Further, when the transfer of one received frame is completed, the DMA main body section stores the address data stored in the next area address storage section of the current transfer destination unit storage area in the base address register. Therefore, at the end of the transfer of one received frame, the start address of the unit storage area used in the transfer of the next received frame in the buffer memory can be set in the base address register without CPU intervention.

Further, according to the present invention, the occurrence of an error in the data sequence forming the received frame is detected, and at the time of detection, the start address of the current transfer destination unit storage area in the buffer memory is reset in the base address register. Therefore, when an error occurs, the start address of the unit storage area used in the transfer of the frame in which the error occurred in the buffer memory can be reset in the base address register without the intervention of the CPU. Therefore, the communication speed can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a DMA device according to an embodiment of the present invention.

2A and 2B are a data structure explanatory diagram of a buffer memory handled by the DMA device shown in FIG. 1, a data structure explanatory diagram of a transfer frame, and an operation timing explanatory diagram of a communication controller and a DMA circuit.

3 is an explanatory diagram of a transfer operation of received data by the DMA device shown in FIG.

FIG. 4 is a block diagram showing a configuration of a conventional DMA device.

5 is an operation timing explanatory diagram of a communication controller and a DMA circuit in the DMA device shown in FIG.

[Explanation of symbols]

 1 address bus 2 data bus 3 CPU 4 memory 5 communication controller 6 DMA circuit 7 DMA main body 71 base register 72 address counter 73, 75 adder 74 address switching unit 8 input decoding unit

Claims (7)

[Claims] 1. A DMA main body for generating a transfer destination address corresponding to a data structure of a unit storage area provided in a predetermined capacity in a received frame storage buffer memory, and each data forming a data string of the received frame. The type of each data is identified by the attribute data added to, and each data is stored in a predetermined area of the unit storage area based on the identification result, and after the end, the current transfer destination unit storage A DMA device comprising: a decoding unit for generating an access control signal to the DMA main unit so that the address data stored in the next region address storage unit of the region is written in the base address register. 2. The DMA main body section includes a base address register for storing a start address of a current transfer destination unit storage area which is a source of a transfer destination address, and is stored in a next area address storage section of the current transfer destination unit storage area. The DMA device according to claim 1, having a function of storing the address data stored in the base address register. 3. The DMA main body unit adds an address value of a base register unit according to an access control signal by a predetermined value to output an address value corresponding to each area of the current transfer destination unit storage area, and an adder section. The DMA device according to any one of claims 1 and 2, further comprising: 4. The first adder for outputting an address value for a first area for storing a data string of a first field of a received frame in the unit storage area, and the adder section for storing in the unit storage area. A second adder for outputting an address value for a second area for storing a data string of the second field of the received frame; and outputs for switching the outputs of the first and second adders according to a memory access control signal. 4. The DMA device according to claim 3, further comprising: an address switching unit for controlling the address, and a write / read control signal generating unit for outputting a write / read control signal for the buffer memory in response to the output of the address switching unit. . 5. The decoding unit, when the first attribute data indicating the position of the body data of the received frame is identified, becomes the address output command and the write control signal output command of the body data storage area in the unit storage area. First control signal generating means for outputting a memory access control signal, and second for indicating a position of status data of the received frame
Second control signal generating means for outputting a second memory access control signal which becomes an address output command and a write control signal output command of the status storage area and the length storage area in the current transfer destination unit storage area when the attribute data is identified. , Outputs a third memory access control signal that is a next area address read control signal output command and a write control signal output command of the current transfer destination unit storage area used when storing the next reception frame of the reception frame in the buffer memory 5. The DMA device according to claim 4, further comprising a third control signal generating means for performing the above. 6. The decoding unit detects the occurrence of an error in a data string forming a received frame, and at the time of detection, the start address of the current transfer destination unit storage area in the buffer memory is reset in the base address register. 6. The DMA according to claim 5, further comprising: fourth control signal generating means for providing a next area address read control signal output command and a write control signal output command in the unit storage area before the current transfer destination unit storage area. apparatus. 7. A read area in which a unit storage area provided with a predetermined capacity is provided, and the unit storage area stores a writing area for each data type and a head address of the unit storage area immediately after the unit storage area in advance. And a buffer memory for storing the data sequence of the received frame, and each data constituting the data sequence based on attribute data indicating the type of each data constituting the data sequence of the received frame A data controller provided in the data register, and an address generating means for addressing each area of the unit storage area by adding a predetermined value to the stored value of the base register section. The base address register is updated and controlled so that the one or more unit storage areas are used according to the length of the data. Communication system is characterized in that a MA controller.