JPH07282583A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a memory in which data having different column addresses are continuously read and rewritten at high speed. [Configuration] In a DRAM, each data line pair DLi, B
Li is configured to be electrically connected to any of the two input / output line pairs I / Oa and I / Ob by controlling a switch. In the page mode or burst mode in which data with different column addresses are continuously accessed, the above two input / output lines are alternately used. [Effect] In the page mode or the burst mode, when one sense amplifier SAi is connected to the input / output line I / Oa to input / output data, the next sense amplifier SAj is connected to I / Ob to output data. I / O can be started. Therefore, continuous data can be input and output at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed semiconductor memory, and more particularly to a system capable of continuously accessing data having different column addresses at high speed.

[0002]

2. Description of the Related Art A dynamic random access memory (DRAM) is a widely used semiconductor memory. The generally well-known memory array configuration is shown in FIG. Each data line pair, for example DL1, BL1
Is provided with a plurality of memory cells such as MC11, a circuit PC1 for precharging the data line, a sense amplifier SA1 for detecting and amplifying stored information, a switch YSWc1 for connecting the data line pair to the input / output line I / Oc, and the like. ing.

In the DRAM, when the stored information is read, for example, the word line WL is selected by the row decoder XDEC.
Activate 1. Then, the information of the plurality of memory cells connected to this flows out to each data line and is amplified and latched by each sense amplifier. In order to select one of the stored information and output it to the external terminal DQ, one of the switches, for example YSWc1, is turned on by the signal line YSc1. As a result, SA1 is connected to I / Oc, and the stored information latched by SA1 is sent to the main amplifier MAc. Then, the stored information is read out to the external terminal via the input / output circuit Din / Dout. When the stored information is rewritten, the sense amplifier connected to the desired memory cell is connected to the I / Oc by selecting the switch, for example, YSWc1, in the state where the previous stored information is latched in each sense amplifier in the read operation. , External terminal DQ to Din / Dout and I / Oc
Rewrite information may be sent via. The signal YSc1
The control such as is performed by the column decoder YDEC which decodes the column address.

Recently, DRAMs have come to have a function called a page mode or a burst mode for inputting / outputting data continuously and at high speed with the increase in scale and speed of computer systems. In the page mode, information of memory cells having the same row address (connected to the same word line) latched by a plurality of sense amplifiers is input or output at high speed by selecting a column address. That is, in FIG. 9, the read or rewrite operation is continuously performed by selecting the switch YSWc1 or the like according to the column address. As compared with the case where the word line is activated again and the read or rewrite operation is repeated from the beginning, information of different column addresses having the same row address can be read and rewritten continuously and at high speed. FIG. 10 shows a waveform of a conventional read operation. With the data latched in the sense amplifier row, the switch YSch is turned on, and the stored information appearing in the I / Oc is detected and amplified by the MAc. This stored information is transferred to the external terminal DQ via Din / Dout, while MAc is precharged in preparation for the next data detection. Then, another switch YSci is turned on, and the next data is output. In this way, the data latched in the sense amplifier row is continuously and rapidly read by selecting the column address. The burst mode is also similar to the page mode, but stored information (of adjacent sense amplifiers) of consecutive addresses is continuously or rapidly input or output.

[0005]

However, when the page mode or burst mode is attempted in the conventional array configuration shown in FIG. 9, the data transfer cycle at the time of reading is as follows.
After turning on the switch YSWc1 etc., the main amplifier M
There is a problem that the time cannot be shorter than the time until the data is fixed in Ac and the preparation for detecting the next data is completed. Alternatively, the data transfer cycle during writing is the switch YSWc1.
There is a problem that it cannot be shorter than the time from turning on of the like to writing data to the sense amplifier SA1. The reason for this is that in the conventional array configuration, since read and write data transfer is performed through one common input / output line, parallel operation is not possible. As a method for solving this problem, there is a configuration in which adjacent data lines are connected to different input / output lines. An example of such a configuration is, for example, the 1993 Symposium on VLSI Circuits, Digest of Techn.
ical Papers) pp. 65-66. Figure 11
Shows this configuration example. Switches YSWc1 and YSWc2
Are controlled by the same signal line YSc12, and the data line pair (DL
1, BL1) and (DL2, BL2) are connected to the input / output lines I / Oca and I / O2cb, respectively. With this configuration, the stored information latched by the adjacent sense amplifiers can be read simultaneously. Alternatively, the adjacent sense amplifiers can be simultaneously written.
Therefore, as compared with the conventional array configuration shown in FIG. 9, a data transfer rate approximately twice as high as that in the burst mode is possible. However, for page mode, only the same data rate as the array configuration of FIG. 9 can be achieved. Because
This is because the column address is random, and it is possible to successively select sense amplifiers connected to the same input / output line. In this case, since the two sense amplifiers cannot be selected at the same time, the data transfer rate is the same as that of the configuration of FIG. As yet another problem, in the case of normal random access, that is, selection of only 1 bit, an unnecessary sense amplifier is also connected to the input / output line. As a result, there is a problem that the current consumption increases.

Another means for parallelizing data reading is presented in, for example, Japanese Patent Laid-Open No. 59-60794. FIG. 12 shows this configuration. At least two column decoders CD1 and CD2 are provided, and the data lines BL, /
Information of the memory cell connected to BL can be read from either of the output lines B1 and B2. However, Japanese Patent Application Laid-Open No. 59-60794 does not describe means for applying the above-mentioned configuration to speeding up the page mode or the burst mode, and a method of reading information of memory cells connected to the same data line in parallel. Is only mentioned. Moreover, it is obvious that information cannot be written into the memory cell via B2, and therefore it cannot be used as a means for increasing the data transfer rate in the page mode or burst mode for writing.

[0007]

In order to solve the above problems, the present invention has a structure in which each data line pair can be connected to a plurality of, for example, two input / output lines I / Oa and I / Ob. . Correspondingly, each data line pair, for example (D
L1, BL1) are two switches YSWa1 and YSW
b1 and signal lines YSa1 and YSb1 respectively
By controlling the above, it is possible to electrically connect to both the I / Oa and the I / Ob. Then, during continuous data transfer, I / Oa and I / Ob are used alternately. I / O
a and I / Ob are main amplifiers MAa and M, respectively.
MAa and MAb are connected to a common input / output circuit Din / Dout via a switch. The switch is controlled by a signal line AE, and one of MAa and MAb is electrically connected to Din / Dout alternately every 1-bit read or write operation.

[0008]

In the page mode or the burst mode, when one sense amplifier is electrically connected to I / Oa, another sense amplifier is selected and normally operates even if electrically connected to I / Ob. Can continue. In particular, as an effect that I / Oa and I / Ob are used alternately, no matter which order the sense amplifiers are selected, the problem in the conventional configuration of FIG. 11, that is, two sense amplifiers are electrically connected to the same input / output line. Therefore, the data transfer rate at the time of writing and reading in the page mode and the burst mode can be increased. For example, if two pairs of input / output lines are provided, the
It has the effect of doubling the speed. Further, when only one bit is selected, only one of I / Oa and I / Ob is connected to the sense amplifier, and an unnecessary sense amplifier is not connected to I / Oa or I / Ob. Therefore, there is an effect that the current consumption can be reduced as compared with the conventional configuration of FIG.

[0009]

EXAMPLES Examples of the present invention will be described below. Hereinafter, the case where the present invention is applied to a memory array of DRAM will be described, but it goes without saying that the concept of the present invention can be applied to a memory array of a ferroelectric memory or a flash memory.

FIG. 1 shows an embodiment of the present invention showing a memory array structure of a DRAM. Each data line pair, for example (DL1, BL1), has two input / output lines I / Oa and I / via a switch, for example YSWa1 and YSWb1.
The feature is that it can be connected to any of the Ob. (DL
1, BL1) is I / O by activation of the signal line YSa1.
a and to I / Ob by activation of the signal line YSb1. Control of the signals YSa1 and YSb1 is performed by the column decoder YDEC, as described later. I / Oa and I / Ob are connected to main amplifiers MAa and MAb, respectively, and MAa and MAb
Is a common input / output circuit Din / Dout via a switch
Leads to. In FIG. 1, data latch circuits LATCHa and LATCHb are provided between the input / output circuit and the main amplifier.
Is provided. The array configuration other than the input / output system described above is the same as that of a normal DRAM. Each data line pair, for example (DL1, BL1), is provided with a plurality of memory cells such as MC11, a circuit PC1 for precharging the data lines, a sense amplifier SA1 for detecting and amplifying stored information, and the like.

FIG. 2 is an embodiment of the present invention showing the read operation waveforms in the circuit of FIG. The page mode or burst mode read operation in the circuit of FIG. 1 will be described with reference to FIG. After the word line WLi is activated by the row decoder XDEC, the sense amplifier column is activated by the signal lines SAN and SAP, and the information of the memory cell connected to WLi is latched in the sense amplifier column. By selecting the column address h, the signal line YSah is activated, and the data line pair DLh, BLh is connected to I / Oa. As a result, the first data is read by the main amplifier MAa. At the stage where YSah is still activated and the read operation is being performed, the next column address i is selected, the signal line YSbi is activated, and the data line pair DL is activated.
i and BLi are connected to I / Ob. Then, the second data is read by the main amplifier MAb. In the middle of the read operation of the second data, the read operation of the first data is completed, the third column address is continuously selected, and YSaj is activated. Like this, 2
By alternately using one input / output line and the main amplifier, it becomes possible to start the reading operation of another data while reading one data. In other words, it is possible to overlap the period in which the switch between the data line pair and the input / output line is on. As a result, there is an effect that the data transfer rate can be doubled as compared with the conventional case shown in FIGS. Further, in the configuration in which data is simultaneously output to a plurality of input / output lines as shown in FIG. 10, the same input / output line may be continuously used when the column addresses are selected in an arbitrary order.
Only in the conditional burst mode, the data transfer rate can be increased compared to the case of the configuration of FIG.
On the other hand, according to the embodiment of the present invention, it is possible to increase the data transfer rate for any page mode and burst mode. Further, in the configuration of FIG. 10, it is necessary to connect an unnecessary sense amplifier to the input / output line at the time of random access for reading or writing only 1-bit data. On the other hand, according to the embodiment of the present invention, there is an effect that it is not necessary to perform unnecessary charge and discharge, and the current consumption can be reduced. Needless to say, the same effect can be obtained in the write operation.

FIG. 3 shows an embodiment of the present invention in which a plurality of sense amplifiers are selected by one signal line. When the signal line YSa12 is activated, the sense amplifier S
A1 and SA2 are input / output lines I / Oa1 and I / O, respectively.
It is connected to Oa2. On the other hand, when YSb12 is activated, SA1 and SA2 become I / Ob1 and I / O, respectively.
It is connected to b2. According to the embodiment of the present invention, the set of input / output lines (I /
Oa1, I / Oa2) and (I / Ob1, I / Ob2) are alternately used to activate YSa (i, i + 1) to access the sense amplifier SAi while another YSb (j , J + 1) can be activated to access SAj. Therefore, as in the case described with reference to FIGS. 1 and 2, there is an effect that data can be continuously input and output at high speed in the page mode and the burst mode. In addition, the signal lines YSa12 and YSb1
There is an effect that the wiring pitch such as 2 becomes loose and manufacturing becomes easy. In the embodiment of the present invention, the signal line YSa12 and the like are shared between two data line pairs, but more data line pairs may be shared. Thereby, the signal line YS
The wiring pitches of 1, YS2, etc. become more and more loose, which has the effect of facilitating manufacturing.

FIG. 4 is a block diagram showing a memory circuit of the present invention including peripheral circuits. Memory array MAr
The ray is the same as the array shown in FIG. 1 or FIG. As a direct peripheral circuit, a row decoder XDec for selecting a row address such as a word line WL1 and a signal line YSa1
Column decoder YDec for selecting column address
Is provided. As peripheral circuits, control signals RAS, CA
A control circuit CNTL for decoding S, CLK and the like to control the memory, and a row predecoder XPreD for decoding input addresses A0-AN in response to a signal from the CNTL.
ec and column predecoder YPreDec, I / O
A circuit I / OSel for generating a selection signal for alternately selecting a and I / Ob is provided. I / OSel
Is composed of, for example, 2-bit registers Re1 and Re2, and 0 is latched in one of Re1 and Re2 and 1 is latched in the other. When it is detected that the column address is changed by the signal (CAS or CLK) from the CNTL, the values of Re1 and Re2 are exchanged. In other words, the value of Re1 is R
Feed e2 and the value of Re2 to Re1. In such a circuit, for example, the value latched in Re1 is output as a signal S for selecting I / Oa, and the value latched in Re2 is output as a signal / S for selecting I / Ob. When the memory chip is composed of a plurality of divided memory arrays, I / OSel may be shared between the memory arrays or may be provided for each memory array. According to the embodiment of the present invention, when inputting / outputting continuous data, I / Oa and I / Ob are alternately used. Therefore, as is apparent from the operation waveforms shown in FIG. There is an advantage that the speed can be increased to about twice. The number of input / output lines is not limited to two, but three or more may be provided. As a result, the data transfer rate can be further increased.

FIG. 5A shows the signal line YSa in FIG.
1 and the like, or a method of controlling the signal line YSa12 and the like in FIG. 3 is an embodiment of the present invention. Conventional DR
A signal line from the column decoder YDEC0 similar to AM, for example YS1, has two flip-flop circuits FFa1.
And FFb1. In response to the signal S from the input / output line selection circuit I / OSel and its inverted signal / S in the block diagram of FIG. 4, the selection signal on YS1 is F
It is sent to Fa1 or FFb1. In FIG. 5 (b),
A specific circuit example of the flip-flop circuit, for example, FFa1 will be shown.

FIG. 6 is an embodiment of the present invention showing the operating method of FIG. 5 (a). The specific operation of FIG. 5A will be described with reference to FIG. In FIG. 6, YSai connecting the data line pair to the input / output line I / Oa and Y connecting to the I / Ob.
Data is continuously transferred by selecting Sbj and Sbj alternately by the next operation. That is, the signal S changes from high level to low level in response to the falling edge of CLK, and changes from low level to high level in response to the next falling edge of CLK. Such a signal S can be generated by the method described in FIG. 4, for example. When S is at low level, S1a shown in FIG. 5 (a) is also at low level. When S changes to a high level in response to the falling edge of CLK, S1a also changes to a high level and YSi (i = 1,
2 ...) is sent to the flip-flop FFai. Due to the operation of the inverters and the AND circuits connected to the odd-numbered stages, S1a returns to the low level again after a delay of a while after S changes to the high level. As a result, YS
The signal of i is latched by FFai, and the signal line such as YS
a1 is held in the activated state. When S changes to a low level, that is, / S changes to a high level in response to the next falling edge of CLK, a similar operation causes the next YSi signal to be latched by FFbi and the signal line, for example YSb2, to be activated. It is kept as it is. According to the above operation, the data line pair (DL1, BL1) is I by the signal line YSa1.
While connected to / Oa and being read or written, another data line pair, for example (DL2, BL2), can be connected to I / Ob by YSb2 to start reading or writing. In this way, since the read and write operations of two data can be overlapped, the data transfer cycle can be shortened to about half the time required for read and write. In other words, there is an effect that the transfer rate of continuous data can be increased to about twice as fast as the conventional one.

FIG. 7A shows the signal line YSa in FIG.
1 or the like, or a method of controlling the signal line YSa12 or the like in FIG. 3 different from that of FIG. 5 is an embodiment of the present invention. A feature of the present invention is that two column decoders are provided, that is, a column decoder YSai system YDEC that controls the signal line YSai and a column decoder YSbi system YDEC that controls the signal line YSbi. The latch circuit AB is provided at the input of each decoder.
1 and AB2 are provided. The column address information sequentially sent from the column predecoder YPreDec is alternately stored in AB1 and AB2 under the control of the clock CLK and the signals S and / S. Figure 7
In (b), the buffer shown in (a) of FIG.
An example of a 1-bit latch circuit that configures the above is shown.

FIG. 8 is an embodiment of the present invention showing the operation waveforms of FIG. 7 (a). Signal S and its inverted signal / S
Rises alternately in synchronization with the falling edge of CLK, similar to the waveform of FIG. For example, when S rises in synchronization with the fall of CLK and then CLK rises again, C1 falls and the column address information is latched by AB1 and sent to the YSai system YDEC. Then, the selected data line pair is connected to I / Oa. Next, when CLK falls, S falls and / S rises. Then, in synchronization with the next rising edge of CLK, the next column address information is latched by AB2 and sent to the YSbi system YDEC. Then, the selected data line pair is connected to the I / Ob. Also in the embodiment of the present invention, the data line pair (DL1, BL) is connected by the signal line YSa1.
1) is connected to I / Oa and is being read or written, another data line pair such as (DL2, B
L2) can be connected to the I / Ob by YSb2 to start reading or writing. In this way, the read and write operations of two data can be overlapped, so that the data transfer cycle can be shortened to about half the time required for read and write. That is, there is an effect that the transfer rate of continuous data can be increased to about twice as fast as the conventional one.

[0018]

According to the present invention, it is possible to obtain a memory capable of continuously reading and rewriting data having different column addresses at high speed.

In the page mode and burst mode, one sense amplifier SAi is connected to the input / output line I / Oa.
While inputting and outputting data by connecting to the I / Ob, the next sense amplifier SAj can be connected to I / Ob to start inputting and outputting data. Therefore, continuous data can be input and output at high speed. Moreover, even if it has a plurality of input / output lines,
Even when compared with the conventional method in which each sense amplifier is always connected to the same input / output line, each sense amplifier is I
As an effect that can be connected to both / Oa and I / Ob,
No matter which column address is selected in succession, I / O
By alternately selecting a and I / Ob, two sense amplifiers are not connected to the same input / output line. Therefore, high-speed data access is possible in any page mode and burst mode. Further, since it is not necessary to connect an unnecessary input / output line to the sense amplifier at the time of normal random access for accessing data of only 1 bit, there is an effect that current consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a memory array configuration of the present invention.

FIG. 2 is a read operation in the memory array of FIG.

FIG. 3 is a memory array configuration of the present invention.

FIG. 4 is a block configuration of a memory of the present invention.

5 is a diagram illustrating the signal lines YSa and YSb in FIG. 1 or FIG.
Is a control method.

6 is an operation waveform of the circuit of FIG.

FIG. 7 is a diagram illustrating signal lines YSa and YSb in FIG. 1 or FIG.
Is a control method.

8 is an operation waveform of the circuit of FIG.

FIG. 9 is a conventional memory array configuration.

10 is a read operation in the memory array of FIG.

FIG. 11 is a conventional memory array configuration.

FIG. 12 is a conventional memory array configuration.

[Explanation of symbols]

WLi ... Word line, DLi, DBi ... Data line, MCi
j ... memory cell, PCi ... precharge circuit, SAi ...
Sense amplifier, YSWai, YSWbi, YSWi, Y
SWci ... Column address selection switch, VPC ... Precharge power supply line, PCS ... Precharge signal line, SA
P, SAN ... Sense amplifier drive line, YSai, YSb
i, YSi, YSa0, YSb0, YSa12, YSb
12, YSci, YSc12 ... Column address selection signal line, I / Oa, I / Ob, I / Oa1, I / Oa2, I
/ Ob1, I / Ob2, I / Oc, I / Oca, I / O
cb ... I / O line, MAArray ... memory array, XDe
c ... Row decoder, YDec ... Column decoder, CNT
L ... Control circuit, XPreDec ... Row predecoder, Y
PreDec ... Column predecoder, I / OSel ... I / O line selection circuit, Re1, Re2 ... Register, CLK ...
Clock, RAS ... Row address strobe signal, CA
S ... Column address strobe signal, A0, AN ... Address signal, MAa, MAb, MAc ... Main amplifier, L
ATCHa, LATCHb ... Latch circuit, AE ... I / O line switching signal, Din / Dout ... I / O circuit, FF
ai, FFbi ... Flip-flop circuit, S1a, S1
b ... Flip-flop circuit selection signal, AB1, AB2 ...
Address latch circuits, CD1, CD2 ... Column decoders, B1, B2 ... Output lines.

Claims (5)

[Claims] 1. A semiconductor memory comprising a plurality of memory cells arranged in a matrix at intersections of data lines and word lines, wherein a plurality of sense amplifiers for detecting information stored in the memory cells are provided. The sense amplifier is
An input / output line for transferring information to and writing information from the external device is shared via a switch, and the shared input / output line is plural, and the sense amplifier is controlled by the switch. Is a structure capable of being electrically connected to at least two of the plurality of input / output lines. 2. The semiconductor memory according to claim 1, further comprising a mode in which the plurality of sense amplifiers are selected one after another to access a series of information, and in the mode, two sense amplifiers which are continuously selected are provided. The semiconductor memory is characterized in that the switches are controlled so as to be connected to different input / output lines. 3. The semiconductor memory according to claim 1, wherein a plurality of sense amplifiers are connected to different input / output lines by one signal line controlling the switch. 4. The semiconductor memory according to claim 1, further comprising a circuit for switching a selected input / output line in response to a change in column address. 5. The semiconductor memory according to claim 1, wherein a plurality of latch circuits for holding the switch in an ON state are provided.