JPH0728443A - Method for controlling frame memory - Google Patents

Abstract

PURPOSE:To provide an excellent method for controlling a frame memory and properly controlling the frame memory for the purpose with minimal memory capacity when a still image and a moving image are displayed while coexisiting. CONSTITUTION:The frame memories 11, 12 storing the data displayed on a display 6 are provided by two pictures. By a frame memory control part 17, respective signals for the frame memories 11, 12 are controlled. The frame memory is controlled so that when the still image data are written in the frame memory 11 or 12 while displaying, the same data are written in the frame memory 12 or 11 while non-displaying, and when the moving image data are written in the frame memory 12 or 11 while non-displaying, no data are written in the frame memory 11 or 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of controlling a frame memory used for storing display data in a personal computer or a workstation.

[0002]

2. Description of the Related Art Conventionally, when displaying a processing result on a display in a personal computer or a workstation, data to be displayed is temporarily written in a display memory (hereinafter referred to as a frame memory), and then the display data is read from the frame memory. Output to the display.

FIG. 7 is a control block diagram showing a control circuit of a conventional frame memory. In the figure, control C
A bus 2 that transfers data is connected to the PU 1, and the bus 2 is connected to the display control unit 3. The display control unit 3 includes a frame memory 4 and a display interface 5, and the display interface 5 is connected to the display 6.

When displaying the processing result on the display 6, the CPU 1 first writes the data in the frame memory 4 via the bus 2. Next, the display control unit 3 uses the display interface 5 to convert the data written in the frame memory 4 into the signal regulation of the display 6 and outputs it to the display 6.

Conventionally, there are two methods for writing data in the frame memory and displaying operations on the display. First, as in the example shown in FIG. 7, the frame memory has a capacity for one screen of the display, and the data write operation by the CPU and the data read operation from the frame memory are performed asynchronously. Such a control method is used when displaying characters or a still image.

The second method is a method used when displaying a moving image or the like. As shown in FIG. 8, a frame memory 4 for two screens is provided and data is read from one frame memory 4a. While displaying on the display 6, new display data is written in the other frame memory 4b. When the writing of the display data is completed, the selector 7 reverses the function of the frame memory 4 to write and read the data. Note that FIG.
FIG. 9 is a block diagram showing another conventional example.

[0007]

Conventionally, some of the above-mentioned two control methods have been adopted according to the contents to be displayed. However, as shown in FIG. The part A of the window displaying the moving image needs to be controlled by using the frame memory for two screens, and the part B other than the window is a part mainly displaying the still image such as characters. Is suitable to be controlled by the frame memory for one screen. FIG. 9 is an explanatory diagram showing the window display.

A circuit configuration for controlling the frame memory as described above is shown in FIG. In the figure, the control circuit for multi-window display has three frame memories 4a, 4b,
4c is provided. Further, a selector 8 for synthesizing the display data of the frame memory 4a or 4b and the display data of the frame memory 4c, and a portion not shown for synthesizing C
A synthesis specification memory 9 specified by PU is newly required. Therefore, there is a problem that a large amount of memory is required.

The present invention has been made in view of the above problems, and an object thereof is to control a frame memory suitable for a still image and a moving image in a mixed display with a minimum memory capacity. An object of the present invention is to provide an excellent frame memory control method.

[0010]

In order to solve the above-mentioned problems, the present invention stores a frame data for two screens in which display data is stored, and when one is being displayed, the other is in a non-display state. A display control unit that controls writing and reading of display data to and from a frame memory for two screens, and the display control unit stores a frame memory being displayed and a frame memory not being displayed, and is not displayed. When writing data to the frame memory of, the data is directly written to the non-display frame memory, and when writing data to the frame memory being displayed, the display control unit writes the data to the non-display frame memory. It was done.

[0011]

According to the present invention having the above structure, as the display data which can be controlled only by one screen, the data is written in the frame memory being displayed and the same data is also written in the non-display frame memory. Then, the image is displayed by switching the displayed frame memory to the non-displayed frame memory. In the case of image data that requires a frame memory for two screens, the data is written in the non-display frame memory, so that the image is displayed by switching the frame memory being displayed to the non-display frame memory. That is, display data that can be controlled with only one screen and display data that requires a frame memory for two screens can be displayed with the same control.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. Note that elements common to the drawings are given the same reference numerals. FIG. 1 is a block diagram showing a display control circuit of a first embodiment according to the present invention. First, the first embodiment will be described.

In FIG. 1, two frame memories 1 are provided.
Reference numerals 1 and 12 are used to store display data.
It has the capacity for the screen. These frame memories 11,
Reference numeral 12 is connected to the CPU 1 via the bus 2 and the data bus 13, and the CPU 1 is connected to the frame memories 11 and 1.
2 can be read and written. The frame memories 11 and 12 are connected to the selector 14 and output display data to the selector 14. The selector 14 is
The output b of the frame memory 11 or the output c of the frame memory 12 is selected, and the selected output is sent to the display 6 via the display interface 5.

A register 15 is connected to the data bus 13, and a synchronizing circuit 16 is connected to the register 15.
The synchronization circuit 16 is connected to the selector 14 and the frame memory control unit 17. The synchronizing circuit 16 outputs a signal d obtained by synchronizing the output of the register 15 set by the instruction of the CPU 1 with the synchronizing signal e of the display. This signal d becomes a signal for controlling the selector 14.
When the signal d is "0", the contents of the frame memory 11 are displayed, and when the signal d is "1", the contents of the frame memory 12 are displayed.

The frame memory control unit 17 is connected to the CPU 1 via the bus 2, and the frame memories 11 and 1 are also connected.
Connected to 2. The frame memory control unit 17 refers to the display / non-display state of the frame memories 11 and 12 by the signal d, the control signal indicating the access from the CPU 1 and the memory address, and generates the frame memory control signal g.

Next, the relationship between the frame memories 11 and 12 and the frame memory controller 17 will be described in detail with reference to FIG. FIG. 2 is a block diagram showing the main part of the first embodiment. In FIG. 2, a signal h and a signal i are address signals designated by the CPU 1, and a signal h is A0 to An-1 representing a position in the frame memory for one screen. A signal I is an address signal An indicating whether the frame memory accessed by the CPU 1 is a display memory or a non-display memory. When An is “0”, it indicates access to the frame memory being displayed, and An is When it is "1", it indicates access to the hidden frame memory.

Signals j and k are control signals from the bus 2, and signal j is a signal "ACC" indicating access to the frame memory. The signal k is “R / W” indicating whether the frame memory is read or written, and indicates “0” for writing and “1” for reading. The signal r is a signal "RDY" indicating that the access to the frame memory is completed. The signal m is an address signal to the frame memory and is generated from A0 to An-1. The signal n is a read signal R0 to the frame memory 11, the signal o is a write signal W0 to the frame memory 11, and the signal p is
Is a read signal R1 to the frame memory 12, and signal q is a write signal W1 to the frame memory 12.

Table 1 shows the logical operation of the frame memory control unit 17 when the CPU 1 accesses the frame memories 11 and 12.

[0019]

[Table 1]

As shown in Table 1, Case 1 to Case 3
Then, the signal d stored in the frame memory control unit 17
Signal i and signal k from bus 2
Validate any signal of o, p, and q. Case 4 is C
This is a case of writing from the PU1 to the frame memory being displayed, and in this case, the write signal o to the frame memory 11 and the write signal q to the frame memory 12 are performed.
Both are valid. As a result, the same data is written in both frame memories 11 and 12.

FIG. 3 is a timing chart showing the operation in case 4 described above. In FIG. 3, the address of the signal m is validated at the timing a, and the write signals o and q to the frame memories 11 and 12 are validated at the timing b when the access signal j from the bus 2 is valid. At this time, the data designated by the data bus 13 is written in both the frame memories 11 and 12.

The timing c indicates the end of data writing. At this time, the signal r becomes valid, then the signal j becomes invalid at the timing d, and each signal becomes invalid at the timings e and c.

Next, the frame memory control from the CPU 1 will be described. FIG. 4 shows a memory space from the CPU 1. In the figure, A is a space for accessing the currently displayed frame memory, and even if any of the frame memories 11 and 12 is displayed, this space is used for memory access. B is a space for accessing a non-display frame memory, and like A, it does not matter which frame memory is non-display. A0 to An are used as memory addresses. For example, when the frame memory capacity for one screen is 256 kilobytes, n = 8 and A0 to A7
Specify the memory address in one screen with, and specify A or B with A8.

Therefore, when writing data in the memory in the space A, the data is written in both frame memories without fail, so that it is possible to control so that there is only one frame memory. On the other hand, when the display data is updated in synchronization with the vertical update time of the display, it can be realized by writing in the frame memory using the space B, and then inverting the display / non-display of the frame memory.

Next, a frame memory control method according to the second embodiment of the present invention will be described with reference to FIGS.
FIG. 5 is a block diagram showing an essential part of the second embodiment, and FIG.
6 is a timing chart showing the operation of the embodiment.

In FIG. 5, the frame memories for two screens are designated by n + 1 memory address signals, MA0 to MA0.
Denote by MAn. Therefore, the number of control signals for writing and reading is one for each of the signal n and the signal o,
It is indicated by "RD" and "WR". The other structure is similar to that of the first embodiment.

Table 2 shows the logical operation of the frame memory control unit in the second embodiment.

[0028]

[Table 2]

In Table 2, as described above, in the second embodiment, since there is only one read signal and one write signal, the signal n or the signal o is controlled by controlling MAn of the address output signal (m). To enable. Then, in case 4, the write operation is enabled twice to write to both the frame memories 11 and 12.

FIG. 6 shows the write operation in Case 4 of Table 2 in two.
The timing control operation performed once is shown. In FIG. 6, 1 is added to the frame memory 11 or 12 at the timing
After completing the second write, change the address MAn,
Writing is started to the frame memory 12 or 11 at the timing of H. Then, at the timing of the end of the second writing, the signal r indicating the end of the operation becomes effective.

[0031]

As described above in detail, according to the present invention, the image data that can be displayed in the frame memory for one screen and the image data that requires the frame memory for two screens are mixed to form one display. In the case of displaying on the screen, when the image data that can be displayed in the frame memory for one screen is written in the frame memory in display, it is also written in the non-display frame memory, so that the frame memory for two screens is required. The image data can be displayed under the same control as that for displaying the image data. Therefore, mixed display is possible with a frame memory having a capacity of two screens, that is, with a minimum frame memory capacity, and with the same control as the conventional one.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment according to the present invention.

FIG. 2 is a block diagram showing a main part of the first embodiment.

FIG. 3 is a timing chart showing the operation of the first embodiment.

FIG. 4 is an explanatory diagram showing a memory space of the first embodiment.

FIG. 5 is a block diagram showing a main part of a second embodiment.

FIG. 6 is a timing chart showing the operation of the second embodiment.

FIG. 7 is a block diagram showing a conventional frame memory control circuit.

FIG. 8 is a block diagram showing another conventional example.

FIG. 9 is an explanatory diagram showing a window display.

FIG. 10 is a block diagram showing a conventional control circuit for multi-window display.

[Explanation of symbols]

 1 CPU 6 display 11 and 12 frame memory 17 frame memory control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06T 1/60 G09G 5/14 E 8121-5G 5/36 530 F 8121-5G E 8121-5G

Claims (3)

[Claims] 1. A display for storing display data, and when one is being displayed, the other is a non-display frame memory for two screens, and the display data is written to the frame memory for two screens. A display control unit for controlling reading, and the display control unit stores a frame memory being displayed and a non-display frame memory, and when writing data to the non-display frame memory, the non-display frame memory is used as it is. A method of controlling a frame memory, characterized in that when the data is written in the frame memory and the data is written in the frame memory being displayed, the display control unit also writes the data in the non-display frame memory. 2. The method of controlling a frame memory according to claim 1, wherein, when the display control unit writes the data in the frame memory being displayed, the data is simultaneously written in the frame memory being displayed and the frame memory not being displayed. 3. The method of controlling a frame memory according to claim 1, wherein, when the display control unit writes data in the frame memory being displayed, the data is written stepwise in the frame memory being displayed and the frame memory not being displayed.