JPH0728663A - Information processing equipment test equipment - Google Patents

Abstract

(57) [Abstract] [Object] The present invention relates to a test apparatus for an information processing apparatus,
Random data is written to the access data area or register during the correct answer data collection processing or comparison processing, and the test is repeated to ensure the randomness of the data in the access data area or register to improve test accuracy and The purpose is to be able to deal with the test for the instruction string under test. An instruction generation control unit 02 that generates a test instruction sequence in which test instructions are randomly arranged and sets a check instruction in the test sequence, and a check instruction set in the test sequence Correct information (register information and interrupt information) when control is passed during execution and in acquisition mode
Check point control unit 12 that saves data or compares the correct answer information in the comparison mode to determine normality / error, and sets random data in the access data area 11 used by the instruction string under test. And so on.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for executing an instruction string under test to test an information processing apparatus.

Since information processing devices in recent years are large in size and have complicated mechanisms, effective tests are required in random instruction combination tests. Therefore, in the test of a small random instruction string, register data,
Although the access data area does not become saturated, it is necessary to control the register data and the access data area that become saturated in the test of a large-scale random instruction sequence to a random state during execution.

[0003]

2. Description of the Related Art A conventional information processing apparatus test apparatus is shown in FIG.
Under the configuration as shown in, random test instruction sequence 1
10 was generated and tested while changing the execution environment of the instruction under test. At this time, in the comparison control of the execution result, it is determined whether it is the collection mode or the comparison mode, and the register information and various interrupt information are set in the save areas 117 and 121 at the execution point of the check instruction as the execution result information and executed. The test was conducted by comparing the execution results for each environment. The conventional configuration and operation of FIG. 7 will be briefly described below.

In FIG. 7, an initial setting section 101 performs initial setting of test conditions. Instruction generation control unit 10
2 generates a random instruction and sequentially sets it in the instruction string 110 to be tested of the test routine 106.

The execution environment setting control unit 103 sets the execution environment in which the test routine 106 executes. The test routine activation control unit 104 controls the activation of the test routine 106.

The mode change control unit 105 arbitrarily changes the mode of the test routine 106 to the collection mode or the comparison mode and executes it. Test repeat control unit 1
Reference numeral 24 is a state in which the mode is changed by the mode change control unit 105 and is repeatedly executed.

The test routine 106 includes the instruction string 11 under test.
0 is executed, control is performed by the check point control 112 at a check point (exec instruction execution point), comparison is performed, and a test is performed.
Execution environment setting 108, start-up processing 109, test instruction sequence 1
10, an access data area 111, and a check point control 112. Figure 7 below
The operation of the configuration will be briefly described.

(1) The initial setting 107 of the test routine 106 is performed corresponding to the initial setting by the initial setting unit 101, and the tested instruction sequence 110 is sequentially set corresponding to the generation of random instructions by the instruction generation control unit 102. Then, the execution environment setting control unit 103 performs the execution environment setting 108 corresponding to the setting of the execution environment executed by the test routine 106,
Test routine 10 by test routine start control unit 104
In response to the activation of 6, the test routine 106 starts the test.

(2) The activated test routine 106 sequentially executes the instruction string 110 to be tested, and when the checkpoint is executed (when the svc instruction is executed), the control is passed to the checkpoint control unit 12, and the checkpoint control unit concerned. 112
Performs the corresponding processing from 113 to 122.

(3) Check Point Control Unit 112
The mode determination unit 113 determines whether the mode is the collection mode or the comparison mode. The mode change control unit 105 changes the collection mode or the comparison mode at any time.

(3-1) If it is the collection mode, the collection mode unit 114 executes the register information 11 of the execution result.
5 is stored in the data A of the save area 117, and various interrupt information 116 is stored in the data B of the save area 117 to be the correct answer information.

(3-2) If it is the comparison mode, the comparison mode unit 118 executes the register information 11 of the execution result.
9 is stored in the data C of the save area 121, and various interrupt information 120 is stored in the data D of the save area 121 to be the comparison target information. Then, the comparison processing unit 122 causes the save area 117 to
Data A of the save area 121 and the data C of the save area 121 are compared, and the data B of the save area 117 and the data D of the save area 121 are compared.
Compare with and perform the test. As a result of the comparison, if there is a mismatch and there is an error, the error control unit 123 outputs error information.

(4) The test repetition control unit 124 causes the instruction generation control unit 102 to generate and set a new instruction string 10 to be tested according to the initial setting unit 101, and repeats and executes the test.

[0014]

A test device for collecting and comparing only result information, which executes a random test instruction sequence 110 according to the above-described configuration of FIG. 7 and compares the execution results, to perform a test. Then, when targeting a large-scale instruction string under test, register data and the access data area may gradually become saturated (all 0s) due to a shift instruction or a multiplication instruction of zero. Therefore, there was a problem that the test with random data could not be performed.

The present invention solves these problems by
Random data is written to the access data area or register during the correct data collection processing or comparison processing, and the test is repeated to ensure the randomness of the access data area or register data to improve the test accuracy and The purpose is to be able to deal with the test for the instruction string under test.

[0016]

[Means for Solving the Problems] Means for solving the problems will be described with reference to FIG. In FIG. 1, the instruction generation control unit 02 generates a test instruction sequence 10 in which test instructions are randomly arranged and sets a check instruction in the test instruction sequence 10.

The check point control unit 12 saves the correct answer information (register information and interrupt information) in the collecting mode, or compares the correct answer information with the correct answer information in the comparison mode to judge normality / error, Random data is set in the access data area 11 used by the instruction string under test 10, random data is set when the ratio of the same value in the access data area 11 is higher than the threshold value, and the register 31 To set random data, or to set random data when the ratio of the same value in the register 31 is higher than the threshold value.

[0018]

According to the present invention, as shown in FIG. 1, the instruction generation control unit 02 arranges the instruction under test at random and the instruction under test sequence 1 is arranged.
0 is generated and a check instruction is set in the instruction string to be tested 10, and the check point control unit 12 to which control is passed when the check instruction set in the instruction string to be tested 10 is executed is in the correct mode. Information (register information and interrupt information) is saved, or normal / error is determined by comparing with correct answer information in the comparison mode, and random data is stored in the access data area 11 used by the instruction string 10 to be tested. Is set and the test is repeated.

At this time, when the ratio of the same value in the access data area 11 used by the instruction string to be tested 10 is higher than the threshold value, random data is set and the test is repeated.

Further, the instruction generation control unit 02 generates the instruction under test 10 in which the instruction under test is randomly arranged, sets a check instruction in the instruction under test 10 and is set in the instruction under test 10 When the check point control unit 12 to which control has passed when the check command is executed saves the correct answer information (register information and interrupt information) in the collection mode, or compares the correct answer information with the correct answer information in the comparison mode. An error is determined, random data is set in the register 31 used by the instruction string to be tested 10, and the test is repeated.

At this time, when the ratio of the same value in the register 31 used by the instruction string to be tested 10 is higher than the threshold value, random data is set and the test is repeated. Therefore, random data is written in the access data area 11 or the register 31 and the test is repeated at the time of collecting or comparing the correct answer data, so that the randomness of the data in the access data area 11 or the register 31 is ensured and the test accuracy is It becomes possible to deal with the test for a large-scale instruction string under test while improving the.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the construction and operation of an embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a block diagram of an embodiment of the present invention.
In FIG. 1, an initial setting unit 01 performs initial settings such as clearing a memory and a register.

The random data writing unit 011 writes random data in the access data area 11 and the register 31 used by the instruction string 10 to be tested.
The instruction generation control unit 02 generates an instruction string to be tested 10 in which instructions to be tested are randomly arranged, and sets a check instruction (svc instruction) in the generated instruction string to be tested 10.

The execution environment setting control unit 03 sets the execution environment used by the instruction string under test 10 (for example, whether or not a cache is used). The test routine activation control unit 04 activates the test routine 06.

The mode change control unit 05 arbitrarily changes the collection mode and the comparison mode. When set to collection mode, access data area 1 at that time
1 and the data of the register 31 are saved as the correct value. When the comparison mode is set, the data in the access data area 11 and the register 31 at that time are compared with the stored correct answer value, and when they match, it is determined as normal, and when they do not match, it is determined as an error.

The test repetition control unit 25 repeats the test. The test routine 06 is a routine for executing a test by the instruction string to be tested 10 in which a random instruction string is set, and includes an initial setting 07, an execution environment setting 08, a starting process 09, an instruction string to be tested 10, an access data area. 1
1, register 31, and check point control 12
It is composed of etc.

Initial setting 07 clears the memory and registers. The execution environment setting 08 sets an execution environment such as the presence or absence of a cache. The start processing 09 is the test instruction sequence 1
Invokes an execution such as 0.

The instruction string to be tested 10 is one in which an instruction string to be tested is randomly set and a check instruction (svc instruction) is set. The control is passed to the check point control unit 12 by executing the check instruction (svc instruction).

The access data area 11 is a data area accessed by the instruction string 10 to be tested. Register 31
It is a register used by the instruction string under test 10.

The check point control section 12 is activated when the svc instruction in the instruction string under test 10 is executed, and is activated, and performs the control as shown in the figure.

The mode determination unit 13 receives the control from the check point control unit 12 by the svc instruction.
The mode is to determine either a collection mode for collecting correct values or a comparison mode for comparing with correct values.

The collection mode unit 14 is activated when the mode determination unit 13 determines that the mode is the collection mode.
The register information 15 and the interrupt information 16 of the execution result by the instruction string 10 to be tested are fetched as correct values, and data 1, data 2, ... At the position pointed by the pointer 17.
To save as.

The pointer 17 is the correct value register information 1
5 is a pointer that points to an address for storing 5 and interrupt information 16. The correct value register information 15 and interrupt information 16 are sequentially stored at the address pointed to by the pointer 17.

The comparison mode unit 19 is activated when the mode determination unit 13 determines that it is in the comparison mode.
The register information 20 and the interrupt information 21 of the execution result by the instruction string under test 10 are fetched as comparison values, and the save area 2
2 are saved as data A and data B, respectively.

The comparison processing section 23 compares the correct value data 1, data 2, ... With the comparison target data A, data B in the save area 22. If they match, they are normal, and if they do not match, they are error. It is a judgment.

The error control section 24 compares the correct value and the comparison value by the comparison processing section 23 and outputs an error result when they do not match. The access data resetting control unit 26 sets random data in the access data area 11 and the register 31 used by the instruction string under test 10, and the ratio of the same value in the access data area 11 and the register 31 is set. Random data is set when the value is higher than the threshold.

The random number generation circuit 27 generates random data to be written in the access data area 11 and the register 31. Next, the operation of the configuration of FIG. 1 will be described in detail according to the order shown in the flowchart of FIG.

In FIG. 2, S1 is initialized. For example, the access data area 11 which is a memory and the register 3
Clear 1. S2 accesses random data
Write to the data area. This is because the random data writing unit 011 of FIG.
Write to 1.

In step S3, an instruction string to be tested is generated. This is because the instruction generation control unit 02 of FIG. 1 randomly sets the instruction to be tested to the instruction-under-test sequence 10 at random and sets the svc instruction to the check point.

In step S4, the execution environment is set. For example, whether or not to use the cache is input, and whether the sequential mode or the sequential mode is input. For this, the execution environment setting control unit 03 in FIG. 1 sets the execution environment.

In step S5, a test routine is started. For this, the test routine activation control unit 04 of FIG. 1 activates the test routine 06. S6 initializes. This is S
The test routine 06 started in 5 performs initial setting, for example, general register setting. Here, as the setting of the general register, as shown in the drawing, the access destination address is set in the base register and the offset register, and the random data is set in the calculation register.

In step S7, the execution environment is set. This is because the test routine 06 sets in the control register whether or not the cache is used, and sets in the control register whether the mode is sequential or non-sequential.

S8 is started. This starts execution of the instruction string 10 to be tested from the beginning. In S9, it is determined whether the command is a check command (svc command). If YES, S10
Proceed to. If NO, the command is executed and S9 is repeated.

In S10, since the check command (svc command) is YES in S9, the collection process or the comparison process is performed (the processes after S21 in FIG. 3 are performed). And
Output if the comparison result is an error.

In step S11, random data is written in the access data area. Further, it is also written in the register 31. S
12 determines whether or not there is a repeat instruction. If yes, then return to S2 and repeat test. On the other hand, in the case of NO, the process ends (END).

As described above, the instruction to be tested is randomly set in the instruction string 10 to be tested, and the check instruction (svc instruction) is set in advance. When the check instruction is executed at the time of execution, the collection process or comparison is performed. Performs processing and saves the correct answer value, or outputs an error when an error occurs by comparing with the correct answer value. Then, after writing the random data to the access data area 11 and the register 31 used by the instruction string under test 10, S3 and subsequent steps are repeated to perform the test. As a result, when the test is repeated, random data is set in the access data area 11 and the register 31 used by the instruction string under test 10, and then the test is repeated, so that it is possible to improve the test accuracy. ,
It is also possible to deal with a test targeting a large-scale instruction string to be tested.

FIG. 3 shows a flow chart of the collection processing / comparison processing of the present invention. This shows a detailed procedure of the collection process or the comparison process in S10 of FIG. In FIG. 3, S21 determines whether the command is a check command. YE
If S, go to S22. If NO, S21
Repeat.

In S22, the mode is determined. This is S2
If YES in 1 indicates that the check command (svc command) has been executed, the check point control unit 1 to which the control is passed.
The second mode determination unit 13 determines whether the mode is the collection mode or the comparison mode.

In S23, the general register data is saved (saved as the correct answer value) because the collection mode is found in S22. This is a general register (register 3 in FIG. 1).
The data 1) is stored as data 1, data 2, ... At the position pointed by the pointer 17.

In step S24, the data in the control register is saved (the interrupt information in the control register is saved as the correct answer value). This saves the interrupt information set in the control register as the correct answer value as data 11, data 12, ... At the position pointed by the pointer 17.

In S25, a random number is generated. S26 resets the access data area. This is the tested instruction sequence 1
The random number generated in S25 is reset in the access data area 11 used by 0. As a result, even if the access data area 11 has the same value in the access data area 11 when the check instruction is executed, random data is reset and the test accuracy can be improved.

In step S27, the instruction following the check instruction is returned to, and the execution of the instruction string under test 10 is restarted. And FIG.
Return to (B). In S28, when the comparison mode is found in S22, the register information is compared. This compares the correct value stored in the previous S23 with the current register information (comparing the correct value with the current register information).

In step S29, the interrupt information is compared. This compares the correct answer value of the interrupt information saved in the previous S24 with the interrupt information of this time (comparing the correct answer value and the current interrupt information).

In step S30, it is determined whether there is an error. In the case of YES, an error result is output in S31 (an error result is output because the register value is different), and the process ends (END).
On the other hand, if NO, a random number is generated in S25 and S26
Reset the random data in the access data area 11 and return to the instruction next to the check instruction in S27.

As described above, when the check instruction (svc instruction) is executed during execution of the instruction string 10 to be tested and control is passed to the check point control unit 12, the mode determination unit 13 of the check point control unit 12 concerned. Determines the mode and saves the register information and interrupt information as the correct value when it is found to be the collection mode, while comparing the correct value with the register information and interrupt information when it is found to be the comparison mode. An error is output to, and when normal, random data is set in the access data area 11 (further, the register 31), and returning to the instruction next to the check instruction (svc instruction) is repeated, and the test is performed. With these, every time the check command is executed, correct values are collected in the collection mode or compared in the comparison mode to perform error checking, and then random data is set in the access data area 11 (further register 31) to improve the test accuracy. It becomes possible.

FIG. 4 is a flowchart (No. 1) for explaining another operation of the present invention. This is a process following (A) in FIG. 3 and shows a procedure for resetting random data in the general register (register 31).

In FIG. 4, S41 generates a random number. In S42, the general register is reset. This is S
The random data generated in 41 is reset in the general register (register information, register 31) and becomes the same value (for example, 0) due to the addition instruction or the shift instruction.
Prevent the test accuracy from decreasing.

The step S43 returns to the instruction following the check instruction. As described above, when the check instruction (svc instruction) is executed at the time of executing the instruction string 10 to be tested and the control is passed to the check point control unit 12, S21 to S2 in FIG.
4, or after the collection process or the comparison process is performed by the processes of S28 to S31, the random data is reset to the general register (register information, register 31), and then the instruction following the check instruction (svc instruction) is returned. Repeat this to conduct the test. As a result, random data can be set in the general register (register 31) and the test accuracy can be improved.

FIG. 5 is a flowchart (part 2) for explaining another operation of the present invention. This is a process following (A) of FIG. 3, and the procedure for resetting random data when the access data area 11 has many data 0 (when the ratio of the same value is equal to or more than the threshold value) is described. It is shown.

In FIG. 5, a step S51 decides whether there are many 0s in the access data area 11. This is because when the percentage of 0s in the access data area 11 used by the instruction string under test 10 is large (for example, when it is more than half).
If YES, the process proceeds to S52. On the other hand, if NO,
Proceed to S54.

In step S52, a random number is generated. The step S53 resets the access data area. This prevents the random data generated in S41 from being reset in the access data area 11 and having the same value (for example, 0) due to the addition instruction and the shift instruction, thereby preventing the test accuracy from decreasing.

The step S54 returns to the instruction following the check instruction. As described above, when the check instruction (svc instruction) is executed at the time of executing the instruction string 10 to be tested and the control is passed to the check point control unit 12, S21 to S2 in FIG.
4, or after the collection process or the comparison process is performed by the processes of S28 to S31, the random data is reset in the access data area 11, and then the check command (s
The test is repeated by returning to the instruction following the vc instruction). As a result, random data can be reset in the access data area 11 and the test accuracy can be improved.

FIG. 6 is a flowchart (part 3) for explaining another operation of the present invention. This is a process following (A) in FIG. 3 and shows a procedure for resetting random data when the register 31 has many 0s (when the ratio of the same value is equal to or more than the threshold value). Is.

In FIG. 6, a step S61 decides whether or not there are many 0s in the data in the register 31. This is the tested instruction sequence 1
When the ratio of 0 in the register 31 used by 0 is large (for example, when the ratio is 0 or more), YES is obtained and S62 is selected.
Proceed to. On the other hand, if NO, the process proceeds to S64.

In step S62, a random number is generated. In S63, the general register (register 31) is reset. This is S
The random data generated in 62 is reset in the general register (register 31), and the same value (for example, 0) due to the addition instruction and the shift instruction is prevented, which prevents the deterioration of the test accuracy.

The step S64 returns to the instruction following the check instruction. As described above, when the check instruction (svc instruction) is executed at the time of executing the instruction string 10 to be tested and the control is passed to the check point control unit 12, S21 to S2 in FIG.
4, or after the collection processing or the comparison processing is performed by the processing of S28 to S31, the random data is reset in the register 31, and then the check instruction (svc instruction)
Repeat the procedure by returning to the next instruction of, and perform the test. As a result, it becomes possible to reset the random data in the register 31 and improve the test accuracy.

[0068]

As described above, according to the present invention,
Since random data is written to the access data area 11 or the register 31 and the test is repeated during correct data collection processing or comparison processing, the randomness of the data in the access data area 11 or the register 31 is ensured. Therefore, it is possible to improve the test accuracy and deal with a test for a large-scale instruction string 10 under test.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a flowchart explaining the operation of the present invention.

FIG. 3 is a flowchart of a collection process / comparison process of the present invention.

FIG. 4 is a flowchart (No. 1) for explaining another operation of the present invention.

FIG. 5 is another operation explanation flowchart (No. 2) of the present invention.

FIG. 6 is another operational explanation flowchart (No. 3) of the present invention.

FIG. 7 is an explanatory diagram of a conventional technique.

[Explanation of Codes] 01: Initial setting unit 011: Random data writing unit 02: Instruction generation control unit 03: Execution environment setting control unit 04: Test routine start control unit 05: Mode change control unit 25: Test repetition control unit 06: Test routine 10: Instruction string to be tested 11: Access data area 12: Check point control unit 13: Mode determination unit 14: Collection mode unit 15, 20: Register information 16, 21: Interrupt information 19: Comparison mode unit 22: Save area 23: Comparison processing unit 26: Access / data resetting control unit 27: Random number generation circuit

Claims (4)

[Claims] 1. A test instruction sequence (10) in which test instructions are randomly arranged is generated and the test instruction sequence (1) is generated.
Instruction generation control unit (02) for setting a check instruction in 0)
When the check instruction set in the instruction string to be tested (10) is executed, control is passed, and correct answer information (register information and interrupt information) is saved in the collecting mode, or correct answer information in the comparison mode. And a check point control unit (12) for determining normality / error by performing comparison of the above and setting random data in the access data area (11) used by the instruction string under test (10). An apparatus for testing an information processing device, characterized by: 2. An under-test instruction sequence (10) in which the under-test instruction is randomly arranged is generated, and the under-test instruction sequence (1) is generated.
Instruction generation control unit (02) for setting a check instruction in 0)
When the check instruction set in the instruction string to be tested (10) is executed, control is passed, and correct answer information (register information and interrupt information) is saved in the collecting mode, or correct answer information in the comparison mode. Checking whether to set the random data when the ratio of the same value in the access data area (11) used by the instruction string under test (10) is higher than the threshold value,・
A test apparatus for an information processing apparatus, comprising: a point control unit (12). 3. A test instruction sequence (10) in which test instructions are randomly arranged is generated, and the test instruction sequence (1) is generated.
Instruction generation control unit (02) for setting a check instruction in 0)
When the check instruction set in the instruction string to be tested (10) is executed, control is passed, and correct answer information (register information and interrupt information) is saved in the collecting mode, or correct answer information in the comparison mode. And a check point control unit (12) for setting the random data in the register (31) used by the instruction string to be tested (10). Testing equipment for information processing equipment. 4. A test instruction sequence (10) in which test instructions are randomly arranged is generated, and the test instruction sequence (1) is generated.
Instruction generation control unit (02) for setting a check instruction in 0)
When the check instruction set in the instruction string to be tested (10) is executed, control is passed, and correct answer information (register information and interrupt information) is saved in the collecting mode, or correct answer information in the comparison mode. Check point control that determines whether normal or error is made by comparing the above, and sets random data when the ratio of the same value in the register (31) used by the instruction string under test (10) is higher than the threshold value. A test apparatus for an information processing apparatus, comprising: a section (12).