JPH07287603A - Engine controller - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to an engine control device, and an object thereof is to provide a device for proactively extracting an initial defect after the contents of the nonvolatile memory are changed on-board. This is achieved by making the stabilized power supply voltage of the engine control device 1 higher than the normal voltage. [Effects] With the above configuration, it is possible to perform screening after changing the contents of the non-volatile memory on-board, and it is possible to identify initial defects in advance, which has the effect of preventing market defects.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an engine control device, and more particularly to an engine control device suitable for detecting an initial failure of an engine control device using a CPU having a nonvolatile memory built in onboard. .

[0002]

2. Description of the Related Art Conventionally, an engine control device is used to control an engine. The engine control device has a CPU which operates according to a predetermined program and a ROM which is a non-volatile memory for storing the program. Is provided. This ROM stores a program and data for determining the fuel injection amount to be supplied to the engine, the ignition timing, and the like. In recent years, a single-chip mode CPU incorporating the above-mentioned ROM has been released. However, it is possible to write a program or data into this ROM in the CPU only once. The method of writing in the etc. is also invented.

As described above, Japanese Patent Application No. 2-20416 discloses a technique for writing data in the ROM incorporated in the CPU after mounting on the substrate.
There is a gazette.

[0004]

In the above prior art, CP is used.
Although it is possible to write U in the built-in ROM after mounting it on the substrate, no consideration is given to extracting initial defects.
That is, there is a problem that a problem occurs after supplying the engine control device to the market.

An object of the present invention is to provide an engine control device which eliminates the above-mentioned drawbacks of the prior art.

[0006]

The above object is to carry out screening by applying a power supply voltage of a non-volatile memory on board to a voltage higher than usual and applying it to operate at a high ambient temperature. Achieved by

[0007]

With the above structure, the non-volatile memory can be screened on-board, and the initial defects can be isolated.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the present invention. 1 is an engine control device. An engine 2 is controlled by the engine control device 1. Although not shown in the figure, the engine 2 is provided with various sensors for indicating the operating state, and signals from the sensors are transmitted to the engine control device 1
Entered in. The engine control device 1 includes an input processing circuit 4 for waveform-processing a signal from the sensor, and a CPU 3 for inputting the sensor signal and calculating an optimum operating state of the engine 2.
And an output circuit 5 which receives the calculated result as a control signal and drives an actuator (not shown) such as a fuel injection device or an ignition device attached to the engine 2. The CPU 3 includes an MPU 7 that operates according to a control program, a ROM 8 that stores a program that operates the MPU 7, a RAM 9 that stores a calculation result of the MPU 7, a signal from the input processing circuit 4, and an output circuit. I for outputting control signal to 5
/ O6 and a communication circuit 10 for data communication with an external device. The engine control device 1 can be electrically connected to a memory rewrite device 11 which is an external device, and
It is connected to the communication circuit 10 in PU3. In the stabilized power supply circuit 12, the battery 13 is used as a power supply, and an optimum constant voltage is always supplied to each part by the power supply line 14. Further, this voltage has a circuit configuration that can be changed by a signal from an external stabilized power supply voltage switching signal generator 15. Here, the ROM 8 is a memory whose contents can be erased and written under special conditions.

FIG. 2 shows a memory map of the CPU 3. FIG. 2A is a memory map of the entire CPU 3,
Reference numeral 3a is an area of the ROM 8, 3b is an external memory space, 3c is an area of the RAM 9, and 3d is an internal register area of the MPU 7. (B) shows a block configuration in the ROM 8.
The ROM 8 is divided into several blocks, as shown in FIG.
In the case of (b), it is divided into 16 blocks A to P,
The contents in the ROM 8 can be erased in each block. The structure of the ROM 8 used in the engine control device 1 is roughly divided into a program area in which a control program is stored, an area in which control data is stored, and a non-erasable area. In this embodiment, block A
.About.K are program areas, and blocks L to P are data areas. FIG. 3 shows the structure of a dedicated register for erasing the data in the ROM 8. The erase register is arranged in the internal register area 3d and is composed of 2 bytes. Each bit of the erase registers 1 and 2 corresponds to each block A to P in the ROM 8, and when this bit is set to 1, for example, the contents of the corresponding block are erased. Therefore, for example, when it is desired to rewrite only the data of the block M which is the data area, first, the erase register 2
The data of the block M may be erased by setting the bit 4 of 1 to 1 and then the data may be written in the block M.

FIG. 4 is a state transition diagram showing an internal state of the CPU 8 when the memory contents in the CPU 8 are rewritten by communication with the memory rewriting device 11 which is an external device. Before the communication with the memory rewrite device 11 is started, the communication rewrite device 11 is in a waiting state in step S1. Here, when the command "INIT" is input from the memory rewrite device 11, the command "INIT" is input to the engine controller 1
From the memory rewrite device 11 to notify that the "INIT" command has been received, and at the same time enter the setting command waiting state of S2. When a command other than "INIT" is input in S1, the <error> command is transmitted and the state returns to the original state S1. Similarly, in each state, when a command corresponding to that state is input, the command corresponding to that is transmitted, and the state transits to the next state. In other cases, the <error> command is transmitted and the process returns to the initial state of S1. From the initial state S1 to "INI
After inputting the "T" command, the process transits to the setting command waiting state of S2 and waits for the next command. If a "PROG" command for entering the program change mode is received in S2, the process proceeds to S3, and "DAT" for entering the data change mode.
If an "A" command is received, the process proceeds to S7, otherwise S1.
Transition to each. When changing to S3, the program change mode is entered, and when changing to S7, the data change mode is entered. When the "GO" command is received in S3, the process goes to S4, and when the change data is input, the process goes to S5 to perform the data change process. After this process is completed, the process waits for the next data to be input, so after sending the <data> command, the process returns to S4. When a predetermined number of data have been input, the process moves from S5 to S6, which waits for an end command. In S6, when the "EXIT" command is received,
The <EXIT> command is transmitted, and the process returns to S1 to end the program change mode. On the other hand, when the "DATA" command is received in S2, the data change mode is entered, and S7
It is the designation of the block in the ROM8 to be changed by
The "DDR" data is received, and the process goes to S8. After receiving the "GO" command, which is the process start command, in S8, S9 and S
At 10, data change processing is performed. In S9, when the data to be changed is received, the process proceeds to S10 and the changing process is executed. After the processing is completed, <data> is transmitted, the process returns to the state of S9 and waits for the next data. When a predetermined number of data have been input, the state shifts to S6 and the state is waiting for the "EXIT" command. After that, as in the program change mode, "EX
When the "IT" command is input, the <EXIT> command is transmitted, the state returns to the state of S1, and the data change mode ends.

FIG. 5 is a flow chart showing the operation of the program in the engine control unit 1 when the communication shown in FIG. 4 is performed. In this embodiment, communication with the memory rewrite device 11 uses serial communication. FIG. 5 shows the processing of the SCI interrupt that occurs when data is transmitted from the memory rewrite device 11. When an SCI interrupt occurs, first, the INIT flag in S20, the PROG flag in S21, and the D in S22.
Check whether the ATA flag is 1. INI in S20
If T flag is 0, it means that the communication is currently in a waiting state, which is S1 in FIG. 4, and it is confirmed in S28 whether or not the data input this time is the “INIT” command.
If it is not the "INIT" command, the process proceeds to S25, the <error> command is output, and INIT, PROG, DAT
Each flag of A is set to 0, and the process of returning to the initial state of communication is performed, and the SCI interrupt process is ended. In S28, "I
If it is confirmed that the command is the "NIT" command, the <INIT> command is output to the memory rewrite device 11 in S29, and the INIT flag is set to 1 to end the processing. If the INIT flag is 1 in S20, it indicates that the state is the state after S2 in FIG. 4, so the state below is confirmed. In S21, it is confirmed by the PROG flag whether the program is in the program change mode. When the flag is 1, the process proceeds to S31, and the program change process is performed. If not,
At S22, the DATA flag is used to confirm whether the mode is the data change mode. If the mode is the data change mode, the process proceeds to S30 and the data change process is performed. If the flag is 0 in S30, it means that the data input this time is "PR" because it is in the state of S2 in FIG.
Whether the command is OG ”or“ DATA ”is determined in S23,
Confirm in S24. If it is determined in S23 that the "PROG" command has been input, the process proceeds to S27, <PROG>
Output the command and set the PROG flag to 1 to enter the program change mode. On the other hand, if it is determined in S24 that the "DATA" command has been input, the process proceeds to S26, <DATA>.
The command output and DATA flag are set to 1 to enter the data change mode. If neither command is confirmed in S23 and S24, it is judged as a data communication error and S
25, the <error> command output and INIT,
Each flag of PROG and DATA is set to 0, and the state returns to the initial state of S1 in FIG.

FIG. 6 is a flow chart for explaining the processing of S31 when the program change mode is entered in the processing of FIG. Since the CPU 3 normally operates with the program stored in the built-in ROM 8, if the contents of the ROM 8 are erased when rewriting the program, the CPU 3 will not operate. To prevent this, when changing the program, the program for rewriting the program is stored in the ROM8.
It is necessary to operate on the RAM 9 instead of operating on it. The process of FIG. 6 shows the process of executing the program for rewriting the program on the RAM 9. The program for rewriting the program originally exists in the ROM 8 and is executed after it is once transferred to the RAM 9. In S40 of FIG. 6, it is confirmed whether the command is the "GO" command. If it is not the "GO" command, the transmitted command is abnormal. Therefore, the process proceeds to S43, after the <error> command is output, each of INIT and PROG is output. Set flag to 0 and return to the initial state. If it is a "GO" command, the process proceeds to S41, and the program for rewriting the program is stored in the ROM 8
9 is performed. After the transfer processing is completed, the program jumps to the program transferred to the RAM 9 in S42 and the RAM 9
Run the above program.

FIG. 7 is a flow chart showing the processing of the program for rewriting the program transferred to the RAM 9 in the above processing. After jumping to the RAM 9 in S42 of FIG. 6, S
Proceeding to step 50, the contents of blocks A to K, which are the program area of the ROM 8, are erased. Here, when data is transmitted from the memory rewrite device 11 by serial communication, an SCI interrupt occurs in the CPU 3, but a vector address is required to jump to the processing program at that time. The vector address contains the start address of the interrupt processing program. In the case of the present embodiment, the vector address is arranged on the block A of the ROM 8, and it is necessary to set the vector address to jump to the RAM 9 when the program for rewriting the program is executed. Further, after the rewriting of the program is completed, when the SCI interrupt occurs, the program on the ROM 8 needs to be executed, so the vector address must be rewritten again. R in S51
In order to execute the program on the AM 9, processing is performed to write the start address of the program on the RAM 9 to the vector address in the block A on the ROM 8. By ending this process, the program can be written. Hereinafter, in S52, the <GO> command is output and GO
Set flag to 1 and remember that the program is being rewritten. In S53, when the program is rewritten, MADR representing the address to write the sequentially transmitted data is initialized, the process is once terminated, and the data waiting state in S4 of FIG. 4 is entered. When data is transmitted in this state, the SCI interrupt is generated again, and the process proceeds to S54 in FIG. S5
In 4, the GO flag is used to confirm whether or not the program is being written. If it is determined that the program is being written, the flow advances to S55 to confirm whether or not the address currently being written is the block A. When it is determined to be the block A, the input data is temporarily stored in the area called MPRG on the RAM 9. The MPRG has the same memory size as the block A, and sequentially stores the transmitted data in the address order. This is the SCI as described above for block A.
Since this vector address exists, writing directly to the ROM 8 destroys the contents of this vector address, and this is a measure for preventing this. On the other hand, S55
If it does not correspond to block A, MADR in S56
The transferred data is written to the address on the ROM 8 located at. Next, in S58, the content of MADR indicating the write address is incremented. With this, the transmitted data has been written in the predetermined address, and the process is temporarily ended until the next data is input. Therefore, the <data> command is output in S59. In S60, it is confirmed whether or not the value of MADR is equal to or larger than a predetermined value, that is, whether or not all data has been written in the program area. If MADR is equal to or less than the predetermined value, it means that the program is still being changed, and the interrupt process is terminated until the next data is input. If it is confirmed in S60 that the program area has been changed to the predetermined value or less, it is determined that all the program area changes have been completed, the GO flag is set to 0, and the completion of the program change process is stored. After that, when the SCI interrupt occurs, since GOflag is 0 in S54, it is confirmed in S62 whether the transmitted data is the "EXIT" command. If the command is not the "EXIT" command, the command is waited until the command is input, and the process is terminated. When the "EXIT" command is confirmed in S62, the process proceeds to S63 and subsequent steps, and the portion of the above block A is stored in the RAM 9
Processing is performed from the MPRG. First, the contents of block A are erased in S63, and the contents of block A are deleted in S64.
Write the contents of PRG. When this writing process is completed, the <EXIT> command is output in S65, and INT, P
Each flag of ROG is set to 0, and the process ends. With the above operation, the program in the ROM 8 can be changed.

FIG. 8 is a flow chart showing the processing when changing the control data of the engine 2. Unlike the program change process described above, the data change process does not require the change program to operate on the RAM 9. If the data change mode is determined in the processing of FIG.
The processing of S70 is executed. In S70, it indicates that the data indicating the block on the ROM 8 to be changed has been input A
Check whether the DDR flag is 1. If the ADDR flag is 0, the data input this time is the data representing the block to be changed, and therefore M in the RAM 9 is determined in S71.
The data is stored in 1. Next, in S72, it is confirmed that the block is a rewritable block, that is, the designated block is a data area block and not a program area block. If it is not in the data area, proceed to S74 to output the <error> command and INI.
Each flag of T and DATA is set to 0, and the initial state is returned. S
After confirming that it is a data area in 72, DCCNTi storing the number of times the block was rewritten in S73.
Check whether the value of is greater than or equal to the specified value. this is,
In the case of a rewritable nonvolatile memory, the number of times of writing is limited due to its structure. If data is written over this limit, the device may be destroyed. In the present invention, in order to prevent this, the number of times of writing is stored for each block, and if the number of times of limitation is exceeded, writing is prohibited. If it is determined in S73 that the number of times of writing has exceeded the predetermined number of times, an error is determined and the process proceeds to S74. S73
If the predetermined number of times of writing has not been reached, the count value of the number of scratches is incremented in S75. In step S76, the <ADDR> command is output, the ADDR flag is set to 1 and the next command is waited for. When the SCI interrupt is generated again, ADDRflag = 1 is set in S70, and the process proceeds to S77. Here, GO flag indicating that the data is being changed
If the data is not being changed, it is confirmed in S84 that the data transmitted this time is the "GO" command. If it is a "GO" command, the above M1 is executed in S85.
The contents of the block indicated by are erased and MADR indicating the address at the time of writing is initialized in S86.
Further, in S87, the <GO> command is output and GO flag
To 1. If GO flag is 1 in S77, that is, if it is determined that the data is being changed, the data to be transmitted thereafter is the data for change, and the data is sequentially written to the designated addresses. In S78, the data transmitted to the address indicated by MADR is written, and in S79, the address (M
ADR) is incremented. In step S80, the <data> command is output to notify the memory writer 11 that the data writing has been completed. M in S82
It is determined whether or not the ADR value has reached a predetermined value, that is, whether or not all the data in the designated block has been rewritten. The process ends. When data is transmitted next time, since GO flag is 0 in S84, the process proceeds to S84. Here, since the "GO" command has already been input, the process proceeds to S88. Here, it is confirmed whether the transmitted data is the "EXIT" command, and if it is the "EXIT" command, the <EXIT> command is output (S89), and if not, the <Error> command is issued.
The command is output (S90) and the process proceeds to S91.
Since a series of processing is finished in S91, each flag of INIT, DATA, and ADDR is cleared to return to the initial state, and the data change processing is finished.

FIG. 9 is a flow chart showing a procedure for carrying out the screening of the CPU 3 having the ROM 8 built-in on board (in the state mounted on the engine control unit 1). The engine control device in which the program or data is written in the ROM 8 by the above method is set to the normal power supply voltage in S93, and the operation is confirmed in S94. In S95, it is determined whether it is operating normally, and if it malfunctions, S104
It becomes a rejected product. If it is normal, the stabilized power supply voltage is switched to a voltage higher than normal in S96. In S97, it is determined whether the power supply voltage has been switched. If the voltage has not been switched, the process returns to S96. When it is switched, S9
In 8, the CPU 3 is energized while the ambient temperature is high to perform screening for a predetermined time. After completion of the screening, the stabilized power supply voltage is switched to the normal voltage in S99.

In S100, it is determined whether the power supply voltage has been switched. If the voltage has not been switched, the process returns to S99. If it has been switched, the operation is confirmed in S101. S
In 102, it is determined whether or not it is operating normally. If it malfunctions, it is rejected in S104, and if it is normal, it passes.

By the above method, after the program or data on the ROM 8 is changed by communication from the external device, the CPU 3 can be screened on the on-board, and the initial defect can be isolated.

[0019]

According to the present invention, after the memory contents in the engine control are changed, the CPU can be screened in the on-board state, and the initial defect can be isolated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of the present invention.

FIG. 2 is a memory map showing a configuration of a ROM with a built-in CPU.

FIG. 3 is a configuration diagram showing a configuration of a register that erases each block in a ROM.

FIG. 4 is a state transition diagram showing a state in the CPU when performing communication with the memory rewrite device.

FIG. 5 is a flowchart showing an operation when shifting to a program change mode or a data change mode.

FIG. 6 is a program RAM in the program change mode.
It is a flow chart which shows operation which transfers to the top.

FIG. 7 is a flowchart showing the contents of a program changing program that operates on a RAM.

FIG. 8 is a flowchart showing the contents of a program when changing data.

FIG. 9 is a flowchart of a procedure for screening a CPU.

[Explanation of symbols]

1 ... Engine control device, 2 ... Engine, 3 ... CPU, 3
a ... ROM area, 3b ... External memory space, 3c ... RAM
Area 3d ... internal register area, 4 ... input processing circuit, 5
... output circuit, 6 ... I / O, 7 ... MPU, 8 ... ROM, 9
... RAM, 10 ... communication circuit, 11 ... memory rewrite machine, 12
... stabilized power supply circuit, 13 ... battery, 14 ... power supply line, 15 ... stabilized power supply voltage switching signal generator.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 15/78 510 G G11C 7/00 (72) Inventor Hideaki Ishikawa 2520 Takaba, Katsuta City, Ibaraki Prefecture Address: Hitachi, Ltd., Automotive Equipment Division

Claims (11)

[Claims] 1. Data can be erased and written,
This data is erased for each predetermined block and includes a read-only nonvolatile memory and a volatile memory capable of writing and reading data, and operates according to a program written in this nonvolatile memory. In an engine control device mounted with a microcomputer, the engine control device can be electrically connected to an external device, and erases the contents of the non-volatile memory built in the microcomputer according to information from the external device,
And an engine control device characterized by being able to write data. 2. The engine control device according to claim 1, wherein the content of the erasable and writable nonvolatile memory is a program for operating the microcomputer. 3. The engine control device according to claim 2, wherein the erasing and writing of the program is executed by a program stored in a volatile memory built in the microcomputer. Control device. 4. The engine control device according to claim 3, wherein the erasing and writing programs stored in the volatile memory are stored in the nonvolatile memory before executing the erasing and writing operations of the nonvolatile memory. An engine control device, which is stored in advance and is transferred to the volatile memory after inputting information from the external device. 5. The engine control device according to claim 1, wherein the contents of the non-volatile memory can be erased and written only by the data for controlling the engine, and the program for operating the microcomputer prohibits the erase and the writing. An engine control device characterized by the above. 6. The engine control device according to claim 5, further comprising means for storing the number of times of erasing and writing of the non-volatile memory, and erasing and writing when the number of times of erasing and writing reaches a predetermined number. An engine control device characterized by prohibiting the engine. 7. The engine control device according to claim 6, wherein means for storing the number of times of erasing and writing of the non-volatile memory is provided for each erasable block. . 8. The engine control device according to claim 1, wherein the power supply voltage of the non-volatile memory can be varied. 9. The engine control device according to claim 1, wherein a voltage value of a stabilized power supply in the engine control device can be varied according to information from an external device. 10. The engine control device according to claim 1, wherein the power supply voltage of the nonvolatile memory can be supplied from an external device. 11. The engine control device according to claim 1, wherein a voltage higher than a power supply voltage of a normal non-volatile memory is applied, and an ambient temperature is increased to operate,
An engine control device characterized by being able to screen non-volatile memory on-board and identify initial defects in non-volatile memory.