JPH0728765A - Program down load monitor circuit - Google Patents

Abstract

PURPOSE:To provide the program down load monitor circuit which easily discriminates the operation confirmation of each CPU. CONSTITUTION:A program is successively loaded into auxiliary CPU systems 21 to 2n from an IPL driver buffer memory 3 of a main CPU system 1 at the time of initialization. The program operates a display driver circuit block 5 through a display I/O port 4 to display a light emitting diode LED by light emission. When the main CPU system 1 and auxiliary CPU systems 21 to 2n are normally operated during the program loading and the program is normally loaded, light emitting diodes LED are lit. Thus, the program is normally loaded down, and it is visually confirmed that the main CPU system or auxiliary CPU systems 21 to 2n are normal. Faulty systems out of the main CPU system 1 and auxiliary CPU systems 21 to 2n are easily discriminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program download monitor circuit of a CPU system which is initialized by initial program loading.

[0002]

2. Description of the Related Art Conventionally, a main (upper) CPU system block (hereinafter referred to as a main CPU system) is connected to a plurality of auxiliary (lower) CPU system blocks (hereinafter referred to as an auxiliary CPU system), and a main CPU system of this main CPU system is connected. An initial program that loads a program from the main CPU system into a plurality of auxiliary CPU systems, for example, during routine initialization.
There is a loading method.

[0003]

However, in the case of the initial program loading method, the main CPU
When loading the auxiliary CPU system from the system, it is necessary to electrically check whether each auxiliary CPU system is loaded with a program or whether each auxiliary CPU system is operating reliably. There is a problem that it is not easy to confirm the operation.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a program download monitor circuit capable of easily confirming the operation of each CPU system.

[0005]

A program download monitor circuit according to the present invention is a program download monitor circuit which has a plurality of CPU systems and initializes a program by initial program loading. Each of the CPUs includes a notification system for displaying an operation, which is connected to the CPU system, and includes a content for driving the notification circuit in the program.
Each of the notification circuits is driven when the program of the system is loaded.

[0006]

According to the present invention, each CPU system is connected to an informing circuit for displaying an operation, and the contents of driving the informing circuit are included in the program. When the program of each CPU system is loaded by initial program loading, the CPU system is loaded. If the program is reliably loaded and the CPU system is normal, the notification circuit is driven, so that the operation of the CPU system can be reliably known.

[0007]

[Embodiment] The program, download, and
An embodiment of the monitor circuit will be described with reference to the drawings.

As shown in FIG. 2, the main CPU system 1
, The auxiliary CPU systems 2 _{1 to} 2 _n are sequentially arranged in series, and the main CPU system 1 is loaded with a program to the auxiliary CPU systems 2 ₁ to 2 _n at the time of initialization. , IPL) driver buffer memory 3 is connected. Further, the IPL driver buffer memory 3 is added with a subroutine for controlling display operation at the time of setting.

The main CPU system 1 and the auxiliary C
As shown in FIG. 1, a display I / O port 4 is connected to the PU systems 2 _{1 to} 2 _n , and a notification circuit is configured in the display I / O port 4 via a display driver circuit block 5. A series circuit of a light emitting diode LED and a resistor R is connected. The display I / O port 4 is turned off in the default state when the system is reset such as when the power is turned on, and the light emitting diode LED is kept in the off state.

Then, at the time of initialization, each auxiliary C is loaded from the IPL driver buffer memory 3 of the main CPU system 1.
The PU system 2 ₁ to 2 _n, performs a program loading sequence or simultaneously. In addition, this program causes the display driver circuit block 5 to be actuated via the display I / O port 4 so that the light emitting diode LED lights up and emits light.

Therefore, the program-loaded main CPU system 1 or each auxiliary CPU system 2 is loaded.
_{When 1} ~ _2n is operating normally and the program is loaded normally, the light emitting diode LED
, The program is downloaded normally, and the main CPU system 1 or each auxiliary CPU
It is possible to visually confirm that the systems 2 _{1 to} 2 _n are operating normally. Therefore, it is possible to easily determine the main CPU system 1 or the auxiliary CPU system 2 ₁ to 2 _n of defective visually state.

Further, in the default state where the system is reset such as when the power is turned on, the display I / O port 4 is turned off and the light emitting diode LED is turned off, so that misidentification can be prevented.

Furthermore, each time the main CPU system 1 and each of the auxiliary CPU systems 2 ₁ to 2 _n are sequentially program-loaded, the corresponding light emitting diode LEDs are lit and displayed, so that the main CPU system 1 and the auxiliary CPU system 2 _It can be used as a guide for checking the operation of _{1 to} 2 _n .

Each of the auxiliary CPU systems 2 ₁ to 2
_{The n} is not limited to those arranged in series as shown in FIG. 2, but the operation can be similarly displayed even if they are arranged in parallel as shown in FIG. In this case also, sequential or each auxiliary CPU system 2 ₁ to 2 _n, it may be programmed loading at the same time.

[0015]

According to the program download monitor circuit of the present invention, when the program is loaded into each CPU system by IPL, if the program is reliably loaded into the CPU system and the CPU system is normal, Since the notification circuit is driven via the above, the normal and abnormal operation of each CPU system can be reliably determined.

[Brief description of drawings]

FIG. 1 is a block diagram showing electrical connections of a main CPU system and auxiliary CPU systems of an embodiment of a program download monitor circuit of the present invention.

FIG. 2 is a block diagram showing an electrical connection of the main CPU system and the auxiliary CPU system of the same.

FIG. 3 is a block diagram showing electrical connection of a main CPU system and an auxiliary CPU system of another embodiment of the same.

[Explanation of symbols]

1 Main CPU system block 2 ₁ to 2 _n Auxiliary CPU system block LED Light emitting diode as notification circuit

Claims (1)

[Claims] 1. A program download monitor circuit having a plurality of CPU systems for initializing a program by initial program loading, wherein each CPU system is connected to a notification circuit for displaying an operation, and A program characterized by including the contents for driving the notification circuit in the program, and driving the notification circuit at the time of program loading of each CPU system.
Download monitor circuit.