JPH0728774A - Computer system - Google Patents

Abstract

(57) [Abstract] [Purpose] In a bus control method for a computer system, two types of buses are directly connected to a processor unit, and a means for controlling them is provided, whereby a logic and a hierarchy for bus control are provided. We will reduce the number of interrupts and simplify the interrupt processing to improve the development efficiency and performance of computer systems. Constitution: A plurality of buses 102 and 103 of different speeds directly connected to a microprocessor, respective input / output commands to the buses, control means for distributing the commands to a plurality of buses, and input / output requests to a target bus Each bus has control means for issuing. On the other hand, it has an interrupt control means for each bus which has a register which receives an interrupt from each bus and reflects from which IO of each bus, a means for controlling the priority of these, and an interrupt vector for each bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control method in a microprocessor system architecture,
In particular, it relates to a computer system capable of reducing and simplifying the logic of a bus adapter.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a conventional bus control system. In FIG. 2, since a plurality of IO buses having different speeds are mixed in one system device, the system bus 2
06 bus adapter for connecting high-speed IO bus (H
high_BA202) and a bus adapter (Low_BA203) for connecting a low-speed IO bus are connected, and a bus hierarchization method for controlling each IO bus is adopted. In such a conventional hardware configuration, when an input / output command is issued from the CPU 200 to the IO, the bus control unit (BCU) 201 determines which of the high speed bus adapter 202 and the low speed bus adapter 203 is to be accessed. This is generally determined by which of the address spaces assigned to each bus the specified address is in. For example, if an input / output instruction is issued from the CPU 200 and this is a read access to the low-speed IO 205 under the low-speed bus adapter 203, B
The CU 201 issues a read request to the low speed bus adapter 203. The low-speed bus adapter 203 determines whether or not the low-speed IO bus 207 is currently available, and if so, sends this read request to the low-speed IO 205. If another low-speed IO is using the low-speed bus 207 and cannot use this request, the low-speed bus 20
Hold this request event until 7 is released. During this period, the low-speed bus adapter 203 must also control the other low-speed IO in parallel with this. As for parallelization of such bus control, there is a method of providing a buffer inside the low-speed bus adapter 203 and controlling it, as described in JP-A-61-1210465. Next, in response to this request, low-speed IO 205
Sends data via the low-speed bus 207,
The low-speed bus adapter 203 receives this, and the BCU 20
Issue a bus use request to start data transfer to 1. Again, if system bus 206 is busy, then data and request events must be held until system bus 206 becomes available. In the meantime, when the use request of the system bus 206 such as interrupt / DMA from another low-speed IO under the control of the low-speed bus 207 occurs, the low-speed bus adapter 203 must hold the event and control the guarantee of the order in parallel. I won't. This is a high speed bus adapter 2
The same applies to 02. Next, low-speed bus adapter 20
Data from the BCU via the system bus 206
When it reaches 201, the BCU 201 writes data to the internal register of the CPU 200. Such a complicated process is performed from when the read request is issued to the low-speed IO 205 to when the CPU 200 actually receives the data. The system bus 206 is generally fast. For this reason, since the low-speed bus adapter 203 is particularly located between the low-speed bus under the control of the low-speed bus adapter 203, the control for obtaining this synchronization is also very complicated. For this reason, in the conventional multiple bus control methods having different speeds by the hardware configuration, there are many bus layers, and the logical scale of the bus adapter units such as the low-speed bus adapters 202 and 203 becomes large. The BCU201 also has a CPU
It must always be determined which bus adapter section the I / O request from the 200 is accessing. For this reason, it is necessary to have a logic for internally holding the information on the IO space assigned to each bus, which also increases the logical scale. Although omitted in the above description of the process, BC
When there is a request from the CPU 200 in U201 as well, it is necessary to monitor the usage status of the system bus 206, hold request events, and guarantee the order. In reality, it takes a huge amount of time and money to develop a system unit having a plurality of buses having different speeds. On the other hand, in terms of interrupt processing by software, especially the operating system, it can be seen that there is another big problem. FIG. 3 is a flowchart showing an example of interrupt processing for the system device having the hardware configuration shown in FIG. For example, if an interrupt occurs from the high-speed IO 204, the high-speed bus adapter 20
2 and the BCU 201, and an interrupt report is sent to the CPU 200. The CPU 200 starts the processing of FIG. 3 starting from the address registered in the interrupt vector. First, in step 300, it is determined which bus adapter unit the interrupt is from. For this purpose, the system bus interrupt information register, which is generally inside the BCU 201, is read, and it is determined whether the corresponding bit is set. That is, B
The CU 201 controls the bit of the corresponding system bus interrupt information register to 1 when an interrupt is reported via the system bus 202. In the case of this example, since it is an interrupt from the high-speed IO 204, the processing moves to step 304. In step 304, in order to determine which high-speed IO under the high-speed bus adapter 202 is the interrupt, the high-speed bus interrupt information register in the high-speed bus adapter 202 is read as in the BCU 201. Here, the bit corresponding to the high-speed IO 204 is 1. In other words, high-speed IO like BCU201
If there is an interrupt from 204, high speed bus adapter 2
02 controls to set 1 to the corresponding bit position of this register. When it is determined that the interrupt is from the high-speed IO 204, the interrupt reaping process dedicated to the high-speed IO 204 is executed in step 305. As a result, the interrupt factor from the high-speed IO 204 is cut off, and then the bit corresponding to the high-speed IO 204 of the information register of the high-speed bus adapter 202 is cleared to 0 in step 306. In this series of processing,
There are the following two problems. First, the interrupt reaping action executed in steps 304 and 305 is performed by the CPU 2 for the high-speed bus adapter 202 and the high-speed IO 204.
System bus 2 because it is executed by input / output command of 00
06 and high speed bus 208 must be used. In particular, if the system bus 206 is used in step 304, other bus adapter units such as the low-speed bus adapter 203 enter the waiting state during this period. For this reason, not only adding to the complexity of the above-mentioned data transfer control, but if there is an IO that frequently causes interrupts, the bus will be loaded due to this control, and user data such as DMA, which is originally important, will be loaded. Will interfere with the transfer.
The same applies to the interrupt from the low speed bus adapter 203. Secondly, from the viewpoint of software processing, the processing steps become large because the interrupt processing must be performed by taking the hierarchy of steps 304 and 305. For this reason, not only the performance of the hardware cannot be sufficiently drawn out, but also the possibility that an interrupt from another IO will occur during the processing increases. It must be assumed that will stand. Therefore, not only the processing becomes more complicated and the performance as a system is adversely affected, but also the development of this processing requires a huge cost and period. As described above, the conventional hardware configuration shown in FIG. 2 is extremely disadvantageous in terms of development effort, performance of the system device, and software for controlling the system device.

[0003]

In the above-mentioned prior art, since a plurality of buses having different speeds are mixed in one system unit, the logical scale of the bus control unit is increased, the number of layers is increased, and the interrupt processing is complicated. Now, there arises a problem of deterioration in the performance of the system unit. An object of the present invention is to provide a computer system capable of improving such a problem and reducing and simplifying the logic of a bus adapter which forms a multi-layered bus.

[0004]

To achieve the above object, the computer system of the present invention provides a high-speed bus for connecting a high-speed IO, a low-speed bus for connecting a low-speed IO, and It has input / output instructions for different buses, and when an input / output instruction for IO is executed, it determines which bus is connected to the input / output by the above instruction, and inputs to each bus. Control means for allocating output operation (input / output control unit 4 in FIG.
00) and the individual control means (high-speed bus control unit 40) for each bus that receives this and issues an input / output request to each bus.
1. The low-speed bus control unit 402) is provided, and by incorporating these control means in the microprocessor, it is possible to directly connect the high-speed bus and the low-speed bus to the processor. In addition, a register (high-speed interrupt register 505, low-speed interrupt register 506) for receiving an interrupt from the above bus, reflecting which IO of each bus the interrupt is from, and providing the information to software is provided for each bus individually. The control means (interrupt control unit 501 for high-speed bus, interrupt control unit 502 for low-speed bus) that it has and the priority order of interrupts from each bus are determined, and when simultaneous interrupts occur, the priority order set by software A means for controlling which interrupt is to be reported to the instruction execution unit (interrupt control unit 500 having the priority determination control register 507) is built in the microprocessor, and when an interrupt occurs, the interrupt vector is individually provided for each bus. By providing it, which IO bus from which It is characterized in that to determine whether the interrupt.

[0005]

In the present invention, when the input / output control unit receives an input / output instruction for accessing each bus from the instruction execution section, the input / output control unit determines from the instruction code section which bus it is an access instruction for. Alternatively, allocate to a low speed control unit. For example, when a read instruction to the low-speed bus is given from the instruction execution unit to the input / output control unit, the input / output control unit requests the low-speed bus control unit to execute the instruction. In the low speed bus control unit,
It only checks if the low-speed IO bus is currently in use, and if it is available, immediately issues a read request to the target low-speed IO. When the read data is returned from this IO, the low speed bus control unit immediately picks it up and passes it to the input / output control unit. The input / output control unit further passes the data requested by the instruction execution unit. As a result, the conventional low-speed and high-speed bus adapters (refer to FIG.
2, 203) to monitor the usage status of the system bus, control logic for guaranteeing event retention / sequentiality, and control logic which bus adapter control unit should issue a request from the address judgment by the bus control unit. Can be omitted. This can significantly reduce the logical scale that must be developed. Also,
In interrupt control, for example, I connected to a high-speed bus
Assume that an interrupt has occurred from O. The high-speed bus interrupt control unit immediately receives this, sets the bit corresponding to the interrupted IO in the high-speed bus interrupt information register to 1 and reports the interrupt to the interrupt control unit. Since the interrupt control unit is an interrupt from the high speed bus, it outputs the address of the high speed bus interrupt vector to the instruction execution unit. In the instruction execution unit, the instruction execution address is moved to that address, and the high speed bus interrupt processing is immediately executed by the operating system. The operating system immediately reads the high-speed interrupt register, determines which high-speed IO the interrupt is from, and executes interrupt retrieving for each IO. After that, the corresponding bit of the high speed bus interrupt register is cleared, and the interrupt processing ends. Therefore, the steps 300 and 306 in FIG. 3 of the above-mentioned prior art are not required, the interrupt processing by the operating system can be simplified, and the processing overhead can be reduced. Since the high-speed bus interrupt register is an internal register of the microprocessor, it does not use the system bus. Therefore, normal data transfer is not hindered and system performance is not deteriorated. Further, when interrupts are simultaneously reported from the interrupt control units for the high speed bus and the low speed bus, the interrupt vector address is output to the instruction control unit according to the priority of the interrupt priority setting register which can be set by software. As a result, even if interrupt reports are issued at the same time, the interrupt processing is executed in the priority order preset by the operating system.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of a processor system according to an embodiment of the present invention. Where the central processing unit (CPU)
100 is a main memory (MS) 101 and a high-speed bus 102,
It is configured to be directly connected to a plurality of buses such as the low speed bus 103, and the high speed bus 104 is connected to the high speed IO 104.
A low speed IO 105 is connected to the low speed bus 103.

FIG. 4 shows the input / output function of the system shown in FIG. The microprocessor 10 includes an input / output control unit 400, and a high-speed bus control unit 401 and a low-speed bus control unit 402, which are separately provided for the number of buses. For example, a low speed I connected to a low speed bus
When the read instruction (Low_IO_Read) to O is executed, the input / output control unit 400 determines to which bus the data is requested. Although the structure of the instruction code is not shown, it is clear from the operation code that it is an access instruction to the low-speed IO bus, so a read request is sent to the low-speed bus control unit 402. Since it is separate from the instruction for accessing the high-speed IO bus, the I / O control unit 400 corresponding to the BCU 201 described in the prior art determines to which bus adapter unit the request should be issued, and the system bus 20.
The determination of whether 6 is in use and the control logic that guarantees ordering can be omitted. This allows the input / output control unit 400 to have a smaller logical scale than the BCU 201. The low-speed bus control unit 402 that has received the request confirms that the low-speed bus is not being used by another IO, and makes a read request directly to the target low-speed IO. If the low-speed bus is being used by another IO, the low-speed bus control unit 40
2 holds the request until the low speed bus is released.
Further, control of other low speed IO is also performed in parallel. When this low-speed bus is released, the low-speed bus control unit 402
Immediately sends the request to the target low speed IO via the low speed bus. In response to the request, the low-speed IO sends data to the low-speed bus control unit 402 via the low-speed bus.
Similar to the above, it is also executed in the case of an access instruction to the high speed IO. In this way, the conventional system bus (2 in FIG.
06) does not exist, logic control can be largely omitted.

On the other hand, in the interrupt processing, the interrupt from the high speed IO 104 in FIG. 5 is taken into the high speed bus interrupt control unit 501 through the high speed bus 102. The high-speed bus interrupt control unit 501 sets 1 in the bit corresponding to the IO causing the interrupt in the built-in high-speed bus interrupt register 505. Next, the high-speed bus interrupt control unit 501 reports the interrupt to the interrupt control unit 500, and branches to the high-speed interrupt vector 503. High-speed interrupt vector 503
In the interrupt processing by the operating system that exists at the address, the high speed bus interrupt register 505 is immediately read to determine what is the IO that has issued the interrupt report. In this case, since it is the interrupt of the high-speed IO 104, the individual interrupt processing corresponding to the high-speed IO 104 is executed, and then the bit of the high-speed bus interrupt register 505 is cleared and the interrupt processing is finished. Therefore, in the interrupt processing shown in FIG.
Since 0 and 306 are unnecessary, interrupt processing by the operating system can be simplified. Further, the high speed bus interrupt register 505 is read by the CPU 1
Since it is the read operation of the internal register of 00, the system performance can be improved because the system bus need not be used as compared with the hardware configuration described in the related art of FIG. 2 which shares the system bus 206. Furthermore, when interrupts are simultaneously generated from both the high-speed bus interrupt control unit 501 and the low-speed bus interrupt control unit 502, the interrupt control unit 500 is prioritized according to the priority set in advance by the operating system in the priority control register 507. The higher-ranked interrupt report is transmitted to the instruction register 403. For example, it is assumed that data is set in the priority control register 507 so as to prioritize interrupts from the low speed bus. When the interrupt reports from the high-speed bus interrupt control unit 501 and the low-speed bus interrupt control unit 502 occur simultaneously, the interrupt control unit 500 reports the interrupt report from the low-speed bus interrupt control unit 502 to the instruction execution unit 403 first. Then, the address of the low-speed bus interrupt vector 504 is output to the instruction execution unit 403. The instruction execution unit 403 uses the low-speed bus interrupt vector 50.
Branch to address 4 and interrupt vector 50 for low-speed bus
The execution of the interrupt process for the low speed IO existing at the address of 4 is started. As described above, in this interrupt processing, the processing corresponding to steps 301 and 302 in FIG. 3 can be immediately executed. When this interrupt processing ends, that is, when the instruction execution unit 403 executes an interrupt processing end instruction (generally called an interrupt return instruction), the interrupt control unit 500 interrupts the pending interrupt from the high-speed interrupt control unit 501. It reports to the instruction execution unit 403 and outputs the address of the high-speed bus interrupt vector 503 to the instruction execution unit 403. Accordingly, it is possible to execute the high-speed IO interrupt processing of the operating system in response to the interrupt report from the high-speed interrupt control unit 501.

[0009]

According to the present invention, it is possible to reduce the load of bus control, reduce the logical scale of the bus, and avoid the hierarchical structure. Further, by simplifying the hierarchy of bus control, it is possible to simplify software interrupt processing. Furthermore, according to this system structure, I connected to different buses
It is possible to process O in parallel.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a processor system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional bus control system.

FIG. 3 is a flowchart showing an interrupt control procedure for the system of FIG.

FIG. 4 is a diagram showing an input / output control unit of a processor system according to an embodiment of the present invention.

FIG. 5 is a diagram showing an interrupt control unit of a processor system according to an embodiment of the present invention.

[Explanation of symbols]

 100 CPU (Central Control Unit) 101 MS (Main Memory) 102 High Speed Bus 103 Low Speed Bus 104 High Speed IO (Input / Output Device) 105 Low Speed IO (Input / Output Device) 200 CPU (Central Processing Unit) 201 BCU (Bus Control Unit) 202 High_BA (high speed bus adapter) 203 Low_BA (low speed bus adapter) 204 High speed IO (input / output device) 205 Low speed IO (input / output device) 206 System bus 400 Input / output control unit 401 High speed bus control unit 402 Low speed bus control unit 403 Instruction Execution Unit 500 Interrupt Control Unit 501 Interrupt Control Unit for High Speed Bus 502 Interrupt Control Unit for Low Speed Bus 503 Interrupt Vector for High Speed Bus 504 Interrupt Vector for Low Speed Bus 505 Interrupt Register for High Speed Bus 50 Interrupt register 507 Priority control register for low-speed bus

Claims (2)

[Claims] 1. A computer system having a high-speed bus for connecting a high-speed IO, a low-speed bus for connecting a low-speed IO, and an input / output instruction for both buses, wherein an input / output instruction for the IO is executed. In this case, the control means for determining which bus is connected to the IO connected to the IO based on the above instruction, and for allocating the input / output operation to the bus, and the individual control for each bus issuing an input / output request to the bus A computer system comprising a microprocessor including means, and a high-speed bus and a low-speed bus are directly connected to the processor. 2. A control unit for each bus, which holds information indicating from which IO of the bus the interrupt is issued and has a readable / writable register, and preset when an interrupt from each bus occurs at the same time. And a control means for determining priority according to the priority order, and a control means for setting an address of the interrupt vector for each bus individually and moving an instruction execution address to the address to perform interrupt processing. The computer system according to claim 1, wherein: