JPH0729379A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH0729379A JPH0729379A JP5174037A JP17403793A JPH0729379A JP H0729379 A JPH0729379 A JP H0729379A JP 5174037 A JP5174037 A JP 5174037A JP 17403793 A JP17403793 A JP 17403793A JP H0729379 A JPH0729379 A JP H0729379A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- data line
- circuit
- supply voltage
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000001514 detection method Methods 0.000 claims abstract description 21
- 238000007599 discharging Methods 0.000 claims abstract description 13
- 230000001902 propagating effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 4
- 230000006378 damage Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
- Dram (AREA)
Abstract
(57)【要約】
【目的】電源電圧が低い時には安定した動作を確保しな
がら、電源電圧が高い時には高速な読みだし動作を可能
な半導体記憶装置を提供する。
【構成】電源電圧の変動により可変となる出力電圧を持
つ電源電位検出回路１５を設け、その出力信号によりデ
−タ線充電回路６および、放電回路４を制御させること
により、デ−タ線２の電圧レベルを電源電圧の変動に合
わせ可変させる。電源電圧が低い状態では、デ−タ線放
電回路４を非活性化させて動作を安定させる。また、電
源電圧の上昇に伴いデ−タ線放電回路は徐々に活性化さ
れ、高電源電圧時には、完全に活性化される。
【効果】デ−タ線充放電回路の動作を電源電圧の変動に
よらず常に最適化する事ができるため、広範囲な電源電
圧で安定した高速動作が可能である。
(57) [Abstract] [Purpose] To provide a semiconductor memory device capable of high-speed read operation when the power supply voltage is high while ensuring stable operation when the power supply voltage is low. A power supply potential detection circuit 15 having an output voltage that is variable due to fluctuations in the power supply voltage is provided, and the data line charging circuit 6 and the discharging circuit 4 are controlled by the output signal thereof, whereby the data line 2 is controlled. The voltage level of is changed according to the fluctuation of the power supply voltage. When the power supply voltage is low, the data line discharge circuit 4 is inactivated to stabilize the operation. Further, the data line discharge circuit is gradually activated as the power supply voltage rises, and is fully activated at the high power supply voltage. [Effect] Since the operation of the data line charging / discharging circuit can be always optimized regardless of the fluctuation of the power supply voltage, stable high speed operation can be performed in a wide range of power supply voltage.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体記憶装置に関す
るものであり、広範囲な電源電圧で高速動作可能な半導
体記憶装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of operating at high speed with a wide range of power supply voltages.
【０００２】[0002]
【従来の技術】従来の半導体記憶装置のブロック図を図
４に示す。１はメモリセル、２は相補なデ−タ線、３は
ワ−ド線、４はデ−タ線放電回路、５はカラムゲ−ト、
６はデ−タ線充電回路、７はセンスアンプ、８は出力回
路、９はデ−タ出力端子、１０は入力端子、１１は入力
バッファ、１２は入力信号遷移検出回路、１３は制御パ
ルス発生回路、１４はワ−ド線駆動回路である。2. Description of the Related Art A block diagram of a conventional semiconductor memory device is shown in FIG. 1 is a memory cell, 2 is a complementary data line, 3 is a word line, 4 is a data line discharge circuit, 5 is a column gate,
6 is a data line charging circuit, 7 is a sense amplifier, 8 is an output circuit, 9 is a data output terminal, 10 is an input terminal, 11 is an input buffer, 12 is an input signal transition detection circuit, and 13 is a control pulse generator. The circuit, 14 is a word line drive circuit.
【０００３】情報の読みだし時に半導体記憶装置に外部
より加わる入力信号が変化したとき、１２の入力信号遷
移検出回路においてこれらの信号の変化を検知し、１３
の制御パルス発生回路において制御パルス信号を生成
し、この制御パルスにより、デ―タ線に付加された４の
デ−タ線放電回路および６のデ−タ線充電回路を一定期
間動作させ、デ−タ線の充電および放電をおこない、デ
−タ線の電位レベルを最適化し、アクセスの高速化をは
かっていた。When input signals externally applied to the semiconductor memory device at the time of reading information are changed, 12 input signal transition detecting circuits detect the changes of these signals, and 13
In the control pulse generating circuit, the control pulse signal is generated, and by this control pulse, the data line discharging circuit 4 and the data line charging circuit 6 added to the data line are operated for a certain period, -The data line was charged and discharged, the potential level of the data line was optimized, and the access speed was increased.
【０００４】[0004]
【発明が解決しようとする課題】上記の従来半導体記憶
装置では，読みだし時には電源電圧に関係無く常にデ−
タ線充電回路とデ−タ線放電回路が、活性化状態に成っ
ている。例えば電池駆動の半導体記憶装置では、電源電
圧が５Ｖ近傍の電圧動作時には、データ線充電回路によ
り、デ−タ線が過充電状態と成っているが、デ−タ線の
電位を放電する放電回路が動作しておりデ−タの伝搬が
正常に行われている。しかし、電池の能力が衰え、電源
電圧が３Ｖを下回るような低電圧動作時には、デ−タ線
の充電が十分でなく、更にデ−タ線放電回路が動作して
いる為に、デ−タ線の電位が下がりすぎデ−タを正常に
伝搬することができず、アクセスの遅れやデ−タの破壊
が生じていた。In the above conventional semiconductor memory device, the data is always read at the time of reading regardless of the power supply voltage.
The data line charging circuit and the data line discharging circuit are in the activated state. For example, in a battery-powered semiconductor memory device, a data line charging circuit causes a data line to be overcharged during a voltage operation near a power supply voltage of 5 V, but a discharge circuit for discharging the potential of the data line. Is operating and data is being propagated normally. However, at the time of low voltage operation in which the capacity of the battery deteriorates and the power supply voltage falls below 3V, the data line is not sufficiently charged, and the data line discharge circuit is operating. The potential of the line was too low to propagate the data normally, resulting in delay of access and destruction of data.
【０００５】本発明は、この様な問題を解決するもの
で、その目的とするところは、電源電圧が低い時には安
定した動作を確保しながら、電源電圧が高い時には高速
な読みだし動作を可能にした半導体記憶装置を提供する
ことにある。The present invention solves such a problem, and an object thereof is to ensure stable operation when the power supply voltage is low, while enabling high-speed reading operation when the power supply voltage is high. Another object of the present invention is to provide such a semiconductor memory device.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体記憶装置
は、デ−タを記憶するためのメモリセルのメモリセル群
と、前期メモリセル群の中から選択されたメモリセルか
ら情報を伝搬するためのメモリセルに接続されたデ−タ
線と、前期デ−タ線から高速にメモリセルの情報を伝搬
するためのデ−タ線充電回路と、デ−タ線の過充電を放
電するためのデ−タ線放電回路とを具備した半導体記憶
装置において、電源電圧の変動を検知し、電源電圧の変
動とともに出力の電圧レベルを可変させ、その出力電圧
によりデ−タ線充電回路およびデ−タ線放電回路の少な
くとも一方の動作を制御する電源電位検出回路とを具備
したことを特徴とする。A semiconductor memory device of the present invention propagates information from a memory cell group of memory cells for storing data and a memory cell selected from the memory cell group of the previous term. A data line connected to the memory cell, a data line charging circuit for rapidly transmitting the information of the memory cell from the previous data line, and a discharge for overcharging the data line. In the semiconductor memory device including the data line discharge circuit of the above, the fluctuation of the power supply voltage is detected, the output voltage level is changed along with the fluctuation of the power supply voltage, and the data line charging circuit and the data line charging circuit A power supply potential detection circuit for controlling the operation of at least one of the power line discharge circuits.
【０００７】[0007]
【作用】上記手段によれば、デ−タ線の充電回路および
放電回路を制御する電源電位検出回路の出力信号を、電
源電圧の変化とともに電圧レベルを可変させ、この電源
電位検出回路の出力信号により、デ−タ線充電回路およ
びデ−タ線放電回路の動作を制御し、デ−タ線の電位レ
ベルを常に良好に保つことにより広い電源電圧範囲で高
速な読みだしが可能となる。According to the above means, the output signal of the power supply potential detecting circuit for controlling the charging circuit and the discharging circuit of the data line is changed in voltage level with the change of the power supply voltage. As a result, the operations of the data line charging circuit and the data line discharging circuit are controlled, and the potential level of the data line is always kept good, so that high-speed reading is possible in a wide power supply voltage range.
【０００８】[0008]
【実施例】以下に本発明について，実施例に基づいて説
明する。図１は、本発明の一実施例を示す半導体記憶装
置のブロック図である。１はメモリセル、２は相補なデ
−タ線、３はワ−ド線、４はデ−タ線放電回路、５はカ
ラムゲ−ト、６はデ−タ線充電回路、７はセンスアン
プ、８は出力回路、９はデ−タ出力端子、１０は入力端
子、１１は入力バッファ、１２は入力信号遷移検出回
路、１３は制御パルス発生回路、１４はワ−ド線駆動回
路、１５は電源電位検出回路、Ｐ１はＰチャネルトラン
ジスタ、Ｎ１，Ｎ２，Ｎ３，Ｎ４，Ｎ５，Ｎ６はＮチャ
ネルトランジスタである。EXAMPLES The present invention will be described below based on examples. FIG. 1 is a block diagram of a semiconductor memory device showing an embodiment of the present invention. 1 is a memory cell, 2 is a complementary data line, 3 is a word line, 4 is a data line discharging circuit, 5 is a column gate, 6 is a data line charging circuit, 7 is a sense amplifier, 8 is an output circuit, 9 is a data output terminal, 10 is an input terminal, 11 is an input buffer, 12 is an input signal transition detection circuit, 13 is a control pulse generation circuit, 14 is a word line drive circuit, and 15 is a power supply. A potential detection circuit, P1 is a P-channel transistor, and N1, N2, N3, N4, N5 and N6 are N-channel transistors.
【０００９】実施例の主要部分である図１のデ−タ線放
電回路と選択回路の構成について説明する。４のデ−タ
線放電回路は相補なデ−タ線にドレインとゲ−トをそれ
ぞれ接続された２つのＮチャネルトランジスタＮ１、Ｎ
２と、前記ＮチャネルトランジスタＮ１、Ｎ２のソ−ス
をドレインに接続したＮチャネルトランジスタＮ３の３
つのトランジスタによって構成されている。２のデ−タ
線は放電回路を構成するこれらのＮチャネルトランジス
タのソ−ス、ドレインを介してＧＮＤに接地されてお
り、デ−タ線からの放電はこのＮチャネルトランジスタ
Ｎ３のゲ−トに入力される信号の電位レベルによって制
御される。図２に示す電源電位検出回路はソースをＶＤ
Ｄに接続されたＰチャネルトランジスタＰ１と、Ｐチャ
ネルトランジスタＰ１と直列に接続されたＮチャネルト
ランジＮ４、Ｎ５および、ゲ−トをＶＤＤに接続された
ＮチャネルトランジＮ６によって構成されており、前記
１３より出力される制御パルスが、このＰチャネルトラ
ンジスタＰ１のゲ−トに入力され、電源電位検出回路選
択回路の出力を制御する。電源電位検出回路の出力は常
時、デ−タ線放電回路のＮチャネルトランジスタＮ３の
ゲ−トと接続されている。The configurations of the data line discharge circuit and the selection circuit of FIG. 1, which are the main parts of the embodiment, will be described. The data line discharge circuit of No. 4 has two N-channel transistors N1 and N1 whose drain and gate are connected to complementary data lines, respectively.
2 and 3 of N-channel transistor N3 in which the source of the N-channel transistors N1 and N2 is connected to the drain.
It is composed of two transistors. The data line No. 2 is grounded to GND via the source and drain of these N-channel transistors constituting the discharge circuit, and the discharge from the data line is the gate of this N-channel transistor N3. It is controlled by the potential level of the signal input to. The power supply potential detection circuit shown in FIG.
The P-channel transistor P1 connected to D, N-channel transistors N4 and N5 connected in series with the P-channel transistor P1, and an N-channel transistor N6 whose gate is connected to VDD. The control pulse output from the P-channel transistor P1 is input to the gate of the P-channel transistor P1 to control the output of the power supply potential detection circuit selection circuit. The output of the power supply potential detection circuit is always connected to the gate of the N-channel transistor N3 of the data line discharge circuit.
【００１０】次に実施例に基づいて動作を説明する。半
導体記憶装置からの情報の読みだし時に外部より加わる
入力信号が変化したとき、１２の入力信号遷移検出回路
においてこれらの信号の変化を検知し、１３の制御パル
ス発生回路において制御パルス信号を作る。ここまでの
動作は従来の回路の動作と同一である。Next, the operation will be described based on an embodiment. When input signals applied from the outside when information is read from the semiconductor memory device change, the input signal transition detection circuit 12 detects the changes in these signals, and the control pulse generation circuit 13 generates a control pulse signal. The operation up to this point is the same as the operation of the conventional circuit.
【００１１】前記１３より出力される制御パルスによ
り、１５の電源電圧検出回路のＰチャネルトランジスタ
Ｐ１は読み出し時、一定期間ＯＮされ、電源電位検出回
路からの出力信号は４のデ−タ線放電回路のＮチャネル
トランジスタのゲ−トに入力される。図３に示すように
１５の電源電位検出回路からの信号は電源電位がＮ４，
Ｎ５のＶｔｈの和によって決まる値以下では出力され
ず、それ以上であればの電源電位に追随して変化するの
で、電源電圧が低い状態では、４のデ−タ線放電回路を
非活性化させて動作を安定させる。また、電源電圧の上
昇に伴いデ−タ線放電回路は徐々に活性化され、高電源
電圧時には、完全に活性化される。この様に電源電圧の
変化に応じてデ−タ線放電回路の動作を制御することに
よりデ−タ線電位を最適化し、広い電源電圧範囲での安
定した高速動作を可能とする。The P-channel transistor P1 of the power supply voltage detection circuit 15 is turned on for a certain period by the control pulse output from the power supply voltage detection circuit 15, and the output signal from the power supply potential detection circuit 4 is a data line discharge circuit. Is input to the gate of the N-channel transistor. As shown in FIG. 3, the signal from the power supply potential detection circuit 15 has a power supply potential N4,
It is not output below a value determined by the sum of Vth of N5, and if it is more than that, it changes following the power supply potential. Therefore, when the power supply voltage is low, the data line discharge circuit 4 is inactivated. Stabilize the operation. Further, the data line discharge circuit is gradually activated as the power supply voltage rises, and is fully activated at the high power supply voltage. In this way, by controlling the operation of the data line discharge circuit according to the change of the power supply voltage, the data line potential is optimized and stable high speed operation in a wide power supply voltage range is enabled.
【００１２】なお、この発明は上記した一実施例に限定
されるものではなく、様々な変形が可能であることはい
うまでもない。例えば上記実施例では、電源電位検知回
路の出力電位は一定の電源電位以上に追随させて変化す
るものとしたが、単純に電源電位に追随させるものでも
よく、電源電位の変化に追随してこれらの回路を制御す
るだけでなく、電源電位を検知してこれらの回路をＯ
Ｎ、ＯＦＦさせるだけのものでも良い。また、電源電位
検知回路からの出力信号を使ってデ−タ線の放電回路を
制御する場合について説明したが、他の信号伝搬線の放
電回路や、充電回路等、電源電位の変化によって特性に
大きな影響を受ける回路を制御してもよい。It is needless to say that the present invention is not limited to the above-mentioned embodiment and various modifications can be made. For example, in the above embodiment, the output potential of the power supply potential detection circuit is assumed to change by following a certain power supply potential or more, but it is also possible to simply follow the power supply potential and follow these changes in the power supply potential. Not only control these circuits, but also detect the power supply potential and turn these circuits on.
It may be one that is turned off or turned off. Also, although the case where the output circuit from the power supply potential detection circuit is used to control the discharge circuit of the data line has been described, the characteristics of the discharge circuit of other signal propagation lines, the charging circuit, etc. may change depending on the change of the power supply potential. Circuits that are significantly affected may be controlled.
【００１３】[0013]
【発明の効果】以上のように本発明によれば、デ−タ線
の充電および、放電を制御する電源電位検出回路の出力
信号の電位を、電源電圧の変動とともに可変させること
により、デ−タ線充放電回路の動作を電源電圧の変動に
よらず常に最適化する事ができるため、広範囲な電源電
圧で安定した高速動作可能な半導体記憶装置を提供する
ことができる。As described above, according to the present invention, the potential of the output signal of the power supply potential detecting circuit for controlling the charging and discharging of the data line is changed by changing the power supply voltage, thereby changing the data. Since the operation of the power line charging / discharging circuit can be always optimized regardless of the fluctuation of the power supply voltage, it is possible to provide a semiconductor memory device capable of stable high-speed operation in a wide range of power supply voltages.
【図１】本発明に係わる半導体記憶装置を示すブロック
図である。FIG. 1 is a block diagram showing a semiconductor memory device according to the present invention.
【図２】本発明の半導体記憶装置における電源電位検出
回路を示す回路図である。FIG. 2 is a circuit diagram showing a power supply potential detection circuit in the semiconductor memory device of the present invention.
【図３】本発明の半導体記憶装置における電源電位検出
回路からの出力電圧と電源電圧との関係図である。FIG. 3 is a relationship diagram between an output voltage from a power supply potential detection circuit and a power supply voltage in the semiconductor memory device of the present invention.
【図４】従来の半導体記憶装置を示すブロック図であ
る。FIG. 4 is a block diagram showing a conventional semiconductor memory device.
１ ・・・・・・メモリセル。 ２ ・・・・・・相補なデ−タ線。 ３ ・・・・・・ワ−ド線。 ４ ・・・・・・デ−タ線放電回路。 ５ ・・・・・・カラムゲ−ト。 ６ ・・・・・・デ−タ線充電回路。 ７ ・・・・・・センスアンプ。 ８ ・・・・・・出力回路。 ９ ・・・・・・デ−タ出力端子。 １０ ・・・・・・入力端子。 １１ ・・・・・・入力バッファ。 １２ ・・・・・・入力信号遷移検出回路。 １３ ・・・・・・制御パルス発生回路。 １４ ・・・・・・ワ−ド線駆動回路。 １６ ・・・・・・電源電位検出回路。 Ｐ１ ・・・・・・Ｐチャネルトランジスタ。 Ｎ１，Ｎ２，Ｎ３・Ｎチャネルトランジスタ。 Ｎ４，Ｎ５，Ｎ６ 1 ... Memory cell. 2 ... Complementary data lines. 3 ... Word line. 4 ... Data line discharge circuit. 5: Column gate. 6 --- Data line charging circuit. 7: Sense amplifier. 8 ... Output circuit. 9: Data output terminal. 10 --- Input terminal. 11 ... Input buffer. 12 ... Input signal transition detection circuit. 13 ... Control pulse generation circuit. 14 ... Word line drive circuit. 16 ··· Power source potential detection circuit. P1 ... P-channel transistor. N1, N2, N3, N-channel transistors. N4, N5, N6
Claims (1)
リセル群と、前記メモリセル群の中から選択されたメモ
リセルから情報を伝搬するためのメモリセルに接続され
たデ−タ線と、前記デ−タ線に付加されたデ−タ線充電
回路と、デ−タ線の過充電を放電するためのデ−タ線放
電回路とを具備した半導体記憶装置において、出力信号
の電位レベルが電源電圧により可変となる電源電位検出
回路を設け、前記電源電位検出回路からの出力信号が、
前記デ−タ線放電回路およびデ−タ線充電回路の少なく
とも一方を制御して成ることを特徴とする半導体記憶装
置。1. A memory cell group of memory cells for storing data, and a data line connected to the memory cell for propagating information from a memory cell selected from the memory cell group. And a data line charging circuit added to the data line, and a data line discharging circuit for discharging the overcharge of the data line, in a semiconductor memory device, the potential of an output signal A power supply potential detection circuit whose level is variable depending on the power supply voltage is provided, and an output signal from the power supply potential detection circuit is
A semiconductor memory device comprising at least one of the data line discharging circuit and the data line charging circuit controlled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5174037A JPH0729379A (en) | 1993-07-14 | 1993-07-14 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5174037A JPH0729379A (en) | 1993-07-14 | 1993-07-14 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0729379A true JPH0729379A (en) | 1995-01-31 |
Family
ID=15971528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5174037A Pending JPH0729379A (en) | 1993-07-14 | 1993-07-14 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0729379A (en) |
-
1993
- 1993-07-14 JP JP5174037A patent/JPH0729379A/en active Pending
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