JPH0729514Y2 - Electronic timepiece circuit board and electronic timepiece - Google Patents

Electronic timepiece circuit board and electronic timepiece

Info

Publication number
JPH0729514Y2
JPH0729514Y2 JP1989129771U JP12977189U JPH0729514Y2 JP H0729514 Y2 JPH0729514 Y2 JP H0729514Y2 JP 1989129771 U JP1989129771 U JP 1989129771U JP 12977189 U JP12977189 U JP 12977189U JP H0729514 Y2 JPH0729514 Y2 JP H0729514Y2
Authority
JP
Japan
Prior art keywords
circuit board
electronic timepiece
crystal unit
change
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1989129771U
Other languages
Japanese (ja)
Other versions
JPH0368099U (en
Inventor
達雄 守屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1989129771U priority Critical patent/JPH0729514Y2/en
Publication of JPH0368099U publication Critical patent/JPH0368099U/ja
Application granted granted Critical
Publication of JPH0729514Y2 publication Critical patent/JPH0729514Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【考案の詳細な説明】 [産業上の利用分野] 本考案は、電子時計用回路基板の水晶振動子用配線パタ
ーンのレイアウトに関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a layout of a wiring pattern for a crystal unit of a circuit board for an electronic timepiece.

[従来の技術] 従来の電子時計用回路基板に於いては、第5図に一例を
示したように、ICチップ1と水晶振動子2を接続するた
めの2本の配線パターンは、お互いがほぼ平行に隣接し
て配置されており、両パターンの間には空隙部はなかっ
た。
[Prior Art] In a conventional electronic timepiece circuit board, two wiring patterns for connecting the IC chip 1 and the crystal unit 2 are connected to each other as shown in FIG. They were arranged almost parallel to each other and there was no space between both patterns.

[考案が解決しようとする課題] しかし前述の回路基板に於いては、水晶振動子用の配線
パターンが隣接しているため、回路基板に配線パターン
を形成する際に銅箔を接着するための接着剤や、回路基
板へのICチップの固定力を高めるためのモールド剤が誘
電体となり、両配線パターンの間に比較的大きな浮遊容
量が形成されてしまい、湿度変化に伴う浮遊容量値の変
化に起因する歩度変化量が大きくなるという問題点を有
していた。このときの歩度変化量は配線パターンの長さ
によっても異なるが、温度20℃で湿度を40%から90%に
変化した場合0.05〜0.07sec/day程度となり、年差10秒
といった高精度時計にとっては致命的な値になってしま
う。
[Problems to be solved by the invention] However, in the above-mentioned circuit board, since the wiring patterns for the crystal unit are adjacent to each other, it is necessary to adhere the copper foil when forming the wiring pattern on the circuit board. The adhesive and the molding agent to enhance the fixing force of the IC chip to the circuit board become a dielectric, and a relatively large stray capacitance is formed between both wiring patterns. However, there is a problem that the rate of change in the rate due to is large. The rate of change at this time varies depending on the length of the wiring pattern, but when the humidity changes from 40% to 90% at a temperature of 20 ° C, it will be about 0.05 to 0.07 sec / day, which is high for a high-accuracy watch with an annual difference of 10 seconds. Becomes a fatal value.

本考案は上述の問題点を解決するためのもので、その目
的は、湿度変化に伴う浮遊容量値の変化に起因する歩度
変化を抑え、年差10秒といった高精度時計の精度保証率
を高めることにある。
The present invention is intended to solve the above-mentioned problems, and its purpose is to suppress the rate change caused by the change of the stray capacitance value due to the change of humidity and increase the accuracy guarantee rate of a high-precision watch such as 10 seconds per year. Especially.

[課題を解決するための手段] 本考案の電子時計用回路基板は、水晶振動子に導電接続
される2本の配線パターンのうち、一方を基板上に形成
し、他方を基板から離してオーバーハングさせたもので
ある。
[Means for Solving the Problem] The circuit board for an electronic timepiece according to the present invention has one of two wiring patterns conductively connected to a crystal unit, one of which is formed on the substrate and the other of which is separated from the substrate and overlaid. It is hung.

[作用] 本考案の上記構成によれば、水晶振動子用の2本の配線
パターンのうち一方を基板上に形成し、他方を基板から
離してオーバーハングさせたことにより、2本の配線パ
ターンの間に空気が存在することとなるために両者間の
浮遊容量を小さくすることができ、結果として湿度変化
に伴う浮遊容量値の変化に起因する歩度変化量を低減す
ることができる。また、一方を基板上に配線したことに
より水晶振動子と配線接続先との間の回路基板の剛性を
高めることができ、水晶振動子の取付位置の変位を低減
させることができる。しかも、この水晶振動子の位置変
位の低減とともに一方の配線パターンが回路基板上に形
成され固定されているので、回路基板の取付時における
配線パターン間の距離変化を低減することができ、配線
間距離の変化に伴う配線容量のばらつきをも低減するこ
とができる。
[Operation] According to the above configuration of the present invention, by forming one of the two wiring patterns for the crystal unit on the substrate and overhanging the other away from the substrate, the two wiring patterns are formed. Since air is present between the two, it is possible to reduce the stray capacitance between them, and as a result, it is possible to reduce the rate change amount due to the change in the stray capacitance value due to the humidity change. Further, by wiring one of them on the substrate, the rigidity of the circuit board between the crystal unit and the wiring connection destination can be increased, and the displacement of the mounting position of the crystal unit can be reduced. Moreover, since one wiring pattern is formed and fixed on the circuit board as well as the positional displacement of the crystal unit is reduced, it is possible to reduce the change in the distance between the wiring patterns when the circuit board is mounted. It is also possible to reduce variations in wiring capacitance due to changes in distance.

[実施例] 以下、実施例により本考案を詳細に説明する。本考案の
一実施例によるアナログウォッチ用回路ブロックの平面
図を第1図に断面図を第2図に示す。第1図及び第2図
に於いて1は1a部に内蔵している半導体温度センサーの
情報に基づいて水晶振動子2の二次温度特性を補償する
機能を持つアナログ電子時計用のCMOS-ICチップ、2は3
2768Hzで発振し二次温度特性を有する音叉形水晶振動
子、3はフレキシブルテープに接着された銅箔からエッ
チングにより形成した配線パターンを備えた回路基板で
あり、ICチップ1はフェイスダウンボンディングで、ま
た水晶振動子2ははんだ付けで回路基板3に装着されて
いる。またICチップ1の回路基板3への固定力を高める
ために、穴3dよりエポキシ系のモールド剤4が流し込ま
れている。また回路基板3の各配線パターン間には、銅
箔を接着するための接着剤や、ICチップ装着部よりはみ
出したモールド剤4によって、浮遊容量が形成されてい
る。
[Examples] Hereinafter, the present invention will be described in detail with reference to Examples. A plan view of a circuit block for an analog watch according to an embodiment of the present invention is shown in FIG. 1, and a sectional view thereof is shown in FIG. In FIGS. 1 and 2, reference numeral 1 is a CMOS-IC for an analog electronic timepiece having a function of compensating for the secondary temperature characteristic of the crystal unit 2 based on the information of the semiconductor temperature sensor incorporated in the 1a section. Chips, 2 is 3
A tuning fork crystal unit that oscillates at 2768Hz and has a secondary temperature characteristic, 3 is a circuit board having a wiring pattern formed by etching a copper foil adhered to a flexible tape, and IC chip 1 is face-down bonding. The crystal unit 2 is mounted on the circuit board 3 by soldering. Further, in order to increase the fixing force of the IC chip 1 to the circuit board 3, an epoxy type molding compound 4 is poured from the hole 3d. Floating capacitance is formed between the wiring patterns of the circuit board 3 by an adhesive for adhering a copper foil or a molding agent 4 protruding from the IC chip mounting portion.

第1図に示したように、本実施例の回路基板3は、水晶
振動子用の2本の配線パターン3a及び3bのうち、3aをほ
ぼ回路基板3の外形形状に沿わせてオーバーハングさせ
ている。このため、両パターン間に接着剤やモールド剤
により形成される浮遊容量値が小さくなり、湿度変化に
伴う浮遊容量値の変化に起因する歩度変化が小さくな
る。
As shown in FIG. 1, in the circuit board 3 of the present embodiment, of the two wiring patterns 3a and 3b for the crystal unit, 3a is made to overhang substantially along the outer shape of the circuit board 3. ing. Therefore, the stray capacitance value formed by the adhesive or the molding agent between both patterns becomes small, and the rate change due to the change in the stray capacitance value due to the humidity change becomes small.

第3図に、第1図の回路ブロックAと第5図の回路ブロ
ックBの20℃中に於ける歩度の湿度特性を示す。
FIG. 3 shows the humidity characteristics of the rate of the circuit block A of FIG. 1 and the circuit block B of FIG. 5 at 20 ° C.

第3図から明らかなように、回路基板3の水晶振動子用
の2本の配線パターンのうち3aを回路基板3の外形形状
に沿わせてオーバーハングさせることにより、湿度変化
により生じる歩度変化を1/2以下にすることができる。
As is apparent from FIG. 3, by overhanging 3a of the two wiring patterns for the crystal unit of the circuit board 3 along the outer shape of the circuit board 3, the rate change caused by the humidity change is changed. It can be less than 1/2.

このようにして本実施例では年差10秒といった高精度時
計の精度保証率を高めることができる。
In this way, in this embodiment, the accuracy guarantee rate of the high-accuracy timepiece, such as 10 seconds per year, can be increased.

ここで、配線パターン3a,3bを共に回路基板3から離し
てオーバーハングさせた場合に較べると、歩度変化量は
同様に低減させることができる上に、第1図に示すよう
に配線パターン3bを回路基板3上に形成したことによ
り、ICチップ1と水晶振動子2との間の回路基板3の剛
性を高めることができるので、水晶振動子の取付位置の
変化(ふらつき)を低減させることができる。
Here, as compared with the case where both the wiring patterns 3a and 3b are separated from the circuit board 3 and overhanged, the rate change amount can be similarly reduced, and as shown in FIG. Since the circuit board 3 is formed on the circuit board 3, the rigidity of the circuit board 3 between the IC chip 1 and the crystal resonator 2 can be increased, so that the change (fluctuation) in the mounting position of the crystal resonator can be reduced. it can.

また、水晶振動子の取付位置の変化が低減されるととも
に配線パターン3bが回路基板3上に形成され固定されて
いることから、回路基板の取付後における配線パターン
3aと3bの間の配線容量のばらつきを低減することもでき
る。
Further, since the change in the mounting position of the crystal unit is reduced and the wiring pattern 3b is formed and fixed on the circuit board 3, the wiring pattern after the circuit board is mounted is fixed.
It is also possible to reduce variations in wiring capacitance between 3a and 3b.

さらに、本実施例によれば水晶振動子用の2本の配線パ
ターンが多少長くなっても回路基板の剛性を確保できる
とともに湿度変化に伴う歩度変化を少なくすることがで
きるため、水晶振動子とICチップの平面レイアウト上の
自由度が格段に向上し、小型の高精度電子時計が製造可
能となる。
Further, according to the present embodiment, the rigidity of the circuit board can be ensured and the rate change due to the humidity change can be reduced even if the two wiring patterns for the crystal oscillator are somewhat lengthened. The degree of freedom in the planar layout of the IC chip is significantly improved, and it becomes possible to manufacture a compact high-precision electronic timepiece.

第4図に本考案の他の実施例を示す。第4図に於いては
回路基板3の内に長穴3cを設けて配線パターン3aをオー
バーハングさせているが、この場合にも第1図の実施例
と同様の効果が得られる。
FIG. 4 shows another embodiment of the present invention. In FIG. 4, elongated holes 3c are provided in the circuit board 3 to overhang the wiring pattern 3a, but in this case also, the same effect as that of the embodiment of FIG. 1 can be obtained.

この場合、回路基板3には長孔3cが形成されているだけ
であるので、ICチップ1と水晶振動子2との間の回路基
板3の剛性を第1図に示す実施例よりもさらに高めるこ
とができる。
In this case, since only the long hole 3c is formed in the circuit board 3, the rigidity of the circuit board 3 between the IC chip 1 and the crystal unit 2 is further increased as compared with the embodiment shown in FIG. be able to.

[考案の効果] 以上述べたように本考案の電子時計用回路基板は、水晶
振動子用の2本の配線パターンのうち一方を基板上に形
成し、他方を基板から離してオーバーハングさせたこと
により、両配線パターン間の浮遊容量を小さくすること
ができるので、結果として湿度変化に伴う浮遊容量値の
変化に起因する歩度変化量を低減することができる。
[Effects of the Invention] As described above, in the electronic timepiece circuit board of the present invention, one of the two wiring patterns for the crystal unit is formed on the board, and the other is separated from the board and overhung. As a result, the stray capacitance between the two wiring patterns can be reduced, and as a result, the rate change amount due to the change in the stray capacitance value due to the humidity change can be reduced.

また、一方を基板上に配線したことにより水晶振動子と
配線接続先との間の回路基板の剛性を高めることがで
き、水晶振動子の取付位置の変位を低減させることがで
きる。
Further, by wiring one of them on the substrate, the rigidity of the circuit board between the crystal unit and the wiring connection destination can be increased, and the displacement of the mounting position of the crystal unit can be reduced.

しかも、この水晶振動子の位置変位の低減とともに一方
の配線パターンが回路基板上に形成され固定されている
ことから、回路基板の取付時における配線パターン間の
距離変化を低減することができ、配線間距離の変化に伴
う配線容量のばらつきをも低減することができる。
Moreover, since the positional displacement of the crystal unit is reduced and one wiring pattern is formed and fixed on the circuit board, it is possible to reduce the distance change between the wiring patterns when the circuit board is mounted. It is also possible to reduce variations in wiring capacitance due to changes in the distance.

さらに、本考案によれば水晶振動子用の2本の配線パタ
ーンが多少長くなっても回路基板の剛性を確保できると
ともに湿度変化に伴う歩度変化を少なくすることができ
るため、水晶振動子及びその配線パターン等の平面レイ
アウト上の自由度が格段に向上し、小型の高精度電子時
計が製造可能となる。
Further, according to the present invention, the rigidity of the circuit board can be secured and the rate change due to the humidity change can be reduced even if the two wiring patterns for the crystal unit are slightly lengthened. The degree of freedom in the plane layout of the wiring pattern and the like is remarkably improved, and a compact high-precision electronic timepiece can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案の電子時計用回路ブロックの実施例を示
す平面図。 第2図は第1図の断面図。 第3図は第1図の回路ブロックAと第5図の回路ブロッ
クBの歩度の湿度特性を示すグラフ。 第4図は本考案の電子時計用回路ブロックの他の実施例
を示す平面図。 第5図は従来の電子時計用回路ブロックの実施例を示す
平面図。 1……ICチップ 2……水晶振動子 3……フレキシブル回路基板 3a,3b……水晶振動子用配線パターン 3c……回路基板3に設けられた穴 4……モールド剤
FIG. 1 is a plan view showing an embodiment of a circuit block for an electronic timepiece according to the present invention. FIG. 2 is a sectional view of FIG. FIG. 3 is a graph showing rate humidity characteristics of the circuit block A of FIG. 1 and the circuit block B of FIG. FIG. 4 is a plan view showing another embodiment of the electronic watch circuit block of the present invention. FIG. 5 is a plan view showing an embodiment of a conventional electronic timepiece circuit block. 1 ... IC chip 2 ... Crystal resonator 3 ... Flexible circuit board 3a, 3b ... Circuit resonator wiring pattern 3c ... Hole provided in circuit board 3 ... Molding agent

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】水晶振動子に導電接続される2本の配線パ
ターンのうち、一方を基板上に形成し、他方を基板から
離してオーバーハングさせたことを特徴とする電子時計
用回路基板。
1. A circuit board for an electronic timepiece, wherein one of two wiring patterns conductively connected to a crystal unit is formed on a substrate and the other is separated from the substrate and overhanged.
【請求項2】実用新案登録請求の範囲第1項に記載の電
子時計用回路基板を搭載したことを特徴とする電子時
計。
2. An electronic timepiece comprising the electronic timepiece circuit board according to claim 1 of the utility model registration.
JP1989129771U 1989-11-07 1989-11-07 Electronic timepiece circuit board and electronic timepiece Expired - Lifetime JPH0729514Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989129771U JPH0729514Y2 (en) 1989-11-07 1989-11-07 Electronic timepiece circuit board and electronic timepiece

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989129771U JPH0729514Y2 (en) 1989-11-07 1989-11-07 Electronic timepiece circuit board and electronic timepiece

Publications (2)

Publication Number Publication Date
JPH0368099U JPH0368099U (en) 1991-07-03
JPH0729514Y2 true JPH0729514Y2 (en) 1995-07-05

Family

ID=31677377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989129771U Expired - Lifetime JPH0729514Y2 (en) 1989-11-07 1989-11-07 Electronic timepiece circuit board and electronic timepiece

Country Status (1)

Country Link
JP (1) JPH0729514Y2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0743672Y2 (en) * 1987-03-05 1995-10-09 セイコーエプソン株式会社 Electronic clock

Also Published As

Publication number Publication date
JPH0368099U (en) 1991-07-03

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