JPH07295522A - Active matrix display device - Google Patents

Abstract

(57) [Summary] (Corrected) [Purpose] When driving the active matrix display device in a dot-sequential manner, eliminates obi-like defects at the lateral end of the screen. [Structure] A plurality of gate lines Y laid out in rows, a plurality of data lines X laid out in columns, and a plurality of pixels PXL provided at each intersection are included in the display area 1. The vertical scanning circuit 2 sequentially vertically scans each gate line X and selects one row of pixels PXL for each horizontal period. The horizontal scanning circuit 3 sequentially scans each data line Y within one horizontal period, samples the video signal Vsig, and writes the video signal to the pixels PXL for one selected row in a dot-sequential manner.
The data line Y is divided into actual data lines Y1 to YL and dummy data lines YD1 to YD4. The horizontal scanning circuit 3 horizontally scans the actual data lines at a plurality of overlapping sampling timings, and continues the horizontal scanning of dummy data lines at the same timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device. More specifically, the present invention relates to a technology for removing obi-like defects that appear at the terminal portion in the horizontal direction of a screen of an active matrix display device that is driven in a dot sequential manner.

[0002]

2. Description of the Related Art A general structure of a conventional active matrix display device will be briefly described with reference to FIG. The active matrix display device has a plurality of gate lines X arranged in rows, a plurality of data lines Y arranged in columns, and a plurality of pixels PXL provided at respective intersections of both. The pixels PXL are composed of, for example, fine liquid crystal cells and are arranged in a matrix to form a display area. Individual pixel PXL
A thin film transistor Tr is formed in an integrated manner to drive the thin film transistor Tr. In addition, a vertical scanning circuit 101 is provided, and each gate line X is sequentially vertically scanned to select one row of pixels PXL for each horizontal period. Further, the horizontal scanning circuit 10
2, each data line Y is sequentially scanned within one horizontal period, the video signal Vsig is sampled, and the video signal Vsig is written in the pixel PXL for one selected row in a dot-sequential manner. Specifically, each data line Y is connected to the video line 103 via the horizontal switch HSW and receives the video signal Vsig supplied from the outside. The horizontal scanning circuit 102 sequentially outputs sampling pulses φ _H1 , φ _H2 , φ _H3 ,
, Φ _HN are output and each horizontal switch HSW is sequentially opened and closed to sample the video signal Vsig on each data line Y.

[0003]

FIG. 9 shows waveforms of sampling pulses sequentially output from the horizontal scanning circuit 102 shown in FIG. The sampling pulse width τ _H is determined corresponding to the sampling time assigned to each data line Y. As the definition of the active matrix display device becomes higher, the number of pixels is remarkably increased and the writing time per dot is remarkably shortened.
Further, in the HDTV-compatible active matrix display device, since the line scanning speed is increased, the writing time per dot is similarly shortened. Correspondingly, the sampling pulse width τ _H becomes extremely narrow. For example, horizontal 470
In the NTSC-compatible half-line type active matrix display device of pixels, the sampling pulse width is τ _H = 50
μs / 470/3 (RGB) = about 320 nsec.
When this becomes 800 pixels horizontally, τ _H = 188 nsec. Furthermore, if the full line configuration is used for double speed driving, τ _H = 9
The sampling time is very short, 4 nsec. If the sampling pulse width is reduced in this way, it becomes unreasonable in terms of waveform shaping, the configuration of the horizontal scanning circuit becomes complicated, and the design margin becomes narrow. Further, since a sufficient time for writing the video signal cannot be obtained, a load is imposed on the liquid crystal panel side, and various restrictions are imposed on the design.

In order to deal with the shortening of the sampling pulse width τ _H , for example, the method disclosed in Japanese Patent Publication No. 1-37911 has been proposed. As shown in FIG. 10, the pulse widths of the sampling pulses φ _H1 , φ _H2 , φ _H3 , φ _H4 , ... _Are made long and output sequentially while overlapping. That is, it is a method of shifting while selecting a plurality of data lines at the same time. For example, in FIG.
When four data lines are simultaneously selected as shown in (3), the sampling pulse width is τ _H = 4 × 188 nsec = 750 nsec for 800 horizontal pixels. This method can reduce the design burden on the drive side of the horizontal scanning circuit etc. and the liquid crystal panel side.

However, in the method of sequentially shifting a plurality of data lines while simultaneously selecting them, there is a problem that the obi-like defect 105 is generated at the horizontal scanning direction end portion of the display area 104 constituting the screen as shown in FIG. is there. For example, in the normally white mode, this lob-like defect 10
5 appears darker than the normal part. The obi-like defect 105 is caused by the fact that the overlapping of the sampling pulse is canceled on the terminal side of the horizontal scanning and the driving condition is different from that of other normal regions.

[0006]

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, it is an object of the present invention to eliminate the obi-like defects appearing at the horizontal scanning direction terminal end in dot-sequential driving of an active matrix display device. The following measures have been taken in order to achieve this object. That is, the active matrix display device according to the present invention has, as a basic configuration, a plurality of gate lines wired in rows, a plurality of data lines wired in columns, and a display area provided at each intersection of both. And a plurality of pixels for Further, a vertical scanning circuit and a horizontal scanning circuit are provided as a peripheral portion. The vertical scanning circuit sequentially vertically scans each gate line to select pixels for one row every horizontal period. On the other hand, the horizontal scanning circuit sequentially scans each data line within one horizontal period, samples the video signal, and writes the video signal in a dot-sequential manner to the pixels for one selected row. As a feature of the present invention, the data line is divided into an actual data line wired in the display area and a dummy data line wired outside the display area and intersecting the terminal side of the gate line. The horizontal scanning circuit performs horizontal scanning at a sampling timing that overlaps a plurality of actual data lines, and continuously adds horizontal scanning at a sampling timing that also overlaps dummy data lines.
In this case, the dummy data lines are wired by the number of lines that are simultaneously horizontally scanned at at least overlapping sampling timings. Dummy pixels are also assigned to this dummy data line. Alternatively, the pixels may be excluded from the dummy data line.

[0007]

According to the present invention, a dummy data line is added to the outside of the display area adjacent to the end of the actual data line wired in the display area. The horizontal scanning circuit continuously performs horizontal scanning over the actual data line and the dummy data line. Therefore, even when reaching the end side of the display area, overlapping sampling timings for a plurality of actual data lines are maintained as they are, and normal image display is performed, so that no obi defects occur. Further, when the horizontal scanning reaches the dummy data line, the overlapping sampling timing is released, and the display state changes in some cases. However, since the dummy data line is arranged outside the display area, it does not appear on the screen.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of an active matrix display device according to the present invention. As shown in the figure, the active matrix display device includes a plurality of gate lines X arranged in rows and a plurality of data lines Y arranged in columns. Pixels PXL are arranged in a matrix at the intersections of the two to form the display area 1. The pixel PXL is composed of, for example, a liquid crystal cell having a fine structure. In the present embodiment, a thin film transistor Tr is provided in order to drive the pixel PXL composed of a liquid crystal cell. The source electrode of each thin film transistor Tr is connected to the corresponding data line Y, the gate electrode is connected to the corresponding gate line X, and the drain electrode is corresponding to the corresponding pixel PXL.
Connected to.

A vertical scanning circuit 2 and a horizontal scanning circuit 3 are provided around the display area 1 described above. The vertical scanning circuit 2 sequentially vertically scans each gate line Y to make the above-mentioned thin film transistor Tr conductive, and selects one row of pixels PXL for each horizontal period. On the other hand, the horizontal scanning circuit 3 sequentially scans each data line Y in one horizontal period, samples the video signal Vsig, and writes the video signal Vsig in the pixels PXL for one selected row in a dot-sequential manner. Specifically, each data line Y is connected to the video line 4 via the horizontal switch HSW and supplied with the video signal Vsig.
The horizontal scanning circuit 3 sequentially outputs the sampling pulse φ and its inversion pulse to open / close the individual horizontal switches HSW to sample the video signal Vsig described above. Video signal V sampled on each data line Y
sig is written in the pixels PXL for one row through the thin film transistor Tr in the ON state. After this, the thin film transistor Tr is turned off and the written video signal Vs
ig is held until the next frame.

As a feature of the present invention, the data lines are real data lines Y1, Y2, ..., Arranged in the display area 1.
YL and dummy data line Y arranged outside the display area 1
It is divided into D1, YD2, YD3 and YD4. These dummy data lines intersect the end side of the gate line X. In this embodiment, the pixel PXL and the thin film transistor Tr are excluded from the dummy data line.
However, the present invention is not limited to this,
In order to make the driving conditions completely the same, dummy pixels and thin film transistors may be assigned to the dummy data lines. On the other hand, the horizontal scanning circuit 3 scans not only actual data lines but also dummy data lines. That is, the horizontal scanning circuit 3 performs horizontal scanning at a plurality of (four in this example) overlapping sampling timings with respect to the actual data lines Y1, Y2, ..., YL. Furthermore, the dummy data lines YD1, YD2, YD3, Y
Horizontal scanning is also added to D4 at the same overlapping sampling timing. In this case, the dummy data lines are arranged at least by the number of lines that are simultaneously horizontally scanned at the overlapping sampling timings. That is, in this embodiment, at least four dummy data lines are provided. More specifically, the horizontal scanning circuit 3 uses the actual data lines Y1, Y2, ...
Sampling pulses φ ₁ , φ ₂ , ..., φ _L and its inversion pulse are sequentially output to the horizontal switch HSW connected to YL. Further continuously, the dummy data line YD
1, YD2, YD3, YD4 to the horizontal switch HSW, sampling pulses φ _D1 , φ _D2 ,
φ _D3 , φ _D4 and its inversion pulse are applied sequentially. In this example, since a transmission gate made of CMOS is used as the horizontal switch HSW, an inversion pulse is also applied.

Next, the operation of the active matrix display device shown in FIG. 1 will be described in detail with reference to FIG. As shown in the timing chart of the figure, the sampling pulse is output at the sampling timing which overlaps four lines with respect to the actual data line, and the horizontal scanning (actual scanning) is performed on the display area 1. For ease of understanding, only five final sampling pulses φ _L are shown in the timing chart. In the present embodiment, the dummy sampling pulses φ _D1 , φ _D2 , φ _D3 , and φ _D4 are sequentially output at timings after the sampling pulse φ _L has risen and overlapping with the dummy data line, and the dummy sampling pulses φ _D1 , φ _D3 , and φ _D4 are output. Horizontal scanning (dummy scanning) is performed. When the sampling pulses φ are successively output at such overlapping timings, the potential fluctuation of the gate line Y occurs due to the capacitive coupling generated at the intersection of the gate line Y and the data line X. Since the capacitive coupling is continued in response to the rising of each sampling pulse φ, the potential of the gate line X continues to fluctuate until the final dummy sampling pulse φ _D4 rises. After the last dummy sampling pulse φ _D4 rises, the capacitive coupling is no longer received, so the potential of the gate line Y is attenuated toward the ground level.

On the other hand, when each sampling pulse φ falls, the horizontal switch HSW shifts from the on state to the off state. When the HSW is closed, the potential fluctuation of the gate line will conversely jump into each signal line Y due to the aforementioned capacitive coupling. As a result, when the potential fluctuation of the gate line is stopped and then the attenuation is started, this affects the potential of the signal line X through the capacitive coupling, and the attenuation also occurs. As can be understood from the timing chart of FIG. 2, the potentials _VL-4 , _VL-3 , _VL-2 of the actual data lines,
Regarding V _L-1 and V _L , since the corresponding HSWs are already in the off state, after the potential fluctuation of the gate line is subsided, the attenuation starts all at once and finally a voltage drop of ΔV0 occurs.
Therefore, the voltage drop ΔV for all actual data lines
Since 0 is the same, unevenness in the display density does not occur. In contrast,
For example, for the first dummy data line YD1, the corresponding dummy sampling pulse φ _D1 falls with a delay of one clock after the fluctuation of the potential of the gate line has subsided. Since the potential V _D1 of the dummy data line YD1 starts to be attenuated in synchronization with this falling time point, the final voltage drop ΔV1 becomes smaller than ΔV0. Similarly, the potential V _D2 of the second dummy data line YD2 is further delayed by one clock and starts to be attenuated, so that the final voltage drop ΔV2 is further reduced. In this way, the voltage drop of the dummy data line is different from each other, and the display density varies. However, since the dummy data line is located outside the display area 1, it does not affect the actual image. As described above, the horizontal scanning circuit 3 carries out horizontal scanning for an additional four pixels beyond the effective display area 1. Further, four dummy data lines are provided in the same arrangement as the effective display area 1 including the HSW. By providing four dummy data lines, the potential fluctuation of the gate line continues in the same manner for four pixels even after passing through the effective display area 1. Therefore, the fluctuation of the signal line included in the display area 1 does not change abruptly only at the end portion. In this embodiment, four signal lines were horizontally scanned at the same time.
When simultaneously scanning two signal lines, the number of dummy data lines may be N or more. Pixels and driving transistors are not necessarily required in the dummy data line, and even if they are omitted, the effect of reducing obi defects is sufficient.

Finally, the mechanism of generation of the lobed defects will be described for reference with reference to FIGS. FIG. 3 shows a configuration of a general active matrix display device, which is similar to the circuit shown in FIG. 8 and corresponding parts are given corresponding reference numerals to facilitate understanding. In particular, reference numerals used in the following description will be mentioned here.
The potential of the video line 103 to which the video signal Vsig is supplied is represented by VA. Also, the potential of each data line Y is represented by VB. Further, the potential of each gate line X is represented by VC. A parasitic capacitance Ch is present at the intersection of each gate line X and data line Y, which causes the above-mentioned capacitance coupling. Each gate line X also contains a resistance component.

FIG. 4 shows the potentials VA and V of each line described above.
B and VC represent changes with time. As shown in the figure, the horizontal scanning circuit 102 outputs a sampling pulse φ _H and the video signal Vsig is sampled and held on the corresponding data line. The potential VB of the data line which is sampled and held and the potential VC of the gate line are flat at first glance, but when the sampling timing is enlarged, the fluctuation appears due to the capacitive coupling described above. That is, a differential-wave-shaped signal is constantly superimposed on the gate potential VC. Further, the data potential VB is attenuated (decay) from the level once sampled and held.

FIG. 5 shows an equivalent circuit of this portion. Each data line intersects all gate lines after the corresponding HSW. Therefore, the equivalent circuit includes the equivalent capacitance C _H corresponding to the total of the parasitic capacitance Ch shown in FIG.
In the equivalent circuit, C _G is the total capacitance of the gate lines themselves, and R _G is the equivalent gate line resistance. In such a circuit, the data potential VB rises and the gate potential VC also rises accordingly. Also, HSW
When is closed, the attenuation of the gate potential VC is directly reflected on the data potential VB as it is.

The timing chart of FIG. 6 shows what happens in the case of simultaneous scanning of four lines, for example. Here, the final sampling pulse φ
It shows from _{H, LAST} to 5 sampling pulses. The charging / discharging of the signal line is repeated until the final sampling pulse φ _{H, LAST} . Therefore, the gate potential VC
Keeps receiving capacitive coupling at each φ _H rise. When the rise of φ _{H, LAST} ends, the gate potential VC is no longer subjected to capacitive coupling, and therefore attenuates toward the ground level. On the other hand, each signal line has a corresponding HSW
After closing, the fluctuation of the gate potential jumps in via the capacitance component C _H shown in the equivalent circuit of FIG. At the timing before φ _{H, LAST-4} , the level of the signal line is VB _LAST-4.
As indicated by, changes by ΔV0. However, φ _{H, LAST-3} ,
As φ _{H, LST-2} , φ _{H, LST-1} , ..., The level at which the attenuation of the gate potential VC jumps into the signal line decreases.
That is, the potentials of the last four signal lines VB _LAST-3 , ...,
The voltage drop ΔV1, ..., ΔV4 of VB _LAST decreases.

This ΔV is schematically shown in FIG. Last four
With respect to the signal line of this line, ΔV is reduced as compared with all the signal lines before that. The degree of decrease increases as it approaches the final signal line. For this reason, obi defects occur in the last four lines.

[0018]

As described above, according to the present invention, the dummy data lines wired outside the display area are provided in addition to the actual data lines wired inside the display area. Obi-like defects are eliminated by performing horizontal scanning at the sampling timing that overlaps with the actual data line and then adding horizontal scanning at the sampling timing that also overlaps with the dummy data line. As a result, the effect of improving the image quality can be obtained. In particular, the present invention is extremely effective when dot-sequential driving is performed in a large-sized active matrix display device in which the number of pixels is extremely increased.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an active matrix display device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the active matrix display device shown in FIG.

FIG. 3 is a reference circuit diagram used to explain an obi defect.

FIG. 4 is also a reference timing chart.

FIG. 5 is a reference equivalent circuit diagram of the same.

FIG. 6 is also a reference timing chart.

FIG. 7 is also a reference graph.

FIG. 8 is a circuit diagram showing a general configuration of a conventional active matrix display device.

9 is a timing chart for explaining the operation of the active matrix display device shown in FIG.

FIG. 10 is a timing chart for explaining the operation of the same.

FIG. 11 is a schematic view showing a lobed defect appearing in a display area.

[Explanation of symbols]

 1 display area 2 vertical scanning circuit 3 horizontal scanning circuit 4 video line X signal line Y data line HSW horizontal switch PXL pixel Tr thin film transistor

Claims (4)

[Claims] 1. A plurality of gate lines arranged in rows,
A plurality of data lines laid out in columns, a plurality of pixels that are provided at each intersection of the two to form a display area, and each gate line are sequentially vertically scanned to vertically select pixels for one row every horizontal period. An active matrix display device comprising: a scanning circuit; and a horizontal scanning circuit which sequentially scans each data line in one horizontal period, samples a video signal, and writes the video signal in a dot-sequential manner to pixels in a selected row. The data line is divided into an actual data line wired in the display area and a dummy data line wired outside the display area and intersecting the end side of the gate line. Horizontal scanning is performed at a sampling timing that overlaps a plurality of data lines, and the dummy data lines are continuously overlapped. An active matrix display device, characterized in that to add a horizontal scanning at the sampling timing. 2. The active matrix display device according to claim 1, wherein the dummy data lines are wired by the number of lines which are simultaneously horizontally scanned at at least overlapping sampling timings. 3. The active matrix display device according to claim 1, wherein dummy pixels are also assigned to the dummy data lines. 4. The active matrix display device according to claim 1, wherein pixels are excluded from the dummy data line.