JPH07296032A - Logical model verification device - Google Patents

Abstract

PURPOSE:To provide a device for automatically verifying the propriety of the function description of a logic model. CONSTITUTION:The logic model verification device is provided with a single library extraction means 18 generating a single library 11 from a library to be tested, an HDL function description group extraction means counting the number of the input/output pins of the logic model in the single library 11 and extracting an HDL function description group from an HDL function description group template 10, a logic synthetic tool 20 which logically synthesizes the HDL function description group by using the single library 11 and generating a net list 14, a first simulation means simulating 21 the net list 14 and obtaining a first result, a second simulation means simulating 22 HDL function description and obtaining a second result and a result comparison means 23 comparing the first and second results and obtaining a verified result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device used in the field of designing a semiconductor integrated circuit such as an ASIC. In particular, in a library that collects logical models used in a logic synthesis tool that automatically generates logic circuits such as logic diagrams and netlists from high-level design data such as hardware description languages, logic expressions, truth tables, etc. The present invention relates to a device for verifying the functional description of.

[0002]

2. Description of the Related Art In recent years, in the design of semiconductor integrated circuits such as LSI, a method of generating a circuit by logic synthesis from an HDL (hardware description language) description has been in the limelight. FIG. 8 is a diagram showing an example of design data according to the HDL description. In FIG. 8, the first line indicates that the designed module name is a counter (COUNTER_4). In the 2nd to 6th lines, 4 is assigned to SIZE as a parameter, and the input is IN and CLR.
The output has a value of 0 to 3 at OUT and indicates that the value repeats.

After the 7th line, this counter is I
The operation is started by the rising edge of the pulse signal input to N or CLR. When the signal is input to CLR, the output OUT becomes 0, and when it is input to IN, 1 is added to the output. It is shown that. A logic circuit is automatically synthesized by the logic synthesis tool from the design data described above.

FIG. 9 is a diagram showing a logic circuit synthesized by a logic synthesis tool based on the design data of FIG. In FIG. 9, NAND and NO indicated by logical symbols
R, NOT, FF, etc. are logic models used as design components in the synthesis of logic circuits. The library is a collection of these logical models. As described above, the logic circuit design of the module in the semiconductor integrated circuit is performed by describing the function of the module as design data.
A logic circuit can be synthesized from the functional description using a logic synthesis tool.

[0005]

By the way, as a user, it is possible to synthesize a logic circuit by a logic synthesis tool provided by a CAD development maker arbitrarily selected by using a library provided by a semiconductor maker arbitrarily selected. Is desirable. For that purpose, the number of libraries that is obtained by multiplying the number of semiconductor manufacturers by the number of logic synthesis tools is required, but not all of them are prepared by the manufacturer.

Therefore, the user must create a library as needed, but there is no method for automatically verifying the function of the logical model included in the created library, and the logical model designer can visually check the function. At present, the verification of the logical model is performed for each logical model. Therefore, the verification was inefficient and the reliability was low. Therefore, an object of the present invention is to provide an apparatus for automatically verifying whether or not the functional description of a logical model is correct.

[0007]

The above object can be achieved by the present invention described below. That is, a single library extracting unit that extracts a logic model for individual logic synthesis to be tested from the tested library for logic synthesis to generate a single library, and the number of input / output pins of the logic model of the single library is counted, The HDL function description group extracting means for extracting the HDL function description group corresponding to the number of pins from the HDL function description group template and the independent library
A logic synthesis tool for performing a logic synthesis of the L function description group to generate a netlist, and a simulation test pattern corresponding to the netlist and a simulation model using a logic model for logic simulation are performed to obtain a first result. First simulation means, second simulation means for obtaining a second result by performing a simulation on the logic-synthesized HDL functional description using the simulation test pattern, the first result, and the second result. A logical model verification device comprising: result comparison means for comparing results to obtain a verification result; and output means for outputting the verification result.

[0008]

According to the logical model verification apparatus of the present invention, the individual library extracting means extracts the individual logical models for logical synthesis to be tested from the library under test for logical synthesis to generate the individual library, and the HDL function is provided. The description group extraction means counts the number of input / output pins of the logical model of the single library, extracts the HDL function description group corresponding to the number of pins from the HDL function description group template, and extracts the single library by the logic synthesis tool. Using the above, the HDL functional description group is logically synthesized to generate a netlist, and the first simulation means performs simulation on the netlist using a simulation test pattern corresponding to the netlist and a logical model for logical simulation. The first result is obtained and the second simulation The means performs a simulation on the logically synthesized HDL functional description using the simulation test pattern to obtain a second result. The result comparing means compares the first result and the second result. As a result, the verification result is obtained, and the output unit outputs the verification result. Then, by repeating the above processing steps for the logic modules other than the verified ones, the verification results of all the logic modules can be obtained.

[0009]

EXAMPLES The present invention will be described below with reference to preferred examples. FIG. 1 is a diagram showing a hardware configuration of a logical model verification device of the present invention. In FIG. 1, reference numeral 1 denotes an arithmetic processing unit, which is a main body of a computer such as an engineering workstation and a personal computer.
Reference numerals 2 and 3 are a keyboard and mouse which are input devices connected to the main body of the computer, 4 is a display device such as a CRT color display monitor, 5 is an FD device which is a floppy disk device, and 6 is a storage device such as a fixed magnetic disk device. , 7 is a printer, 8 is a LAN such as Ethernet
(Local area network).

In the hardware configuration of FIG. 1, the logical model verification apparatus of the present invention performs the processing shown in FIG. FIG. 2 is a flow chart showing a processing process by the logical model verification device of the present invention. In FIG. 2, 9 is a library under test for logic synthesis, 10 is an HDL function description group template, 11
Is a single library, 12 is an HDL functional description group, 13 is a logical model for simulation, 14 is a netlist,
15 is a HDL function description in which a single library is synthesized, 1
6 is a test pattern for logic simulation, and 17 is a verification result of a data file or the like.

Data 9 to 16 are data files stored in or stored in the storage device 6, and are read or written in the arithmetic processing unit 1 when the processing of the present invention is performed. Reference numeral 17 is data of a simulation result obtained after performing the processing, which is stored in the FD device 5 or the storage device 6 as a data file or is printed out. Further, in FIG. 2, 18 is a single library extraction means, 19 is an HDL function description group extraction means, 20 is a logic synthesis tool, 21 is a first simulation means, 22 is a second simulation means, and 23 is a result comparison means. Reference numeral 24 is an output means. These 18-2
Reference numeral 4 denotes software incorporated in the arithmetic processing unit 1 of FIG. 1, by which the processing in FIG. 2 is executed.

The logical model verification apparatus of the present invention will be described in detail below for each of the constituent means. §1. Individual Library Extracting Unit The individual library extracting unit 18 extracts the individual logic models for logic synthesis to be tested from the tested library 9 for logic synthesis to generate the individual library 11. When extracting, a logical model other than the already verified logical model is extracted. By doing so, by repeating the verification process described below, it is possible to perform the verification process for all the logical models included in the library under test.

FIG. 3 shows a library 9 to be tested for logic synthesis.
It is a figure which shows a part of contents as an example. In FIG. 3, the first line indicates that the name of the library is MODEL. The second to fourth lines indicate that the manufacturing process of the semiconductor integrated circuit is the process indicated by "1".
It is shown that the condition when the characteristic analysis is performed is that the ambient temperature is 26 ° C. and the driving voltage is 3.0 V. The fifth line is the cell name as the logical model name, which is NAND in this case. In FIG. 3, DFF (D-p flip-flop), INV (inverter), and LATCH (latch) are also described as cell names.

The logical model is described by HDL, and H
It is part data used when designing a module by DL. FIG. 4 shows an example of the independent library 11 (NAN generated from the tested library 9 for logic synthesis).
It is a figure which shows D). This example uses NAN as a logical model.
The D logic is described in HDL. In the first to seventh lines in FIG. 3, the cell name as a logical model name is NAND, the cell area is 300, and both I1 and I2 are inputs and have a fanout of 1.1 and a capacity of 0.03. It is shown that. Further, from the 13th line onward, it is described that O1 is an output, fanout is 10, and the function is "(I1 & I2) '", that is, the NOT of the AND logic of I1 and I2 and the NAND logic.

Further, FIG. 5 shows an example of the independent library 11 generated from the tested library 9 for logic synthesis (D
It is a figure which shows FF). In FIG. 5, the cell name is DFF
(D-flip-flop), the cell area is 1500,
CLK, D, and CLR all indicate that they are inputs and have a capacitance of 0.0. Also, from the 15th line onward, it is described that the function description and Q are output. The present invention verifies whether or not the logical name registered in the library corresponding to the above logical model and the functional description of the logic in the above described logical model match and are correct.

§2. HDL function description group extraction means The HDL function description group extraction means 19 counts the number of input / output pins of the logical model of the independent library 11,
From the L function description group template 10, the HDL function description group 12 having the corresponding number of pins is extracted. FIG. 6 is a diagram showing an example of the HDL function description group 12 with the number of pins of 3 generated by the HDL function description group extraction means 19. FIG. 7 is a diagram showing an example of the HDL function description group 12 having 4 pins generated by the HDL function description group extraction means 19. The HDL function description group template 10 is a set of HDL function description groups 12 as shown in FIGS. 6 and 7.

In FIG. 4, the pin of the cell NAND is p
Since it is described as in (I1), pin (I2), and pin (O1), the number of pins is three. Therefore, in the HDL function description group template 10, the module name (m
3names are searched and HD shown in FIG.
The L function description group 12 is extracted. In FIG. 6, in1
_1, in2_1, out_1, in1_2, in2_
2, out_2, in_3, out_3, and clk_3 are input / output pins, in indicates an input and out indicates an output. Also, the numerical value immediately after in or out is given for distinguishing when there are a plurality of input / output pins in one HDL function description, and the numerical value immediately after _ is a plurality of H
In the HDL function description group consisting of DL function descriptions, HD
It is added to specify the L function description. Figure 6
In the above example, the HDL functional description is 2 NAND (2-input NAND logic), 2 NOR (2-input NOR logic), DFlip-Flop (D flip-flop).
Function is described.

Similarly, in FIG. 5, the pins of the cell DFF are pin (CLK), pin (D), pin (RES).
ET) and pin (Q), the number of pins is four.
Therefore, in the HDL function description group template 10,
The module name (module name) 4pins is searched, and the HDL function description group 12 shown in FIG. 7 is extracted. In the example of FIG. 7, the HDL function description is D Flip-
Flop with synchronous res
et (D flip-flop with asynchronous reset), D
Flip-Flop with asyncrono
us set (D flip-flop with asynchronous set)
Function is described.

§3. Logic Synthesis Tool The logic synthesis tool 20 uses the single library for logic synthesis shown in FIG. 4 (or FIG. 5) to perform logic synthesis of the HDL function description group shown in FIG. Is generated. Further, at that time, the HDL of the HDL function description group 12 which is logically synthesized (mapped)
HD in which functional descriptions are extracted and a single library is synthesized
The L function description 15 is generated.

If the independent library 11 is a 2-input NAND, logic synthesis of the HDL function description group 12 is performed by using the independent library 11, and the result is 2 in the HDL function description.
Mapping can be performed for the input NAND. On the other hand, with respect to other HDL function descriptions, since the single library 11 is only a 2-input NAND, mapping cannot be performed. That is, independent library 1
When the logic synthesis of the HDL function description group 12 is performed using 1,
Only the netlist of the HDL functional description having the same logic as that of the single library 11 which can be mapped is obtained after the synthesis. As shown in the diagram of the logic synthesis tool 20 of FIG. 2, the NAND of the single library 11 is mapped to the nand of the HDL function description, but other HDLs are mapped.
It is not mapped to the function description, and the netlist 14 is N
It becomes the netlist 14 of AND only.

§4. First Simulation Means The first simulation means 21 performs a simulation on the netlist 14 using the corresponding simulation test pattern 16 and the logic simulation logic model, and obtains a first result.

The simulation test pattern 16 is
It is prepared in a one-to-one relationship with the HDL function description of the HDL function description group template 10. As shown in FIG.
HDL function description of the DL function description group template 10, i
For each of nv, nand, nor, and, or, dff, the simulation test pattern 16 has i
nv. pat, nand. pat, nor. pat, a
nd. pat, or. pat, dff. pat is prepared. Therefore, if the netlist 14 is NAND, the simulation test pattern 16 is nan.
d. Pat is selected and the simulation is performed.

For example, a pattern is given as shown in Table 1 and a first result is obtained as shown in Table 1.

[Table 1] As shown in Table 1, patterns that can take all the possible states of the simulated netlist NAND are the pattern nand. pat has. The same applies to the other simulation test patterns 16.

As another example, a simulation test pattern 16 of the D flip-flop with asynchronous reset, dff. The pattern for pat is shown in Table 2 below.

[Table 2] As shown in Table 2, patterns (in, clk, rese
Given t), the result out is obtained as shown in Table 2. When reset is 1, in is 0 and clk is L
When rising from ow to High, out is 0, res
When et is 1, when in is 1 and clk rises from Low to High, out is 1 and reset is 0.
In the case of, out is 0 regardless of in and clk.

§5. Second simulation means HDL function description 1 to which the single library 11 extracted by the second simulation means 22 is mapped
For No. 5, simulation is performed using the same simulation test pattern 16 as used in the first simulation means, and a second result is obtained.

§6. Result comparing means and output means The result comparing means 23 compares whether or not the output values of the same patterns of the first result and the second result are the same, and a verification result is obtained. Then, the output unit 24 outputs the verification result. The output form is output as a display screen of the display device 4, a data file, or a printed out list.

The output contents include the name of the library under test, the name of the tested logical model, the name of the reference library, the name of the logical model of the reference library used for the test, and the result determined by the result comparing means 23. If the determination is no, the test pattern in the case of no, the name of the logical model determined to be no, and the like.

Then, the above processing steps §1. ~ §6. It is possible to obtain the verification results of all the logic modules by repeating the above for the logic modules other than the verified ones. The output of the verification result by the output means 24 may be a method in which it is sequentially output every time one logic module is verified as described above, or a method in which it is collectively output after verification of all the logic modules. Good.

[0029]

As described above, according to the present invention, it is possible to verify a plurality of logical models in a library under test automatically without the need for human judgment. If the template of the HDL function description group covers the functions of all the logical models, all the logical models can be verified by the above-mentioned sequential processing. Therefore, the verification is highly reliable and efficient. Further, in performing the verification work, it is not necessary to know and understand the function of each logical model, and since the verification work may be simply performed according to the determined procedure, there is no difference due to the skill level of the verification worker.

[Brief description of drawings]

FIG. 1 is a diagram showing a hardware configuration of a logical model verification device of the present invention.

FIG. 2 is a flowchart showing a processing process by the logical model verification device of the present invention.

FIG. 3 is a diagram showing a part of contents of a library under test for logic synthesis.

FIG. 4 is a diagram showing an example (NAND) of a single library generated from a library under test for logic synthesis.

FIG. 5 is a diagram showing an example (DFF) of a single library generated from a library under test for logic synthesis.

FIG. 6 is a diagram showing an HDL function description group with a pin number of 3 generated by an HDL function description group extraction means.

FIG. 7 is a diagram showing an HDL function description group having four pins generated by an HDL function description group extraction means.

FIG. 8 is a diagram showing an example of design data in HDL description.

FIG. 9 is a diagram showing an example of a logic circuit synthesized by a logic synthesis tool.

[Explanation of symbols]

 1 arithmetic processing device 2 keyboard 3 mouse 4 display device 5 FD device 6 storage device 7 printer 8 LAN 9 test library for logic synthesis 10 HDL function description group template 11 single library 12 HDL function description group 13 logic model for simulation 14 Netlist 15 HDL function description 16 Simulation test pattern 17 Verification result 18 Single library generation means 19 HDL function description group extraction means 20 Logic synthesis tool 21 First simulation means 22 Second simulation means 23 Result comparison means 24 Output means

Claims (1)

[Claims] 1. A single library extracting means for generating a single library by extracting a logic model for individual logic synthesis to be tested from a test target library for logic synthesis, and the number of input / output pins of the logic model of the single library. The HDL function description group extracting means for counting and extracting the HDL function description group corresponding to the number of pins from the HDL function description group template and the independent library are used to perform the logic synthesis of the HDL function description group to generate a netlist. A logic synthesizing tool to be generated, first net simulation means for simulating the netlist using a corresponding simulation test pattern and a logic model for logic simulation, and the logic synthesized HDL. Regarding the functional description, the simulation test pattern A second simulation means for obtaining a second result, a result comparing means for obtaining a verification result by comparing the first result with the second result, and an output for outputting the verification result. A logical model verification device comprising means and.