JPH07296525A - Phase synchronization circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To simplify the circuit configuration of the voltage control filter for the phase locked loop in the partial response playback system. In a phase synchronization circuit for generating a clock phase-synchronized with a signal read by a head, a voltage difference for converting a phase difference between a signal obtained by waveform equalizing the signal read from the head and a synchronization clock into a voltage difference. Calculator 25 and integral filter 2 for smoothing the output of the voltage difference calculator 25
6 and a voltage controlled oscillator 27 for generating a synchronous clock of controlled phase at the output of the integral filter 26.

Description

Detailed Description of the Invention

(Table of Contents) Industrial Application Field of the Prior Art (FIG. 6) Problem to be Solved by the Invention Means for Solving the Problem (FIG. 1) Action Example (a) Description of One Example (FIG. 2) To FIG. 5) (b) Description of another embodiment Effect of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit in a partial response reproduction system. In order to improve the recording density of magnetic disks and magneto-optical disk devices in recent years, partial response signals (Partial-response
ignaling) is used. In particular, partial response signalization (PRML: Partial-re
sponse signaling with maximum-likelihood sequence
detection) is preferred.

In such a partial response reproducing system, if the phase of the synchronizing clock is deviated, a demodulation error of the output signal of the recording channel occurs. Therefore, it is necessary to correct the phase of the synchronization clock with the phase error detected from the equalized amplitude value and the determination value.

[0004]

2. Description of the Related Art FIG. 6 is an explanatory view of a conventional technique. As shown in FIG. 6, when the head is reading the signal of the magnetic disk medium, the switching circuit 18 connects the gm amplifier filter 16 to the voltage difference calculator 15. Then, the partial equalizer 14, the voltage difference calculator 15, the gm amplifier filter 16, and the voltage controlled oscillator 17 form a PLL loop.

In this PLL loop, during reading, the signal read from the disk medium is waveform-equalized by a partial equalizer 14 which is an equalizer for partial response reproduction. The partial equalizer 14 is composed of an equalization filter having a characteristic of 1 + D and a cosine equalizer. Equalized read signal and voltage controlled oscillator 1
The output of 7 is input to the voltage difference calculator 15. The voltage difference calculator 15 calculates the phase difference between the output signal of the partial equalizer 14 and the output of the voltage controlled oscillator 17.

For example, in the PRML class-4, the voltage difference calculator 15 is F.Dolivo.W.Sco.
Paper by tt and G. Ungerbock "FAST TIMING RECOVERY
FOR PARTIAL-RESPONSE SIGNALING SYSTEMS "(1986 IE
EE CH2655-9 / 89 / 0000-0573). That is, the sampling voltage of the read signal after partial equalization is set to Y
Let (n) be the result of the ternary determination by the demodulator (three-valued determinator) in the voltage difference calculator 15 and be X (n).
τ (n) is represented by the following formula. Δτ (n) = Y (n−1) · X (n) −Y (n) · X
(N-1)

The voltage difference calculator 15 outputs the phase difference as a voltage to the gm amplifier filter 16. The gm amplifier filter 16 smoothes the voltage signal. Then, the voltage controlled oscillator 17 is controlled by the output of the gm amplifier filter 16. As a result, the clock output from the voltage controlled oscillator 17 is synchronized with the read signal.

On the other hand, when not reading, the switching circuit 18 connects the gm amplifier filter 16 to the phase / voltage converter 13. Thereby, the external oscillator 11, the phase comparator 12, the phase / voltage converter 13, the gm amplifier filter 16, and the voltage controlled oscillator 17 form a PLL loop.

That is, it is necessary to keep the output of the voltage controlled oscillator 17 at the center of the reproduction clock frequency except when reading. It is also used as a clock for writing to the magnetic disk medium. Therefore, the PLL loop is formed with the external oscillator 11 that can obtain a stable frequency as a reference.

To explain this operation, the output of the external oscillator 11 and the output of the voltage controlled oscillator 17 are compared to the frequency phase comparator 1.
Enter 2. The frequency / phase comparator 12 outputs a signal corresponding to the phase difference between the output of the external oscillator 11 and the output of the voltage controlled oscillator 17. A voltage signal corresponding to the phase difference signal is output by the phase / voltage converter 13. Then, this voltage is smoothed by the gm amplifier filter 16 and the voltage controlled oscillator 17 is controlled.

As described above, in the prior art, since the phase difference at the time of reading is output as the voltage difference, the smoothing filter uses the gm amplifier filter 16 which is a voltage control type filter. The gm amplifier filter 16 was a filter in which a plurality of gm amplifiers were connected in series and a capacitor was provided in the feedback loop.

[0012]

This voltage control filter is composed of a gm amplifier filter because the gm amplifier can change the cutoff frequency. That is, it is convenient to control the cutoff frequency for each zone of the magnetic disk.

This gm amplifier filter has a problem that the structure is complicated and the circuit scale becomes large. or,
There is also a problem that the structure is complicated and therefore expensive.

An object of the present invention is to provide a phase locked loop circuit for simplifying the circuit configuration of the voltage control filter.

Another object of the present invention is to provide a phase locked loop circuit for making the voltage control filter inexpensive and having a small circuit scale.

[0016]

FIG. 1 shows the principle of the present invention. According to a first aspect of the present invention, in a phase synchronization circuit for generating a clock phase-synchronized with a signal read by a head, a phase difference between a signal obtained by waveform-equalizing a signal read from the head and a synchronous clock is a voltage difference. A voltage difference calculator 25 for converting the output of the voltage difference calculator 25, an integral type filter 26 for smoothing the output of the voltage difference calculator 25, and a voltage controlled oscillator 27 for generating a synchronous clock of a controlled phase at the output of the integral type filter 26 And having.

According to a second aspect of the present invention, in the phase locked loop circuit according to the first aspect, the oscillator 21 and the phase comparator 22 for comparing the phase of the output of the oscillator 21 and the phase of the synchronous clock.
A phase / voltage converter 23 for converting the phase difference output of the phase comparator 22 into a voltage; and the integration filter 26 connected to the voltage difference calculator 25 when the head is read,
When the head is not read, a switching circuit 28 for connecting the integration filter 26 to the phase / voltage converter 23 is further provided.

[0018]

In the present invention, the integral type passive filter is used as the voltage control filter. In the prior art, the reason why the gm amplifier filter is used as the voltage control filter is to change the frequency characteristic for each zone of the disk by the gm amplifier filter. As a result of studies by the present inventors, it has been found that the change in frequency characteristic due to the track density for each zone can be absorbed to some extent by the original operation of the voltage controlled oscillator 27. Therefore, it is not necessary to use the gm amplifier filter as the voltage control filter in consideration of the frequency characteristic. From this result, the present invention uses an integral type filter having a simple configuration as the voltage control filter. As a result, the voltage control filter can be realized with a simple structure and at a low cost.

[0019]

【Example】

(A) Description of an embodiment FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of the voltage difference calculator of FIG. 2, FIG. 4 is a time chart diagram of FIG. FIG. 3 is a time chart diagram at the time of reading in FIG.

In FIG. 2, the external oscillator 21 is composed of a crystal oscillator or the like. Then, the external oscillator 21 is
Generates a clock with a fixed period. Frequency / phase comparator 22
Is the output clock of the external oscillator 21 and the voltage controlled oscillator 2
It compares the phase with the synchronization clock of No. 7 and outputs a signal (phase difference signal) according to the phase difference. The phase / voltage converter 23 converts the phase difference signal from the frequency phase comparator 22 into a voltage.

The partial equalizer 24 has an equalization filter having a characteristic of (1 + D) and a cosine equalizer. Then, after the read signal from the head is equalized by the equalization filter, the equalized signal is automatically equalized by the cosine equalizer according to the partial response characteristic in the radial direction of the disk.

The voltage difference calculator 25 comprises a sample circuit composed of an analog-digital converter and a phase difference calculator circuit shown in FIG. Then, the voltage difference calculator 25
The sample circuit samples the equalized signal with the synchronous clock. The voltage difference calculator 25 calculates a voltage signal indicating a phase difference from the amplitude of the sampled signal.

The voltage control filter 26 is for cutting high frequency components of the voltage signal from the voltage difference calculator 25 or the phase / voltage converter 23, and is composed of an integrating circuit. This integrating circuit includes an input resistor R1 and an input resistor R
1 and a current adjusting resistor R2 provided between the ground and a capacitor C. Therefore, this integration circuit
It forms a well-known integral type passive filter.

The voltage controlled oscillator 27 generates a synchronous clock having a phase according to the voltage. This synchronous clock is output to the frequency / phase comparator 22 and the voltage difference calculator 25. The switching circuit 28 connects the voltage control filter 26 to the voltage difference calculator 25 when the head is read, and the voltage control filter 26 when the head is not read.
Is connected to the phase / voltage converter 23.

The phase difference calculation circuit of the voltage difference calculator 25 will be described with reference to FIG. The ternary determination circuit 250 compares the sample value Y (n) with the two slice levels S1 and S2 and determines a determination value X (n) of +1, 0, −1. The first delay element 251 has a sample value Y
(N) is delayed by one sample to obtain Y (n-1). The second delay element 252 delays the determination value X (n) by one sample to obtain X (n-1). The first multiplier 253 multiplies Y (n-1) and X (n). The second multiplier 254 is Y
(N) is multiplied by X (n-1). The adder 255 outputs the output Y (n−1) · X of the first multiplier 253.
From (n) the output of the second multiplier 254 Y (n) .X (n
−1) is subtracted to obtain the phase difference Δτ (n).

Next, the operation of the circuit shown in FIG. 2 will be described. When the head is reading the signal of the magnetic disk medium, the switching circuit 28 connects the voltage control filter 26 to the voltage difference calculator 25. And the partial equalizer 2
4, the voltage difference calculator 25, the voltage control filter 26, and the voltage control oscillator 27 form a PLL loop.

In this PLL loop, at the time of reading, the signal read from the disk medium is waveform-equalized by a partial equalizer 24 which is an equalizer for partial response reproduction. As shown in FIG. 5, the equalized signal is sampled by the analog-digital converter of the voltage difference calculator 15 at the timing of the synchronous clock of the voltage controlled oscillator 17. The sample value Y (n) is ternary judged by the ternary judgment circuit 250.

As shown in FIG. 5, the difference Δa between the amplitude of the sampled value Y (n) and the reference voltage a is proportional to the phase difference ΔT (n). The phase difference calculation circuit of the voltage difference calculator 15 calculates the phase difference Δτ (n) by the above-mentioned formula. That is, the adder 25
5, the output Y (n−1) · X of the first multiplier 253
(N) and the output of the second multiplier 254 Y (n) .X (n-
Find the difference from 1). The voltage output Δτ of this adder 255
(N) is Y (n-1) .X (n) -Y (n) .X (n
-1).

The voltage difference calculator 25 outputs this voltage signal to the voltage control filter 26. The voltage control filter 26 smoothes this voltage signal by the capacitor C. Then, the voltage controlled oscillator 27 is controlled by the output of the voltage controlled filter 26. As a result, the clock output from the voltage controlled oscillator 27 is synchronized with the read signal.

On the other hand, when not in reading, the voltage control filter 26 is connected to the phase / voltage converter 23 by the switching circuit 28. As a result, the external oscillator 21, the phase comparator 22, the phase / voltage converter 23, the voltage control filter 26, and the voltage control oscillator 27 form a PLL loop.

This operation will be described with reference to FIG. The output of the external oscillator 21 and the output of the voltage controlled oscillator 27 are input to the frequency phase comparator 22. The frequency / phase comparator 22 outputs a signal corresponding to the phase difference between the output of the external oscillator 21 and the output of the voltage controlled oscillator 27. A voltage signal corresponding to the phase difference signal is output by the phase / voltage converter 23.
Then, this voltage is smoothed by the voltage control filter 26 and the voltage control oscillator 27 is controlled.

In this way, the voltage control filter is
Since it is configured by the passive filter including the integrating circuit, the voltage control filter can be configured easily and inexpensively. Further, the difference in the frequency characteristic of the magnetic disk in the radial direction can be absorbed to some extent by the voltage controlled oscillator 27.

(B) Description of Other Embodiments In addition to the above embodiments, the present invention can be modified as follows. Although the partial equalizer has been described as an analog one, an analog-digital converter may be provided before the cosine equalizer and the cosine equalizer may be configured as a digital one. In this case, the analog-digital converter of the voltage difference calculator 25 is unnecessary.

Although the example of the magnetic disk has been described, the invention can be applied to a magneto-optical disk or the like. Although the present invention has been described with reference to the embodiments, various modifications are possible within the scope of the gist of the present invention, and these modifications are not excluded from the scope of the present invention.

[0035]

As described above, according to the present invention,
It has the following effects. Since the voltage control filter of the phase locked loop is composed of an integral type filter, the structure becomes simple. Further, since the integral type filter is used, the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a block diagram of the voltage difference calculator of FIG.

FIG. 4 is a time chart diagram of the configuration of FIG. 2 during non-reading.

FIG. 5 is a time chart diagram at the time of reading the configuration of FIG.

FIG. 6 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

 11, 21 External oscillator 12, 22 Frequency phase comparator 13, 23 Phase / voltage converter 14, 24 Partial equalizer 15, 25 Voltage difference calculator 26 Integral type filter 17, 27 Voltage controlled oscillator 18, 28 Switching circuit

Claims (2)

[Claims] 1. A phase synchronization circuit for generating a clock phase-synchronized with a signal read by a head, wherein a phase difference between a signal obtained by waveform-equalizing a signal read from the head and a synchronization clock is converted into a voltage difference. A voltage difference calculator (25), an integral filter (26) for smoothing the output of the voltage difference calculator (25), and a synchronous clock of a phase controlled by the output of the integral filter (26) And a voltage controlled oscillator (27) that operates. 2. The phase locked loop circuit according to claim 1, further comprising: an oscillator (21); and a phase comparator (22) for comparing the phase of the output of the oscillator (21) with the phase of the synchronous clock.
A phase / voltage converter (23) for converting the phase difference output of the phase comparator (22) into a voltage, and the integration filter (26) for the voltage difference calculator (2) when the head is read.
5) and a switching circuit (28) for connecting the integration filter (26) to the phase / voltage converter (23) when the head is not read. .