JPH07297721A - AD conversion method - Google Patents

Abstract

(57) [Summary] [Structure] In order to achieve the above object, the present invention provides a latch circuit of m (m = 2, 3 ...) Systems as an output circuit of an AD converter, and divides the output into m systems. (Demultiplexing) the up date rate of one system to AD
The conversion frequency of C is set to 1 / m, and the conversion frequency of ADC can be dynamically improved. According to the present invention, an AD converted value converted at an extremely high speed can be output at a low speed simply by arranging a latch circuit in parallel with the output, so that it is necessary to use a special circuit or device. It is possible to realize an ultra-high-speed ADC extremely economically.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter, and more particularly to a conversion method for a high speed AD converter.

[0002]

2. Description of the Related Art Generally, a parallel comparison method is used as a high-speed AD converter (hereinafter abbreviated as ADC), which is shown in FIG.
If n is the number of output bits, as shown in (2n-1)
Each of the reference voltages V _j divided into levels and the analog input voltage V _IN are (2n−1) (2n if there is overflow) comparators 10 and these comparators 1.
Code conversion circuit 2 for converting output from 0 to binary code
Consists of. This method is suitable for a monolithic IC because it does not use any special element. Further, as shown in FIG. 4, the code conversion circuit is multi-staged and the latch circuit is combined to perform pipeline processing to achieve high speed (eg, Yoshii, Asano et al. "8 bit, 100 MS / S flash type ADC"). Television Society Technical Report TEB397-
3, 1946).

With such a circuit configuration suitable for high speed operation and recent high speed operation of devices, an extremely high speed ADC is being realized. However, although the inside of the IC can operate at an extremely high speed as described above, there is a problem that the digital signal output limits the high speed operation due to the capacity attached to the load. Specifically, many output forms are of ECL level, and many are output by an emitter follower circuit as shown in FIG. When a capacitance C is added to this circuit as a load, when a resistor R is connected to the emitter of the emitter follower as shown in FIG.
C) and when a constant current source is connected to the etter, the conversion frequency is limited by the discharge time td (= CV / I; V is the output signal amplitude and I is the current of the constant current source). For example, in the circuit of (b), the load capacitance C is 20 pF,
V = 1V, and I depends on the size of the output transistor, but a maximum of about 10 mA is practical, and at this time td
Is 2 ns. Further, in the same figure (a), R = 10
If 0Ω is set, r becomes 2 ns, and thus the conversion frequency is limited to 500 MHz. Furthermore, it is not easy to transmit such a high-speed signal, and it is very difficult to realize an ADC having a conversion frequency of 300 to 500 MHz or more by the conventional method.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide an ultra high speed ADC.

[0005]

In order to achieve the above object, the present invention uses m (m = 2, m) as an output circuit of an AD converter.
3) system latch circuits are prepared, and the output is divided into m systems (demultiplexing) so that one system u
By making the p date rate 1 / m of the ADC conversion frequency, it is possible to improve the ADC conversion frequency dynamically.

[0006]

In order to achieve the above object, the present invention prepares an m (m = 2, 3 ...) system latch circuit as an output circuit of an AD converter and divides the output into m systems (demultiplex). By doing this, the up date rate of one system is AD
The conversion frequency of C is set to 1 / m, and the conversion frequency of ADC can be dynamically improved.

[0007]

EXAMPLES The present invention will be described below with reference to examples. Figure 1
Shows the first embodiment, and a parallel comparison type ADC is shown as an example. In the figure, 1 is a comparator group consisting of a number of comparators corresponding to the required resolution, and 2 is a code conversion circuit (encoder) for converting the output of the comparator into a binary code or the like. The figure shows a case where two latch circuits 31 and 32 are arranged and the output of the code conversion circuit 2 is input to each latch circuit. FIG. 2 shows the timing diagram of FIG. The outputs from the code conversion circuit 2 converted at the conversion frequency f are latched by the latches 31 and 32,
The output of each latch has a rate half that of the conversion frequency f of the ADC.

The above is the case where two latch circuits are prepared and output to two systems, but m latch circuits are prepared,
If the output of the ADC is sequentially latched and output to the m system, the output of each latch will be divided into 1 / m of the conversion frequency of the ADC.

As described above, according to this embodiment, it is possible to obtain the AD converted value converted at high speed at low speed.

Although the parallel comparison type ADC is used for the sake of convenience in the above description, it is clear that the AD converter system may be of any type in principle, and that a high-speed AD conversion value can be stably obtained by the present invention.

Further, in such an ultra high speed ADC,
The clock itself becomes faster, and even a slight time lag causes a malfunction. Therefore, when there are two or more systems of output latches, it is necessary to lay out in consideration of the wiring length and the like, and it is necessary to prevent the time shift as much as possible. An example of the layout is shown in FIG. The figure shows a case where the output latch is of two systems, and 100 is an ADC including, for example, a comparator and a code conversion circuit. From now on, n output bit lines are being output, and these are two sets of latch circuit groups (consisting of n latch circuits) 31, 32.
Has been converted to. Reference numerals 41 and 42 denote circuits for generating latch clocks φ ₁ and φ ₂ , which are synchronized with a reference clock. The feature of this layout is that the latch circuit and the clock generation circuit are arranged line-symmetrically with respect to the output of the ADC 100. For example, a bit line input to a latch circuit located outside one latch circuit group is input to a latch circuit located outside the other latch circuit group. As a result, the signal of the output bit line input to the two sets of latch circuit groups is propagated between the two sets of latch circuit groups without a time delay. On the other hand, in the latch circuit group, the distance of each bit line to the latch circuit is slightly different, but if the clock generation circuit is placed inside, the clock is delayed as well as each bit line, so the output signal of the bit line On the other hand, the timing of latching between each bit will not be shifted. With the layout as described above, the output signal can be stably latched.

[0012]

EFFECTS OF THE INVENTION According to the present invention, the A converted at an extremely high speed
Since the output can be taken out at a low speed simply by arranging the D conversion value in parallel with the latch circuit at the output, there is no need to use a special circuit or device, and it is extremely economical and extremely high speed AD.
C can be realized.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram of FIG.

FIG. 3 is a diagram showing a configuration of a conventional parallel comparison type ADC.

FIG. 4 is a diagram showing a configuration of a conventional parallel comparison type ADC.

FIG. 5 is a diagram showing an output circuit.

FIG. 6 is a diagram showing an example of a layout when the present invention is integrated into an IC.

[Explanation of symbols]

10 ... Comparator, 1 ... Comparator group, 2 ... Code conversion circuit, 3
1, 32 ... Latch circuit.

Claims (2)

[Claims] 1. A step of comparing one analog input signal with a plurality of reference signals, a step of converting a comparison result into a digital code at a predetermined clock frequency, and a step of temporarily storing the conversion result in a latch circuit for external output. In the AD conversion including the latch process for m, m (m = 2, 3, 4 ...) The latch process has at least two systems of latch circuits,
An AD conversion method, wherein the frequency of taking in the latch and outputting it to the outside is 1 / m of the clock frequency. 2. The AD conversion method according to claim 1, wherein m
AD conversion method, wherein is at least 2.