JPH0730383A - Pulse signal generating circuit - Google Patents
Pulse signal generating circuitInfo
- Publication number
- JPH0730383A JPH0730383A JP5169952A JP16995293A JPH0730383A JP H0730383 A JPH0730383 A JP H0730383A JP 5169952 A JP5169952 A JP 5169952A JP 16995293 A JP16995293 A JP 16995293A JP H0730383 A JPH0730383 A JP H0730383A
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- JP
- Japan
- Prior art keywords
- signal
- circuit
- phase
- modulation
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001934 delay Effects 0.000 claims abstract description 4
- 239000000284 extract Substances 0.000 claims abstract description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 17
- 238000001514 detection method Methods 0.000 claims description 11
- 238000000605 extraction Methods 0.000 abstract description 4
- 230000010363 phase shift Effects 0.000 abstract 1
- 230000005540 biological transmission Effects 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 1
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、位相変調されたクロッ
ク信号の位相変動を除去するパルス信号発生回路に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse signal generating circuit for removing a phase fluctuation of a phase-modulated clock signal.
【０００２】[0002]
【従来の技術】一般に、基幹伝送のネットワーク構成に
おけるクロック供給装置は、局内の各種装置に安定な基
準クロック信号を送出している。クロック供給装置と各
種装置との間は、基準クロック信号を送出するためのイ
ンタフェースのみが介在されるので、送信側における送
出クロックに関する情報や、クロック供給側で故障等の
情報はクロックの受信側では分からないのが現状であ
る。2. Description of the Related Art In general, a clock supply device in a backbone transmission network configuration sends a stable reference clock signal to various devices in a station. Since only the interface for transmitting the reference clock signal is interposed between the clock supply device and various devices, information about the transmission clock on the transmission side and information such as a failure on the clock supply side are received on the clock reception side. The current situation is that I don't understand.
【０００３】送信側の情報を受信側に送る手段として
は、先ず問題とする情報を送るための専用の別線を設け
ることが考慮されるが、クロック供給装置と被クロック
供給装置と間の全てに新たな信号用の送受信回路を付設
し、それらを結ぶ専用のケーブルを設けると、物理的に
多大なスペースが必要となる上、費用も膨大になる。従
って、既に各装置に個々に伝送されているクロック信号
を変調して情報を乗せる方法が望ましい。As a means for transmitting information on the transmitting side to the receiving side, it is considered to provide a dedicated separate line for transmitting the information in question, but it is necessary to provide a separate line between the clock supplying device and the clock receiving device. If a transmission / reception circuit for a new signal is attached to and a dedicated cable for connecting them is provided, a physically large space is required and the cost becomes enormous. Therefore, it is desirable to modulate the clock signal that has already been individually transmitted to each device to carry information.
【０００４】そこで、こうした場合に受信側でクロック
信号を受けてこれをパルス波形として扱う際に、図３に
示すようなパルス信号発生回路が用いられる。このパル
ス信号発生回路は、入力端子１より入力され，位相変調
された入力クロック信号Ａの電圧値を電圧比較回路５に
よって基準電圧部６からの基準電圧値との間で比較し、
両信号における電圧差に応じて異なる２つの論理レベル
を発生すると共に、これらの２つの論理レベルに基づく
パルス矩形波信号Ｄを出力端子２へ出力する。Therefore, in such a case, when the receiving side receives the clock signal and handles it as a pulse waveform, a pulse signal generating circuit as shown in FIG. 3 is used. The pulse signal generation circuit compares the voltage value of the input clock signal A, which is input from the input terminal 1 and is phase-modulated, with the reference voltage value from the reference voltage section 6 by the voltage comparison circuit 5,
Two different logic levels are generated according to the voltage difference between the two signals, and the pulse rectangular wave signal D based on these two logic levels is output to the output terminal 2.
【０００５】[0005]
【発明が解決しようとする課題】上述したパルス信号発
生回路の場合、出力端子２から出力されるパルス矩形波
信号Ｄは、図４（図３に示すパルス信号発生回路におけ
る入出力波形を示したもの）に示す如く入力クロック信
号Ａが正弦波であるとき、しばしば入力クロック信号Ａ
における位相変調により基準クロックの周期Ｔに対して
ｔ１，ｔ２，ｔ３，…といった位相の変動（ジッタ）が
含まれたパルス波となってしまう。従来のパルス信号発
生回路では、不要な位相変動を除去するためには位相同
期発振器等が必要になる。このように、受信信号中のジ
ッタを抑制除去する位相同期発振器に関連する技術は、
例えば特開昭６２−２０４４２号公報，特開昭６２−１
４９２３２号公報，及び特開平３−１１９８８２号公報
等に開示されている。In the case of the pulse signal generation circuit described above, the pulse rectangular wave signal D output from the output terminal 2 has the input / output waveforms shown in FIG. 4 (the pulse signal generation circuit shown in FIG. 3). When the input clock signal A is a sine wave as shown in FIG.
Due to the phase modulation in (1), a pulse wave including phase fluctuations (jitter) such as t1, t2, t3, ... In the conventional pulse signal generation circuit, a phase locked oscillator or the like is required to remove unnecessary phase fluctuation. Thus, the technology related to the phase-locked oscillator that suppresses and removes the jitter in the received signal is
For example, Japanese Patent Laid-Open Nos. 62-20442 and 62-1
It is disclosed in Japanese Patent No. 49232, Japanese Patent Laid-Open No. 3-119882, and the like.
【０００６】ところが、位相同期発振器を備えるとパル
ス信号発生回路自体が高価になってしまう上、回路全体
の規模も大きくなってしまい、現状ではその使用が望ま
れていない。However, if the phase-locked oscillator is provided, the pulse signal generation circuit itself becomes expensive, and the scale of the entire circuit becomes large, so that its use is not desired at present.
【０００７】本発明は、かかる問題点を解決すべくなさ
れたもので、その技術的課題は、簡素に構成されると共
に、入力クロック信号における位相変調により生じる位
相の変動を十分に除去できるパルス信号発生回路を提供
することにある。The present invention has been made to solve the above problems, and its technical problem is to simply construct a pulse signal capable of sufficiently eliminating fluctuations in phase caused by phase modulation in an input clock signal. It is to provide a generating circuit.
【０００８】[0008]
【課題を解決するための手段】本発明によれば、位相変
調された入力クロック信号からその変調成分のみを取り
出す変調信号検出回路と、変調信号検出回路による処理
時間に等しい時間分，入力クロック信号を遅延させる遅
延回路と、変調信号検出回路から出力される出力信号と
遅延回路から出力される出力信号との電圧を比較し、該
両信号の電圧差に基づいてパルス信号を出力する電圧比
較回路とを備えたパルス信号発生回路が得られる。According to the present invention, a modulation signal detecting circuit for extracting only the modulation component from a phase-modulated input clock signal, and an input clock signal for a time equal to the processing time by the modulation signal detecting circuit. And a voltage comparison circuit for comparing the voltage of the output signal output from the modulation signal detection circuit and the voltage of the output signal output from the delay circuit, and outputting a pulse signal based on the voltage difference between the two signals. A pulse signal generation circuit having the following is obtained.
【０００９】又、本発明によれば、上記パルス信号発生
回路において、電圧比較回路は、両信号の電圧差に応じ
て異なる２つの論理レベルを発生し、該２つの論理レベ
ルに基づく矩形波をパルス信号として出力するパルス信
号発生回路が得られる。Further, according to the present invention, in the pulse signal generation circuit, the voltage comparison circuit generates two different logic levels according to the voltage difference between the two signals, and generates a rectangular wave based on the two logic levels. A pulse signal generation circuit for outputting as a pulse signal can be obtained.
【００１０】[0010]
【実施例】以下に実施例を挙げ、本発明のパルス信号発
生回路について、図面を参照して詳細に説明する。図１
は、本発明の一実施例に係るパルス信号発生回路の構成
を示したものである。The pulse signal generating circuit of the present invention will be described in detail below with reference to the accompanying drawings. Figure 1
FIG. 4 shows a configuration of a pulse signal generation circuit according to an embodiment of the present invention.
【００１１】このパルス信号発生回路は、位相変調され
た入力クロック信号Ａ中に含まれる位相変調を検出し、
その変調成分を取り出す変調信号検出回路３と、変調成
分の取り出し処理時間に等しい時間だけ入力クロック信
号Ａを遅延させる遅延回路４と、変調信号検出回路３か
ら出力される変調出力信号Ｂと遅延回路４から出力され
るクロック遅延出力信号Ａ´との電圧値を比較し、これ
らの両信号の電圧差に基づいてパルス矩形波信号Ｃを発
生する電圧比較回路５とを備えている。This pulse signal generating circuit detects the phase modulation contained in the phase-modulated input clock signal A,
A modulation signal detection circuit 3 that extracts the modulation component, a delay circuit 4 that delays the input clock signal A by a time equal to the extraction processing time of the modulation component, a modulation output signal B that is output from the modulation signal detection circuit 3, and a delay circuit. And a voltage comparison circuit 5 for generating a pulse rectangular wave signal C based on the voltage difference between the two signals and the clock delay output signal A '.
【００１２】次に、このパルス信号発生回路の動作を説
明する。但し、ここでは初期的に周波数ｆ1 の入力クロ
ック信号Ａがその周波数ｆ1 に対して非常に小さい周波
数ｆ2 の位相変調成分を含んでいるとする。Next, the operation of this pulse signal generating circuit will be described. However, here, the input clock signal A of initially frequency f 1 contains a very small phase modulation component of the frequency f 2 with respect to the frequency f 1.
【００１３】先ず入力端子１から入力された入力クロッ
ク信号Ａは、変調信号検出回路３に入力され、この変調
信号検出回路３で位相の変調成分が検出される。変調信
号検出回路３としては、復調器のように主信号の位相変
化分を取り出せる機能を持つものを用いれば良い。これ
により取り出された変調出力信号Ｂは、電圧比較回路５
に入力される。First, the input clock signal A input from the input terminal 1 is input to the modulation signal detection circuit 3, and the modulation signal detection circuit 3 detects the phase modulation component. As the modulation signal detection circuit 3, a demodulator having a function of extracting the phase change of the main signal may be used. The modulated output signal B thus extracted is the voltage comparison circuit 5
Entered in.
【００１４】一方、入力クロック信号Ａは遅延回路４に
も入力され、この遅延回路４で変調信号検出回路３によ
る位相の変調成分の取り出し処理時間に等しい時間だけ
入力クロック信号Ａを遅延させることにより、クロック
遅延出力信号Ａ´を出力する。このクロック遅延出力信
号Ａ´は電圧比較回路５に入力される。On the other hand, the input clock signal A is also input to the delay circuit 4, and the delay circuit 4 delays the input clock signal A by a time equal to the extraction processing time of the phase modulation component by the modulation signal detection circuit 3. , And outputs a clock delay output signal A ′. This clock delay output signal A ′ is input to the voltage comparison circuit 5.
【００１５】電圧比較回路５では、変調出力信号Ｂとク
ロック遅延出力信号Ａ´との電圧値を比較し、これらの
各信号Ａ´，Ｂの電圧差に応じて異なる２つの論理レベ
ルを発生すると共に、これらの２つの論理レベルに基づ
くパルス矩形波信号Ｃを発生して出力端子２へ出力す
る。The voltage comparison circuit 5 compares the voltage values of the modulated output signal B and the clock delay output signal A ', and generates two different logic levels according to the voltage difference between these signals A'and B. At the same time, the pulse rectangular wave signal C based on these two logic levels is generated and output to the output terminal 2.
【００１６】ここで、入力クロック信号Ａの位相差が大
きくなる過程において、クロックの立ち上がりに着目す
ると、位相差の変化は電圧の変化に対応するので、図２
（図１に示すパルス信号発生回路における入出力波形を
示したもの）を参照すれば、電圧比較回路５によりクロ
ック遅延出力信号Ａ´の電圧値から変調出力信号Ｂの電
圧値を差し引いて発生したパルス矩形波信号Ｃは、クロ
ック遅延出力信号Ａ´（クロック信号Ａの場合も同様）
の立ち上がりに対して位相差が補正されたものとなる。
即ち、電圧比較回路５ではクロックの立ち上がりが検出
されてから一定時間，正パルスを生成することで位相の
揃ったＤＵＴＹ比５０％の矩形波を得ることができる。Here, focusing on the rising edge of the clock in the process of increasing the phase difference of the input clock signal A, a change in the phase difference corresponds to a change in the voltage.
With reference to (showing the input / output waveforms in the pulse signal generating circuit shown in FIG. 1), the voltage comparing circuit 5 generates by subtracting the voltage value of the modulation output signal B from the voltage value of the clock delay output signal A ′. The pulse rectangular wave signal C is a clock delay output signal A ′ (the same applies to the clock signal A).
The phase difference is corrected for the rising edge of.
That is, in the voltage comparison circuit 5, a positive pulse is generated for a certain period of time after the rising edge of the clock is detected, so that a rectangular wave with a DUTY ratio of 50% with a uniform phase can be obtained.
【００１７】[0017]
【発明の効果】以上に説明したように、本発明のパルス
信号発生回路によれば、位相変調された入力クロック信
号中に含まれる位相の変調成分を取り出す変調信号検出
回路を設け、遅延回路でこの位相変調成分の取り出し処
理時間に等しい時間だけ入力クロック信号を遅延させ、
更に電圧比較回路でこれらの両回路からの出力信号の電
圧差値に応じて２つの異なる論理レベルを発生すると共
に、これらの２つの異なる論理レベルに基づいて位相変
動を除去したパルス矩形波信号を発生しているので、正
弦波の入力クロック信号に低周波の位相変調がかかって
も位相の変動分を電圧差として捕えられる。これによ
り、比較的簡単な構成で位相変動を除去し得るパルス信
号発生回路が得られるようになる。As described above, according to the pulse signal generating circuit of the present invention, the modulation signal detecting circuit for extracting the phase modulation component contained in the phase-modulated input clock signal is provided and the delay circuit is used. Delay the input clock signal by a time equal to the extraction processing time of this phase modulation component,
Further, the voltage comparison circuit generates two different logic levels according to the voltage difference value of the output signals from these two circuits, and the pulse rectangular wave signal from which the phase fluctuation is removed based on these two different logic levels. Since it is generated, even if the low frequency phase modulation is applied to the sine wave input clock signal, the phase variation can be captured as a voltage difference. As a result, it is possible to obtain a pulse signal generation circuit capable of removing phase fluctuations with a relatively simple configuration.
【図１】本発明の一実施例に係るパルス信号発生回路の
構成を示したものである。FIG. 1 shows a configuration of a pulse signal generation circuit according to an embodiment of the present invention.
【図２】図１に示すパルス信号発生回路における入出力
波形を示したものである。2 shows input / output waveforms in the pulse signal generation circuit shown in FIG.
【図３】従来のパルス信号発生回路の構成を示したもの
である。FIG. 3 shows a configuration of a conventional pulse signal generation circuit.
【図４】図３に示すパルス信号発生回路における入出力
波形を示したものである。4 shows input / output waveforms in the pulse signal generation circuit shown in FIG.
１ 入力端子 ２ 出力端子 ３ 変調信号検出回路 ４ 遅延回路 ５ 電圧比較回路 ６ 基準電圧部 Ａ 入力クロック信号 Ａ´ クロック遅延出力信号 Ｂ 変調出力信号 Ｃ，Ｄ パルス矩形波信号 1 Input Terminal 2 Output Terminal 3 Modulation Signal Detection Circuit 4 Delay Circuit 5 Voltage Comparison Circuit 6 Reference Voltage Section A Input Clock Signal A'Clock Delay Output Signal B Modulation Output Signal C, D Pulse Square Wave Signal
Claims (2)
の変調成分のみを取り出す変調信号検出回路と、前記変
調信号検出回路による処理時間に等しい時間分，前記入
力クロック信号を遅延させる遅延回路と、前記変調信号
検出回路から出力される出力信号と前記遅延回路から出
力される出力信号との電圧を比較し、該両信号の電圧差
に基づいてパルス信号を出力する電圧比較回路とを備え
たことを特徴とするパルス信号発生回路。1. A modulation signal detection circuit that extracts only the modulation component from a phase-modulated input clock signal, a delay circuit that delays the input clock signal by a time equal to the processing time by the modulation signal detection circuit, and A voltage comparison circuit that compares the voltage of the output signal output from the modulation signal detection circuit and the voltage of the output signal output from the delay circuit and outputs a pulse signal based on the voltage difference between the two signals. Characteristic pulse signal generation circuit.
いて、前記電圧比較回路は、前記両信号の電圧差に応じ
て異なる２つの論理レベルを発生し、該２つの論理レベ
ルに基づく矩形波を前記パルス信号として出力するもの
であることを特徴とするパルス信号発生回路。2. The pulse signal generation circuit according to claim 1, wherein the voltage comparison circuit generates two different logic levels according to a voltage difference between the two signals, and generates a rectangular wave based on the two logic levels. A pulse signal generation circuit which outputs as the pulse signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5169952A JP2950351B2 (en) | 1993-07-09 | 1993-07-09 | Pulse signal generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5169952A JP2950351B2 (en) | 1993-07-09 | 1993-07-09 | Pulse signal generation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0730383A true JPH0730383A (en) | 1995-01-31 |
| JP2950351B2 JP2950351B2 (en) | 1999-09-20 |
Family
ID=15895907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5169952A Expired - Lifetime JP2950351B2 (en) | 1993-07-09 | 1993-07-09 | Pulse signal generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2950351B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6879638B1 (en) | 1999-12-28 | 2005-04-12 | International Business Machines Corporation | Method and apparatus for providing communication between electronic devices |
| CN112994507A (en) * | 2021-02-02 | 2021-06-18 | 南京大全电子科技有限公司 | PWM pulse generation method and PWM pulse generation device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63292840A (en) * | 1987-05-26 | 1988-11-30 | Nippon Telegr & Teleph Corp <Ntt> | Clock signal regenerating circuit |
-
1993
- 1993-07-09 JP JP5169952A patent/JP2950351B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63292840A (en) * | 1987-05-26 | 1988-11-30 | Nippon Telegr & Teleph Corp <Ntt> | Clock signal regenerating circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6879638B1 (en) | 1999-12-28 | 2005-04-12 | International Business Machines Corporation | Method and apparatus for providing communication between electronic devices |
| CN112994507A (en) * | 2021-02-02 | 2021-06-18 | 南京大全电子科技有限公司 | PWM pulse generation method and PWM pulse generation device |
| CN112994507B (en) * | 2021-02-02 | 2021-12-10 | 南京君海数能科技有限公司 | PWM pulse generation method and PWM pulse generation device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2950351B2 (en) | 1999-09-20 |
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