JPH0730421A - D / A converter - Google Patents

Abstract

(57) [Abstract] [Objective] To provide a low noise D / A converter. [Structure] The digital data D is converted by the registers 3a and 3b into data D having a phase difference of a sampling cycle Ts.
D / A converters 4a and 4b are divided into odd and even.
Output current I which is the sum of the currents i weighted corresponding to the bits by individually operating the plurality of current switches CS of
1 and I2 are obtained and added by the adder circuit 6. At the time of weighting, the conductivity of the current switch CS is controlled by using the sine wave signals S and S synchronized with the sampling period Ts output from the oscillation circuit 5, and all the individual currents i are smooth sine wave waveforms. By converting to ON and OFF,
Suppresses noise generation due to sudden current changes. The divided data D is separately converted and re-added to cancel harmonics and improve waveform restoration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D / A (digital / analog) converter, and more particularly to a D / A converter which is preferably implemented in a multi-bit D / A converter.

[0002]

2. Description of the Related Art There are various types of so-called D / A converters for converting input digital data into analog data, but a multi-bit type D using a ladder resistor network is used.
A / A converters are widely known. The multi-bit method is
A ladder resistor network and switches corresponding to the current source and the number of bits are prepared, and the switches are individually operated according to the bit codes from the most significant bit (MSB) to the least significant bit (LSB) of digital data for each sampling period, The sum of the currents flowing according to the bits is calculated and converted into an analog output.

FIG. 6 is a circuit diagram showing the structure of a ladder resistor network type D / A conversion circuit. The ladder resistance network type D / A conversion circuit 51 includes a data latch circuit 52 that latches the input digital data D for a certain period, a plurality of current switches CS corresponding to the bit number n of the digital data D, and a resistance value R. And a resistance of 2R that is twice that of R connected in a ladder
-2R type ladder resistor network RN. Input digital data D (n-1), D (n-2), ..., D0
Are latched by the data latch circuit 52, the corresponding current switches CS are individually turned on / off by each bit, and the currents i (n-1), i (n-) corresponding to the weights thereof are turned on.
2), ..., I0 are converted into voltage levels by the current / voltage conversion circuit 53 to obtain an analog output.

FIG. 7 is a block diagram showing the structure of a conventional multi-bit D / A converter. D / A
The converter 101 includes a D / A conversion unit 102 including the ladder resistance network, a current switch, and a latch circuit described above, a current / voltage conversion circuit 103 realized by an operational amplifier and the like, and a low-pass filter 104. . D / A converter 10
A plurality of bits of digital data D and a sampling clock signal CLK are input to 2. Digital data D
Is latched during the sampling period, ON / OFF control the corresponding current switch for each bit, and inputs the output current Iout, which is the sum of the currents according to the bit weight, to the current / voltage conversion circuit 103 at the next stage. Analog output V
Convert to out. The analog output Vout is further restored to analog data which is a continuous original waveform by removing high-order harmonics included in the analog output Vout through the low pass filter 104.

[0005]

However, since the conventional D / A converter drives the current switch with a square wave digital signal, the waveform of the analog output is shown, for example, in FIG. 8 (1). Since a jagged staircase waveform composed of such a square wave contains high-order harmonics, the jaggedness is removed by using a low-pass filter.
In order to restore the analog waveform shown in Fig. 2, a high-order filter with excellent high-frequency characteristics is required, and a large amount of high-frequency noise is generated due to the rapid change in the level of the current.
There is a problem that the signal-to-noise ratio (S / N) of the proximity circuit is deteriorated, and therefore there are many problems that increase the cost, such as the need for a noise prevention filter.

The object of the present invention is to solve the above-mentioned problems,
D / A with high resilience of original waveform and suppressed generation of noise
It is to provide a converter.

[0007]

According to the present invention, a digital data input consisting of a plurality of bits is weighted corresponding to each bit, and the sum of analog quantities corresponding to the weights is calculated to convert it into analog data. In the converter, timing signal generating means for processing the sampling clock signal to generate a plurality of timing signals having a predetermined cycle and phase difference, and input digital data are latched for a certain period by the plurality of timing signals. , Corresponding to the divided data and a data dividing means for dividing into odd number data and even number data based on the phase difference,
A pair of data conversion means that includes a plurality of switch circuits that operate according to the bits that configure each data and a current source circuit, and that outputs a total sum of the currents that pass through the switch circuits, and a sine wave signal that is synchronized with the timing signal And a control signal generating unit for adding the outputs of the pair of data converting units, and a current / voltage converting circuit for converting the output of the adding circuit to a voltage level and outputting the voltage level. It is a D / A converter characterized by inputting a signal to the pair of data conversion means to control the conductivity of the switch circuit and amplitude-modulating a current passing through the switch circuit with a sine wave.

[0008]

In the D / A converter according to the present invention, the data dividing means latches the digital data inputted to the data dividing means for a certain period of time by a plurality of timing signals output from the timing signal generating means and having a predetermined cycle and a phase difference. , And odd-numbered data and even-numbered data.

The digital data divided into two groups are input to a pair of data conversion means each having a plurality of switch circuits and a current source circuit, and a current corresponding to the bit weight passes through the switch circuits.

The control signal generating means outputs a sine wave signal synchronized with the timing signal, and controls the conductivity of a plurality of switch circuits provided in the data converting means. As a result, the data conversion means outputs the sum of the currents amplitude-modulated by the sine wave signal when passing through the switch circuit. The sum of both currents is added by an adder circuit, converted into a voltage level by a current / voltage conversion circuit, and analog data is output.

In the present invention, the current passing through the switch circuit at the time of weighting is converted into a smooth sine wave waveform and turned on / off, so that noise generation due to a sudden change in current at the time of switching is suppressed. It Also, because the input data is divided, converted separately, and re-added,
At the time of addition, the harmonics are canceled out, and a good waveform can be obtained.

[0012]

1 is a block diagram showing the configuration of a D / A converter which is an embodiment of the present invention. The D / A converter 1 is
Frequency dividing circuit 2 which is a timing signal generating means, data latch circuit 3 which is a data dividing means, two D / A converters 4a and 4b which are data converting means, and an oscillation circuit 5 which is a control signal generating means. And n-bit digital data D including a block of the adder circuit 6 and the current / voltage conversion circuit 7.
And the sampling clock signal SCK having the cycle Ts are input.

The frequency dividing circuit 2 divides the input sampling clock signal SCK to generate a timing signal TCK having a period of 2Ts, and further, through a logic circuit (not shown), a phase difference of 1/2 period (= Ts). Generate two word latch clock signals WCK1 and WCK2.

The data latch circuit 3 has a bit number n of digital data (hereinafter also referred to as "data") n.
Are realized by the registers 3a and 3b having the input terminals corresponding to. The digital data D is input in parallel to the registers 3a and 3b, and the word latch clock signals WCK1 and WCK2 having a phase difference of 1/2 cycle are stored in the register 3
They are individually input to the clock terminals a and 3b. The data D input according to the sampling cycle Ts is once held by the registers 3a and 3b and then updated at the timing of the word latch clock signal WCK. At this time, the data D is odd-numbered data Dod due to the phase difference Ts between the word latch clock signals WCK1 and WCK2.
d (odd = 1, 3, 5, ...) And even-numbered data De
ven (even = 2, 4, 6, ...) And the odd number data Dodd is output from the register 3a,
The even-numbered data Deven is output from the register 3b.

Odd number data Dodd and even number data D
The even is individually input to the D / A conversion units 4a and 4b. The pair of D / A converters 4a and 4b have the same configuration and include an R-2R ladder resistor network (not shown) and a current switch including a plurality of current source circuits and switch circuits, and each bit of data Dodd and Deven. The switch circuit is activated by the output current I1, which is the sum of the currents passing through the individual switch circuits, on the lines L1 and L2.
A level corresponding to the value of I2 is derived. Each individual current switch is realized by a semiconductor switching element.

The oscillation circuit 5 is realized by, for example, a PLL circuit, and the D / A conversion section 4a, which corresponds to the pair of sine wave signals S and S synchronized with the timing signal TCK, is provided.
4b to control the conductivity of the current switch.
As a result, the output currents I1 and I2 have sinusoidal waveforms having mutually opposite phases.

It should be noted in the present invention that, as described above, the input digital data D is divided into two data Dodd and Deven at a period twice the sampling period, and D / A conversion is performed individually. After that, the addition is performed to obtain the total output current Iout, and the oscillation circuit 5
Are provided, and the conductivity of the current switches in the D / A converters 4a and 4b is controlled by the sine wave signals S and S that are output, and the current passing through the current switches is amplitude-modulated. However, these will be described later.

The levels corresponding to the output currents I1 and I2 are
The level corresponding to the value of the total output current Iout is added by the adder circuit 6 and converted into a voltage via the current / voltage conversion circuit 7, and the analog output voltage Vout is output. By passing the output voltage Vout through a low-pass filter (not shown), the analog waveform of the original signal is restored.

Output current I from the D / A converters 4a and 4b
Since 1 and I2 are output in mutually opposite phases, the pulsating current components included in the output currents I1 and I2 are canceled during addition, and do not appear in the output. Further, since the divided data have a phase difference of ½ cycle from each other, even if “1” is continuously input to the digital data D, the output of the adding circuit 6 is kept at “1”. . Since the total output current Iout has a smooth sine wave waveform and does not have a stepwise waveform as in the conventional example, a high-order filter is unnecessary and the filter configuration is simplified.

Further, the current switches in the D / A converters 4a and 4b repeat ON / OFF of the smooth sinusoidal current, and there is no sudden change in the current. Therefore, the current O
The generation of high frequency noise associated with N / OFF is significantly reduced. Since each current switch is controlled by a sine wave at a cycle twice the original sampling cycle Ts, high slew rate and high speed such as shortening of settling time are not required, and the circuit cost is reduced. It has many advantages such as reduction.

FIG. 2 is a circuit diagram showing the configuration of a D / A converter which is an embodiment of the present invention. In FIG. 2, the above-mentioned FIG.
The same reference numerals are attached to the portions corresponding to.

Next, each block will be described. Referring also to FIG. 1, the frequency dividing circuit 2 is formed of a D-type flip-flop circuit (hereinafter referred to as “D-FF circuit”) 2a and two AND gates 2b and 2c. The sampling clock signal CLK having the cycle Ts is input to the clock terminal CK of the D-FF circuit 2a and also to one of the terminals of the AND gates 2b and 2c in negative logic. D-
The data terminal D of the FF circuit 2a is connected to the inverting output terminal / bar Q, and further connected to the other input terminals of the AND gates 2b and 2c. The output of the D-FF circuit 2a and the bar Q are positive logic in the AND gate 2b, and the AND gate 2c.
Is input in negative logic.

The sampling clock signal CLK is DF
The frequency is divided by the F circuit 2a, and a timing signal TCK having a doubled period 2Ts is output.
The D gate 2c outputs a first word latch clock signal WCK1 and a second word latch clock signal WCK2 having a period of 2Ts. First word clock signal WC
K1 and the second word clock signal WCK2 are 1 /
With a phase difference of 2 cycles (= Ts), the first word latch clock signal WCK1 is input to the clock terminal of the first register 3a of the data latch circuit 3, and the second word latch clock signal WCK2 is input to the second register 3b. Input to clock terminal.

The data latch circuit 3 is formed of two registers 3a and 3b having input terminals corresponding to the number n of bits of the input digital data D. The digital data D is input in parallel to the registers 3a and 3b and is supplied to the clock terminal CK. A word latch clock signal (hereinafter, also simply referred to as "clock signal") WCK
1 and WCK2 are individually latched at the falling timing, and the data is updated by the next word latch clock signal WCK. As described above, the clock signals WCK1, WC
Since K2 is given a phase difference of ½ cycle (= Ts), the data D is alternately latched at the sampling cycle Ts by the registers 3a and 3b, whereby the odd-numbered data Dodd and the even-numbered data Dodd. No. Data Dev
It is divided into n and sequentially input to the D / A converters 4a and 4b in the next stage.

Since the two D / A converters 4a and 4b have the same structure, the D / A converter 4a to which the odd number data Dodd is input will be described. The D / A conversion unit 4a includes a plurality of current switches CS (n- corresponding to the bit number n of the data D.
1), CS (n-2), ..., CS1, CS0 (reference numeral CS is used for generic name) and R-2R ladder resistance network RN (hereinafter referred to as “ladder resistance network”), and includes a current switch. A voltage -Vcc is applied to the other end of CS.

The plurality of current switches CS include switch circuits A (n-1), A (n-2), ..., A0 (the reference numeral A is used for generic name) and a current source circuit B (n-.
1), B (n-2), ..., B0 (reference numeral B is used for generic name), and each switch circuit A
Is driven by the bit of the odd-numbered data Dodd to be input, and when the bit is "1", the current source circuit B and the ladder resistance network RN are connected and a current flows corresponding to the weight of the bit. Each current source circuit B is a transistor Tr.
And a transistor Tr formed by a series circuit of a resistor Re
The sine wave signal S output from the oscillation circuit 5 is commonly applied to the base of the line through the line L3. As a result, the conductivity of the transistor Tr changes according to the change in the waveform of the sine wave signal S, and the individual currents flowing through the ladder resistance network RN follow the waveform of the sine wave signal S. From the line L1, Output current I which is the sum of them
A level corresponding to 1 is derived. The other even-numbered data Deven is input to the D / A conversion unit 4b except that the output current I2 derived from the line L2 is in the opposite phase to the output current I1 due to the sine wave signal / bar S. , And others are the same as the D / A converter 4a.

The oscillator circuit 5 includes a phase comparator circuit 5a and a VC.
O (voltage controlled oscillator) 5b, Schmitt circuit 5c,
A PLL including an inverter 5d for inverting the output S
(Face-locked loop) circuit. The output S of the VCO 5b is fed back to the terminal Pa of the phase comparison circuit 5b via the Schmitt circuit 5c, and the timing signal TCK is input to the terminal Pb. Since the output of the VCO 5b is binarized by the Schmitt circuit 5c with the zero cross point as a reference, the oscillating circuit 5 outputs the sine wave signal S which is completely synchronized with the rising and falling of the timing signal TCK. The sine wave signal S and the opposite phase sine wave signal / bar S inverted via the inverter 5d are connected to the current source circuit B of the D / A converters 4a and 4b via the lines L3 and L4. Applied to the base of the transistor Tr, the conductivity of the transistor Tr is controlled. In this embodiment, the sine wave signal S is generated using the PLL circuit as described above, but the sine wave signal S is not limited to the sine wave and may be, for example, a triangular wave. This simplifies the circuit configuration. However, the accuracy is slightly lower than that when the sine wave signal S is used.

The output currents I1 and I2 are added by the adder circuit 6, and the level corresponding to the sum current Iout (= I1 + I2) is input to the current / voltage conversion circuit 7. Current /
The voltage conversion circuit 7 is realized by an operational amplifier and has a feedback resistor Rf connected between its input and output terminals.
An analog output voltage Vout = Rf · Iout, which is the product of the sum current Iout and the feedback resistance Rf, is output.

FIG. 3 shows the D / A converters 4a and 4 of this embodiment.
It is a circuit diagram which shows the structure of the current switch used for b. The current switch CS includes transistors Tr1 and Tr2.
Differential amplifier circuit a, transistor Tr5 and resistor R
The current source circuit b is formed by the grounded-emitter circuit of e and the level shift circuit c is formed by the transistors Tr3 and Tr4. One current switch CS corresponds to one bit of the data D. Referring also to FIG. 2, one transistor Tr2 of the differential amplifier circuit a corresponds to the switch circuit A of FIG. 2, and the current source circuit b corresponds to the current source circuit B of FIG. The collector of one transistor Tr1 of the differential amplifier circuit a is connected to the ground line g, and the collector of the other transistor Tr2 is connected to the ground line g via the ladder resistance network RN.

The level shift circuit c includes a transistor Tr.
3 and a resistor R2, and a transistor Tr4 and a resistor R3 in a series circuit, and a voltage Vcc and a negative voltage -Vc are provided across the series circuit.
A voltage of 2 × Vcc is applied by c. The base of the lower transistor Tr4 of the level shift circuit c is given a base potential Vb4 which is almost equal to the junction voltage by the diode Dd2. On the other hand, the upper transistor T
The base of r3 is connected to the voltage Vc via the pull-up resistor R1.
c is applied, and 1 is applied through the diode Dd1.
Bit digital data D is input.

Since the base voltage Vb3 of the transistor Tr3 rises / falls according to "0" and "1" of the data D, the collector potential of the transistor Tr4, and thus the base potential Vb1 of one transistor Tr1 of the differential amplifier circuit a. Be shifted. When the data D is "0", the base potential Vb1 of the transistor Tr1 rises and the transistor Tr2 is in the OFF state. On the contrary, when the data D is "1", the base potential Vb1 of the transistor Tr1 falls and the transistor Tr2 becomes conductive. . In this way, the transistor Tr2 is ON / OFF controlled by the level of the data D, and functions as a current switch circuit.

The conductivity of the transistor Tr5 of the current source circuit b connected in series with the transistor Tr2 is controlled by the amplitude of the sine wave signal S input to the base,
Output current i flowing in by turning on the transistor Tr2
The current value of is 0 when the level of the sine wave signal S is minimum,
It increases as the amplitude of the sine wave signal S increases, reaches a maximum value at the maximum, and then returns to 0 again. Therefore, the output current i
Has a sinusoidal waveform having a period of 2Ts as one cycle, and the current accumulation during the period corresponds to one bit of the data D.

FIG. 4 shows the D / A converters 4a and 4 of this embodiment.
It is a waveform diagram of output currents I1 and I2 derived from b.
FIG. 4 (1) shows an example of the waveform of the output current I1, and the output currents I1-1, I corresponding to the odd-numbered data D1, D3, D5, ... For each cycle 2Ts which is twice the sampling cycle Ts.
1-3, I1-5, ... Are sequentially output. FIG. 4B shows an example of the waveform of the output current I2, which is even-numbered data D2, D4, D.
Output currents I2-2, I2-4, I2-corresponding to 6, ...
6, ... are sequentially output.

In each of the output currents I1 and I2, the weight of each bit of the quantized data D is a sine wave signal S,
It can be regarded as a sinusoidal pulsating current modulated by the bar S and further weighted and added by the ladder resistance network RN,
Since these output currents I1 and I2 are deviated from each other by the sampling period Ts, they are added and synthesized by the adder circuit 6. As shown in FIG. 4 (3), the waveform corresponding to the total output current Iout obtained as a result is such that the data D1, D2, D3, ... The pulsating phase components cancel each other out and do not appear in the output.

Therefore, the analog output Vout output from the current / voltage conversion circuit 7 has a smooth waveform which does not include a stepwise change, as shown in FIG. 4 (4). The analog output Vout is restored to the original waveform by a low-pass filter (not shown), but since it is already a smooth sine wave signal, the filter does not need to have high high-frequency characteristics. The switch circuit A is
Repeated smooth ON / OFF of the sine wave current, and because the data D is transferred at the zero level point,
There is no abrupt change in level, noise generation is suppressed as much as possible, and the signal-to-noise ratio (S / N) of the circuit can be significantly improved.

FIG. 5 is a timing chart showing the operation of each part of this embodiment. In FIG. 5, portions corresponding to those in FIG. 2 above are designated by the same reference numerals, and description will be given with reference to FIG. 2 as well. FIG. 5A shows the waveform of the sampling clock signal CLK input to the frequency dividing circuit 2.
Based on the cycle Ts of the sampling clock signal CLK, the digital data D1, D2 shown in FIG.
D3, ... Are sequentially input.

The sampling clock signal CLK is frequency-divided by the D-FF circuit 2a of the frequency dividing circuit 2 as shown in FIG.
A timing clock signal TCK having a doubled cycle 2Ts shown in (3) is generated and input to the oscillation circuit 5 and the AND gates 2b and 2c. By the logical product of the sampling clock signal CLK and the timing signal TCK, A
From the ND gates 2b and 2c, the first word latch clock signal WCK1 shown in FIGS. 5 (4) and (6) and the second word latch clock signal WCK2 having a phase difference of 1/2 cycle (= Ts) from the first word latch clock signal WCK1. Are generated, the first word latch clock signal WCK1 is input to the register 3a of FIG. 2, and the second word latch clock signal WCK2 is input to the register 3b.

The digital data D is stored in the registers 3a, 3
Since it is input in parallel to b, as shown in FIG. 5 (5), the odd-numbered data D1, D3, ... Are latched by the register 3a for a period of 2Ts at the rising of the first word latch clock signal WCK1. And then odd number data D
First D / A converter 4a provided corresponding to odd
Are input sequentially. Further, as shown in FIG. 5 (7), even-numbered data D2, D4, ... Are latched by the register 3b for a period of 2Ts at the rising edge of the second word latch clock signal WCK2, and then even-numbered data D2, D4 ,. D2, D4, ... Are also sequentially input to the second D / A conversion unit 4b.

FIG. 5 (8) shows the waveform of the sine wave signal S output from the oscillator circuit 5, and FIG. 5 (9) shows the waveform of the sine wave signal S of the opposite phase. Sine wave signal S, bar S
Both have their zero level points synchronized with the rising and falling edges of the timing signal TCK, and control the output currents Iodd and Ieven during a period of 2Ts, which is twice the sampling period Ts. Therefore, D /
The output current immediately after the A conversion is already a smooth current change, and when added by the adder circuit 6, the pulsating current arranged according to the original data according to the sampling period Ts as shown in FIG. Since the waveform becomes a waveform and the AC component of the opposite phase is canceled and not output at the time of addition, it is possible to realize the D / A converter in which the filtering process is simplified and the noise is less generated. Further, since the switching element used for the current switch is not required to have a high slew rate or a short settling time, the cost can be reduced also in this respect.

[0040]

As described above, in the D / A converter according to the present invention, the input digital data is divided into the odd number data and the even number data by the data dividing means, and the divided digital data is obtained. , A plurality of switch circuits corresponding to the number of bits and a current switch provided with a current switch circuit are separately input to a pair of data conversion means, and a current corresponding to the weight of each bit is applied to the switch circuit. When the weighting is performed, the conductivity of the switch circuit is controlled by the sine wave signal output from the control signal generating means. As a result, the current flowing through the switch circuit becomes a smooth sinusoidal waveform whose amplitude is modulated by the sinusoidal signal, and is turned on / off.
As a result, the generation of noise due to a sudden change in current at the time of switching is suppressed, the S / N ratio of the proximity circuit is improved, and a noise prevention filter is not required, so that the cost can be reduced.

Further, since the input data is divided and converted separately and the sum of the converted current values is added by the adder circuit, the added data is smooth sine as described above. Since the harmonic components included in the data that are waves are canceled during the addition, a high-quality waveform can be obtained. Therefore, it does not require a high-order filter as in the prior art, and has a great industrial effect such as a simplified structure.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a D / A converter that is an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a D / A converter shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a current switch used in the circuit shown in FIG.

FIG. 4 is a timing chart showing a waveform of an output current of the circuit shown in FIG.

5 is a waveform chart showing the operation of each part of the circuit shown in FIG.

FIG. 6 is a circuit diagram showing a configuration of a ladder resistance network used in a D / A converter.

FIG. 7 is a block diagram showing a configuration of a D / A converter according to a conventional technique.

FIG. 8 is a waveform diagram showing an output waveform of a conventional D / A converter.

[Explanation of symbols]

 1 D / A converter 2 Dividing circuit 3 Data latch circuit 3a, 3b Register 4 D / A converter 5 Oscillation circuit 6 Adder circuit 7 Current / voltage conversion circuit A (n-1) to A0 switch circuit B (n- 1) to B0 Current source circuit CLK Sampling clock signal CS Current switch D Digital data Deven Even number digital data Dodd Odd number digital data I1, I2 Output current Iout Total output current S Sine wave signal TCK Timing signal WCK1, WCK2 Word latch clock signal

Claims (1)

[Claims] 1. A D / which weights a digital data input consisting of a plurality of bits corresponding to each bit, obtains a sum of analog amounts corresponding to the weights, and converts the sum into analog data.
In the A converter, timing signal generating means for processing a sampling clock signal to generate a plurality of timing signals having a predetermined cycle and phase difference, and input digital data are latched for a certain period by the plurality of timing signals. And based on that phase difference,
Data division means for dividing into odd-numbered data and even-numbered data, a plurality of switch circuits corresponding to the divided data and operated by bits constituting each data, and a current source circuit, and a switch A pair of data conversion means for outputting the sum of the currents passing through the circuit, a control signal generation means for generating and outputting a sine wave signal synchronized with the timing signal, and an addition for adding the outputs of the pair of data conversion means. Circuit and current output by converting the output of the adder circuit to voltage level /
A voltage conversion circuit, wherein the sine wave signal is input to the pair of data conversion means, the conductivity of the switch circuit is controlled, and a current passing through the switch circuit is amplitude-modulated by a sine wave. D / A converter.