JPH0730593A - Modulated wave communication method - Google Patents

Abstract

PURPOSE:To reduce radiation noise from a transmission line by eliminating an undesired harmonic component when a cable of electric conductors is used as the transmission line. CONSTITUTION:When a reference signal is generated from a sine wave oscillator 1, an analog PLL circuit 2 outputs sine wave signals whose frequencies are f, 2f in response to the reference signal. In this case, a CPU 7 sends transmission data 14 and synchronization transmission data 15 are outputted from a latch 8 in response thereto and a signal whose frequency differs from a logic of the synchronization transmission data 15 to be 0 or 1 is sent to the transmission line 21. A receiver side converts the signal into a signal of a logic level and a delay circuit 18 delays the signal by 1/2 bit length and the result is exclusively ORed and a received NRZ signal is demodulated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a modulated wave communication method, and in particular, a transmitting circuit and a receiving circuit are connected via a transmission line to transmit and receive a modulated wave signal between the transmitting circuit and the receiving circuit. The present invention relates to a modulated wave communication method suitable for.

[0002]

2. Description of the Related Art Conventionally, in this type of communication system, a method of transmitting / receiving a binary logic level signal using an electric conductor as a communication medium or a method of transmitting / receiving an optical modulation signal using an optical fiber cable as a communication medium. Has been adopted.

[0003]

However, in the above-mentioned conventional method for transmitting / receiving the signal of the binary logic level, the filter for removing unnecessary harmonic components becomes multistage when the transmission rate becomes high, and the communication equipment is expensive. There is a drawback that Further, in the communication method using the optical fiber cable, there is a problem in that the optical fiber cable is currently more expensive and lacks flexibility as compared with the electric conductor cable.

SUMMARY OF THE INVENTION The present invention is intended to solve such a conventional problem, and an object thereof is to provide a modulated wave communication method capable of reducing radiation noise even if an electric conductor is used for a transmission line. It is a thing.

[0005]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides transmission information generated by binary logic with different frequencies depending on whether the logic is 0 or 1 and logic 0 and logic 1. A modulated wave signal is generated by converting it into an AC signal whose period is an integral multiple of one-half wavelength, and this modulated wave signal is transmitted from the transmission side to the transmission path, and this modulated wave signal is received via the transmission path. On the receiving side, the modulated wave communication method is adopted in which the received modulated wave signal is demodulated into binary logic reception information according to the difference in the frequency of the signal.

When applying the above-mentioned modulated wave communication method, it is desirable to use a signal approximate to a sine wave as an AC signal.

[0007]

Therefore, according to the present invention, when the modulation wave signal is transmitted from the transmission side to the reception side, the transmission waveform of the modulation wave signal to be transmitted to the transmission line is a combination of sine wave signals of two frequencies. Even if an electric conductor cable is used for the transmission path, unnecessary harmonic components can be removed with a simple filter to reduce radiation noise.

[0008]

1 is a block diagram showing a transmitting side of a first embodiment of the present invention, and FIG. 2 is a timing chart showing signal waveforms of respective parts shown in FIG. In FIG. 1, on the transmission side, a sine wave oscillator 1, an analog PLL circuit 2, analog switches 3 and 4, an inverter 5, a waveform shaping circuit 6, a CPU 7, and D.
A latch 8 of a type, a low-pass filter 9, and an amplifier 10 are provided, and the output side of the amplifier 10 is connected to a transmission line composed of an electric conductor.

The sine wave oscillator 1 is configured to output a sine wave reference signal to the analog PLL circuit 2. When the analog PLL circuit 2 receives the reference signal from the sine wave oscillator 1, it outputs two types of synchronized sine wave signals (in this embodiment, frequencies f and 2f) from the reference signal. . That is, the analog PLL circuit 2 outputs a sine wave signal of frequency f to the analog switch 3 and the waveform shaping circuit 6, and the analog switch 4 outputs the frequency 2f.
The sine wave signal of is output. The sine wave signal input to the waveform shaping circuit 6 is waveform-shaped and then input to the INT terminal of the CPU 7 and the latch 8 as the timing signal 13. When the CPU 7 detects the falling edge of the timing signal 13 input to the INT terminal, it sets the transmission data 14 to the DT terminal at the logical level. This transmission data 14
Is input to the latch 8, the latch 8 operates at the rising edge to output the synchronous transmission data 15 to the analog switch 3 and the analog switch 4 via the inverter 5. The analog switch 3 is turned on by a signal input via the inverter 5 when the logic of the synchronous transmission data 15 is 1. At this time, the analog switch 4 is turned off. That is, the analog switches 3 and 4 are alternately turned on and off according to the logic of the synchronous transmission data 15. When the signal from the analog switch 3 or 4 is input to the low-pass filter 9, the low-pass filter 9 passes the signal of frequency 2f and outputs a signal from which unnecessary harmonic components are removed to the amplifier 10. ing.

On the other hand, the receiving side is provided with a comparator 17, a delay circuit 18, an EXOR gate 19, and a CPU 20, and the input side of the comparator 17 is connected to the transmitting side amplifier 10 via a transmission line 21. The comparator 17 is configured to convert an analog signal input from the transmission line 21 into a logical signal.
The logic signal output from the input terminal is input to one input terminal of the EXOR gate 19 via the delay circuit 18 as the delay circuit output 23 and directly input to the other input terminal of the EXOR gate 19 as the comparator output 22. Has become. From the EXOR gate 19, the differential detection output (reception NRZ) according to the exclusive OR of the input signals is received.
Signal) 24 is output, and this signal is input to the CPU 20 as received data. Then, the delay circuit 18 delays the output signal 22 of the comparator 17 by a half bit length of the data (in this embodiment, a half wavelength of the frequency f).

Next, the operation of the first embodiment will be described with reference to FIGS. 2 and 4. First, when the reference signal is output from the sine wave generator 1 to the analog PLL circuit 2, the PLL circuit 2 outputs two types of synchronized sine wave signals 11 and 12 of the frequency f and the frequency 2f to the analog switches 3, 4 and. It is output to the waveform shaping circuit 6. When the signal 11 having the frequency f is input to the waveform shaping circuit 6, the timing signal 13 is output from the waveform shaping circuit 6 to the INT terminal of the CPU 7 and the clock terminal of the D type latch 8. At this time C
PU7 detects D when falling edge of INT terminal
The transmission data 14 is output to the T terminal at a logical level. When the transmission data 14 is input to the latch 8, the latch 8 synchronizes the transmission data 14 with the sine wave signals 11 and 12 and outputs the synchronous transmission data 15. When the synchronous transmission data 15 is input to the analog switch 3 via the inverter 5 and directly to the analog switch 4, the analog switch 3 is turned off when the logic of the synchronous transmission data 15 is 1, and the analog switch 4 is turned on. Turn off. Conversely, when the logic of the synchronous transmission data 15 is 0, the analog switch 3 is turned off and the analog switch 4 is turned on. That is,
Frequency f, corresponding to logic 1 and 0 of the synchronous transmission data 15,
The 2f sine wave signal is combined, and the output signal 16 is output to the low pass filter 9 as a modulation wave signal. This signal is amplified by the amplifier 10 after removing unnecessary harmonic components by the low-pass filter 9 and sent to the transmission line.

When the modulation wave signal from the transmission side is input to the reception side comparator 17 via the transmission line 21, the modulation wave signal is converted into a logic signal by the comparator 17,
It becomes the comparator output 22. The comparator output 22 is output to the EXOR gate 19 as a delay circuit output 23 delayed by one-half bit of the data in the delay circuit 18. On the other hand, the comparator output 22 is directly input to the EXOR gate 19. The exclusive OR operation of the input signals input to the EXOR gate 19 is the EXOR gate 1
9. The EXOR gate 19 outputs the differential detection output 24 according to the exclusive OR operation. That is, the gate 19 outputs the differential detection output 24 from the received modulated wave signal as binary logic reception information corresponding to the frequency difference of the signal. Then, this signal is input to the CPU 20 as a reception NRZ signal.

As described above, according to the first embodiment, since the output signal to the transmission line 21 is a combination of two kinds of synchronized sine wave signals, the modulated wave signal is transmitted through the transmission line 21. It is possible to reduce the superposition of radiation noise on the modulated wave signal.

FIG. 5 is a block diagram showing the transmitting side of the second embodiment of the present invention, and FIG. 6 is a timing chart showing the signal waveform of each part shown in FIG. In this embodiment, a CPU 7 ', a D type latch 8', a pattern generator 26, a digital / analog (D / A) converter 27, a low pass filter 9, an amplifier 10 and an octal counter 25 are provided on the transmission side. The output side of the amplifier 10 is connected to the transmission line 21.

The CPU 7'uses an octal counter 2 at the INT terminal.
When the carry output 31 is input from 5, after detecting the rising edge of the carry output 31, DT0,
2-bit transmission data 28 is output from the DT1 terminal. The latch 8'operates at the rising edge of the clock and outputs the latch output 29 to the pattern generator 26 according to the transmission data 28. The octal counter 25 outputs a 3-bit counter output 30 to the pattern generator 26 and outputs a count value of 7
At this time, the L level carry output 31 is outputted to the CPU 7'and the latch 8. Pattern generator 26
Outputs 3-bit data 32 synchronized with the count clock of the octal counter 25 in response to a 5-bit input signal output from the latch 8'and the octal counter 25. The digital / analog converter 27 converts the input data into an analog signal and outputs this signal as the staircase wave data 33 to the low pass filter 9. The data input to the low-pass filter 9 is converted into a signal having a smooth waveform and then amplified by the amplifier 10,
It is output to the transmission line 21.

Next, the operation of the second embodiment will be described with reference to FIGS. First, when the carry output 31 from the octal counter 25 is input to the INT terminal of the CPU 7 ', in response to the rising edge of the carry output 31, 2-bit data corresponding to the transmission data is sent from the CPU 7 to the DT0 terminal and the DT1 terminal. Is output as a signal 28 from the. At this time, the latch 8'latches the signal 28 in response to the next rising edge of the carry output 31, and outputs the latch output 29 to the pattern generator 26. This 8
The advance counter 25 is continuously counting, and
A bit count output 30 is output, and a carry output 31 is generated when the count value reaches 7.
When the latch output 29 and the count output 30 are input to the pattern generator 26, the pattern data 32 is output according to the input data as shown in (Table 1) below.

[0017]

[Table 1]

In this case, when the data as shown in FIG. 6 is input, the data of the pattern 1 is first generated among the four types of patterns shown in FIG. 7, and then the data of the pattern 4 is generated. After that, the data of pattern 2 will be generated. When this data is input to the digital / analog converter 27, the digital / analog converter 27 outputs a signal obtained by converting the pattern data 32 into the staircase wave data 33. When this signal is input to the low pass filter 9, the low pass filter 9 converts the staircase wave data 33 into a smooth waveform, and the amplifier 1
After being amplified by 0, it is output to the transmission line 21.

The signal output from the amplifier 10 is transmitted through the transmission line 2
It is input to the receiving side comparator 17 shown in FIG. In this case, by changing the delay amount of the delay circuit 18 to 1 bit, the CPU 20 demodulates the received information into binary logic.

[0020]

As is apparent from the above embodiment, the present invention is such that, when transmitting a modulation wave signal from the transmitting side, the transmission waveform of the modulation wave signal is a combination of two sinusoidal wave signals having different frequencies. Therefore, even if the transmission line is composed of an electric conductor, unnecessary harmonic components can be removed by a simple filter, and it is possible to reduce the superposition of radiation noise on the transmission signal. Can contribute to construction.

[Brief description of drawings]

FIG. 1 is a block diagram showing a transmitting side of a modulated wave communication method according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing signal waveforms of the same embodiment.

FIG. 3 is a block diagram showing a receiving side of the embodiment.

FIG. 4 is a timing chart showing signal waveforms of the same embodiment.

FIG. 5 is a block diagram showing a transmitting side of a modulated wave communication method according to a second embodiment of the present invention.

FIG. 6 is a timing chart showing signal waveforms of the same embodiment.

FIG. 7 is an explanatory diagram of pattern data of the same embodiment.

[Explanation of symbols]

 1 sine wave oscillator 2 analog PLL circuit 3,4 analog switch 5 inverter 6 waveform shaping circuit 7 CPU 8 latch 9 low pass filter 10 amplifier 17 comparator 18 delay circuit 19 EXOR gate 20 CPU

Claims (2)

[Claims] 1. A transmission information generated by a binary logic is converted into an AC signal in which the logic has different frequencies depending on 0 and 1 and the period of the logic 0 and the logic 1 is an integral multiple of a half wavelength. To generate a modulated wave signal, transmit this modulated wave signal from the transmission side to the transmission line, and receive this modulated wave signal on the reception side via the transmission line. A modulated wave communication method for demodulating into binary logic reception information according to a difference. 2. The modulated wave communication method according to claim 1, wherein a signal approximate to a sine wave is used as the AC signal.