JPH0730603A - Detection circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] A low-pass filter (LPF) of a detection circuit that performs differential detection is digitized so that a detection circuit for a signal that is phase-modulated well can be configured. An output of a detection means by a 1-symbol delay of an input signal is supplied to a first level determination means via a first LPF, and the phase of the level determination output is determined by the first phase determination means. , The output of the detection means due to the delay of a plurality of symbols of the input signal is supplied to the second level determination means via the second LPF, and the phase of the level determination output is set to the second phase determination output.
Phase determination means, the output level of the detection means by one symbol delay is determined by the third level determination means, and the phase of the level determination output is determined by the third phase determination means. In the detection circuit provided with the detection means for detecting the frequency shift of the input signal from the output of the phase determination means of No. 3, a digital filter by digital arithmetic processing is used as each LPF.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a π / 4 shift QPSK.
The present invention relates to a detection circuit suitable for application to a circuit that detects a phase modulation wave such as a modulation wave.

[0002]

2. Description of the Related Art In a communication system such as a digital cordless telephone, there has been proposed a communication method that transmits phase-modulated digital data such as π / 4 shift DQPSK modulation (π / 4 shift / Differential / QPSK modulation). There is.

In the π / 4 shift DQPSK modulation, the differentiated two series of data are used as phase information by complex operation, and the phase information is combined into a modulated signal. That is, for example, as shown in FIG. 7, two series of data (I, Q) is converted into phase data θ _k by a four-value phase converter and transmitted. Such a π / 4 shift DQP
Performing SK modulation enables efficient transmission of digital data.

In order to detect such a π / 4 shift DQPSK modulated wave, it is necessary to set the frequency of the signal input to the detection circuit to a predetermined frequency. As described above, as the AFC (automatic frequency control circuit) for automatically controlling the frequency, the tank input / output phase difference detection type AFC, the baseband beat signal detection type AFC, or the reference signal comparison type AF is used.
C and the like are known.

In these conventional devices, the oscillation frequency of the local oscillator used to generate the intermediate frequency is controlled according to the frequency error so that the intermediate frequency (IF) becomes a preset predetermined frequency. I am trying.

Since the conventional device controls the frequency of the local oscillator in the IF signal generation stage as described above, noise is likely to be superposed on the control signal line for controlling the local oscillator and the SN ratio is deteriorated. There was a problem to do.

Therefore, the present applicant has previously proposed a detection circuit capable of suppressing the deterioration of the SN ratio. This detection circuit is configured as shown in FIG. In FIG. 4, reference numeral 1 denotes an intermediate frequency amplifier (IF amplifier). The IF amplifier 1 saturates and amplifies the input intermediate frequency (IF) signal and outputs it to the differential detection circuits 41 and 42. . The differential detection circuit 41 delays the input signal by one symbol and outputs the delayed signal, and an exclusive OR circuit (Ex) that calculates an exclusive OR of the signal delayed by the delay circuit 2 and the undelayed signal. -OR circuit) 3,
The low pass filter 4 removes unnecessary high frequency components of the output of the Ex-OR circuit 3. The differential detection circuit 41 delay-detects the I component.

On the other hand, the differential detection circuit 42 calculates the exclusive OR of the delay circuit 8 which delays the input signal by one symbol and outputs it, the signal delayed by the delay circuit 8 and the signal which is not delayed. Ex-OR circuit 9 and a low-pass filter 10 that removes unnecessary high-frequency components of the output of the Ex-OR circuit 9. This differential detection circuit 42
Causes the Q component to be delayed and detected.

The output of the delay circuit 2 is also supplied to the delay circuit 5, further delayed by one symbol, and then Ex-OR.
It is adapted to be supplied to the circuit 6. The Ex-OR circuit 6 receives the signal input from the delay circuit 5 and the IF amplifier 1
The exclusive OR with the more input signal is calculated and output to the low pass filter 7. This delay circuit 2, 5, E
The x-OR circuit 6 and the low-pass filter 7 constitute a delay detection circuit 43 that delays the input signal by two symbols and delay-detects the I component.

Similarly, a delay circuit 11 is connected to the subsequent stage of the delay circuit 8 so that the signal delayed by one symbol by the delay circuit 11 is supplied to the Ex-OR circuit 12. The Ex-OR circuit 12 calculates the exclusive OR of the signal input from the delay circuit 11 and the signal input from the IF amplifier 1, and outputs it to the low pass filter 13. The delay circuits 8 and 11, the Ex-OR circuit 12, and the low-pass filter 13 constitute a delay detection circuit 44 that delays the input signal by two symbols and delay-detects the Q component.

The output of the low-pass filter 4 is supplied to a ternary decision circuit 15 so that its level is ternary decided. Then, the determination result is supplied to the phase difference determination circuit 25. Further, the output of the low-pass filter 10 is supplied to the ternary judgment circuit 18, the ternary judgment is made, and the judgment result is supplied to the phase difference judgment circuit 25. The output of the low-pass filter 7 is supplied to the ternary judgment circuit 16 and ternary judgment is made, and the judgment result is the phase difference judgment circuit 24.
Is supplied to. The output of the low pass filter 13 is
It is supplied to the three-value determination circuit 19 and is subjected to three-value determination, and the determination result is supplied to the phase difference determination circuit 24. further,
The output of the low-pass filter 4 is supplied to the binary determination circuit 14, and after the binary determination, the determination result is supplied to the phase difference determination circuit 20. In addition, the low-pass filter 10
Is output to the binary determination circuit 17, and after the binary determination, the determination result is supplied to the phase difference determination circuit 20.

The output of the phase difference judgment circuit 20 is the adder 22.
To the adder 22, after being delayed by one symbol by the 1-symbol delay circuit 21,
The signal supplied from the phase difference judging circuit 20 is added. Then, the output of the adder 22 is supplied to the subtractor 23, is subtracted from the output of the phase difference determination circuit 24, and the output of the subtractor 23 is supplied to the subtraction circuit 26. The integration 26 is adapted to integrate the signals supplied from the subtractor 23 in synchronization with the integration timing signal supplied from a CPU (not shown) or the like.

The delay circuit 21, the adder 22 and the subtractor 2
3 and the integrating circuit 26 constitute a detecting circuit 45 for detecting a frequency shift.

The preamble detection circuit 29 detects the preamble from the output of the phase difference determination circuit 24, supplies the detection signal to the integration circuit 26 as a reset signal, and also serves as a high-speed symbol synchronization signal for resetting the PLL, which is not shown. It is adapted to be supplied to the PLL.
A synchronization establishment signal output by the CPU is supplied to the preamble detection circuit 29 as a disable signal.

The correction circuit 27 generates a correction signal corresponding to the output of the phase difference determination circuit 25 and the output of the integration circuit 26,
It is output to the adder 28. The adder 28 adds the output of the phase difference determination circuit 25 and the output of the correction circuit 27 and outputs the result to the phase data conversion circuit 31. The phase data conversion circuit 31 converts the signal supplied from the adder 28 into demodulated data and outputs the demodulated data to a CPU (not shown).

The output of the integrating circuit 26 is supplied to a latch circuit 30 and, after being latched, is supplied to a circuit (not shown) as a signal representing a frequency shift and also to a control circuit 32. . The control circuit 32 controls the delay times of the delay circuits 2, 5, 8 and 11 in accordance with the output of the latch circuit 30.

Next, the operation will be described. The signal saturated and amplified by the IF amplifier 1 is input by the delay detection circuit 41 including the 1-symbol circuit 2, the Ex-OR circuit 3, and the low-pass filter 4, and the I component is delay-detected. The signal output from the low-pass filter 4 is
It is supplied to the three-value determination circuit 15 and is subjected to three-value determination.

As shown in FIG.
Level I greater than 0 level as a reference level₁When,
Level I less than 0 level₂As a threshold
It Then, the signal input from the low-pass filter 4
Level and this level I₁, I₂Compare with and low pass
The level of the signal input from the filter 4 is the level I ₁
H, I when larger₁Smaller and I₂Greater than
When M comes, then I ₂Three value judgment of L when smaller
The result is converted into 2-bit data and is sent to the phase difference determination circuit 25.
Output.

On the other hand, a delay detection circuit 42 including a 1-symbol delay circuit 8, an Ex-OR circuit 9 and a low-pass filter 10.
The signal of the Q component, which is delay-detected by the
It is supplied to 8 and a three-value judgment is made.

That is, as shown in FIG. 5, the ternary judgment circuit 18 has a level Q larger than 0 level as a reference level.
₁ and a level Q ₂ smaller than 0 level are used as threshold values, and the level of the signal input from the low-pass filter 10 is compared with these levels Q ₁ and Q ₂ . Level of the input signal from the low pass filter 10, the level Q ₁ less than greater than the time H, Q _1, and, when Q ₂ is greater than M and 2 bits L, and ternary decision results when Little from Q _2, Of the phase difference determination circuit 2
Output to 5.

As described above, the phase difference determination circuit 25 has I
The H, M, L ternary determination result for the component and the H, M, L ternary determination result for the Q component are input. As shown in FIG. 5, assuming that the I component is on the horizontal axis and the Q component is on the vertical axis, and the points on the I axis are 0, and the positions separated by 45 degrees counterclockwise are 1 to 7, respectively. The position of the phase of the π / 4 shift QPSK signal is any one of 1, 3, 5, and 7.

When the ternary determination result of the I component is H, the phase position of the signal is either 0, 1 or 7.
When the determination result of the I component is M, the phase position is
It becomes 2 or 6. When the determination result is L, the phase position is 3, 4 or 5. Similarly, 3 of the Q component
When the value judgment result is H, the phase position of the signal is 1
When the determination result of the I component is M, the phase position is 0 or 4, and when the determination result is L, the phase position is either 5 or 7. Therefore, the phase difference determination circuit 25 can perform the determination shown in FIG. 6 from the determination result of the three values of the I and Q components.

That is, when the determination result of the I component is H, M, L and the determination result of the Q component is H, the phase position is
It becomes 1, 2, or 3. When the determination result of the I component is H or L and the determination result of the Q component is M, the phase position is
It becomes 0 or 4. In addition, the determination result of the I component is H, M, L
If the determination result of the Q component is L, the phase position becomes 7, 6 or 5.

The phase difference judgment circuit 25 outputs the judgment result to the adder 28 and the correction circuit 27. The signal input to the adder 28 is added (corrected) to the signal output from the correction circuit 27 and supplied to the phase data conversion circuit 31 as a final determination result.

The operation of this correction will be described. The output detected by the delay detection circuit 43 including the 1-symbol delay circuits 2 and 5, the Ex-OR circuit 6 and the low-pass filter 7 is ternary determination circuit 16 Is supplied to the phase difference determination circuit 24, and the determination of three values is performed in the same manner as described above, and the determination result is supplied to the phase difference determination circuit 24. Similarly, 1-symbol delay circuits 8 and 11 and Ex-OR circuit 1
2, and the differential detection circuit 4 including the low-pass filter 13
The output that is delayed and detected by 4 is supplied to the ternary judgment circuit 19, the ternary judgment is performed, and the judgment result is supplied to the phase difference judgment circuit 24.

The phase difference judging circuit 24 is the phase difference judging circuit 2.
As in the case of 5, the phase positions 0 to 7 of the π / 4 shift QPSK signal are determined from the determination results of the ternary values of the I component and the Q component, and the determination result is output to the subtractor 23. The difference between the judgment results of the phase difference judgment circuit 24 and the phase difference judgment circuit 25 is that the phase difference judgment circuit 25 judges the phase position from the outputs of the delay detection circuits 41 and 42 which detect the input signal by delaying it by one symbol. On the other hand, the phase difference determination circuit 2
4 is that the phase position is determined corresponding to the outputs of the differential detection circuits 43 and 44 which detect the input signal by delaying it by two symbols.

On the other hand, the binary decision circuit 14 binary-decides the output of the differential detection circuit 41, which delays the I-component input signal by one symbol and detects it. That is, the binary determination circuit 14 determines whether the level of the signal input from the low-pass filter 4 is higher or lower than the 0 level as a threshold value. Output to the determination circuit 20.

Similarly, the binary decision circuit 17 makes a binary decision on the signal level of the Q component output by the low-pass filter 10, and when the level is higher than the threshold level 0, it is H, and when it is low, the decision result is L. The phase difference determination circuit 20
Output to.

In this way, the binary judgments H and L of the I component and the binary judgments H and L of the Q component are input to the phase difference judgment circuit 20. As shown in FIG. 7, when the I component is determined to be H, the phase position of the input signal is 0, 1 or 7, and when it is L, it is any of 3 to 5. Also,
When the Q component is H, the phase position of the input signal is 1 to 3
And L is any one of 5 to 7. Therefore, as shown in FIG. 8, when both the I component and the Q component are H, the phase position is determined to be 1,
When the I component is L and the Q component is H, the phase position is determined to be 3. Similarly, when the I component is H and the Q component is L, the phase position is determined to be 7, and the I component and Q
When both components are L, the phase position is determined to be 5. The phase difference determination circuit 20 is provided with this 1, 3, 5 or 7
The determination result of the phase position of is output.

The output of the phase difference judging circuit 20 is delayed by 1 symbol by the 1-symbol delay circuit 21,
Those that are not delayed are added in the adder 22. The adder 22 adds modulo 8.

That is, the delay circuit 21 and the adder 22 generate a signal having a determination result of the same level as that when the phase difference determination circuit 24 determines a signal obtained by delaying and detecting the input signal by two symbols. This signal is then subtracted by the subtractor 23.
And is subtracted from the signal output from the phase difference determination circuit 24. The signal output from the phase difference determination circuit 24 is generated based on the signals delayed by two symbols in the delay detection circuits 43 and 44. On the other hand, the adder 22
The signal output by is generated based on the signal detected by the delay detection circuits 41 and 42 with one symbol delay. Generally, as the number of delay symbols in the differential detection circuit increases, the detection performance with respect to frequency fluctuation deteriorates accordingly. In other words, the delay detection circuit that delays by 1 symbol and performs detection has a 1 / n deterioration in detection performance as compared with the delay detection circuit that delays and detects n symbols.

Therefore, the signal output by the subtractor 23 is 1
When the delay detection circuits 41 and 42 for symbols and the delay detection circuits 43 and 44 for two symbols are both demodulating correct data, it becomes 0, and it can be estimated that there is no frequency error. In other words, the output of the subtractor 23 is positive (+1) when the frequency of the signal input from the IF amplifier 1 is higher, and is negative (-1) when the frequency is lower. Become.

The integrating circuit 26 integrates the signal output by the subtractor 23 in synchronization with the input integration timing.
The preamble detection circuit 29 detects a preamble (this preamble is periodically arranged at a predetermined position of a time slot of a signal detected in this device) from the signal output by the phase difference determination circuit 24. The integrating circuit 26 resets the integrated value when the detection signal is input from the preamble detecting circuit 29. In this way, the integrating circuit 26 outputs the integrated value of the output of the subtractor 23 in the predetermined period.

The correction circuit 27 monitors the polarity (positive or negative) of the integrated value of the integration circuit 26 and the output of the phase difference determination circuit 25 (phase positions 0 to 7) and generates a correction signal. This correction signal is set to 0 when the phase position output by the phase difference determination circuit 25 is 1, 3, 5 or 7. That is, at this time, the phase position signal output from the phase difference determination circuit 25 is
Via the adder 28, the phase data conversion circuit 31 is used as it is.
Is supplied to.

On the other hand, if the phase position output from the phase difference determination circuit 25 is 0, 2, 4 or 6, and the integrated value in the integrating circuit 26 is positive, the correction signal is positive 1. , Is negative, -1 is set. Since this correction signal is added to the output of the phase difference determination circuit 25 in the adder 28, the output of the adder 28 is the output of the phase difference determination circuit 25.
When the phase position output by is 0, 2, 4 or 6, it is 1, 3, 5 or 7 if the integrated value of the integrating circuit 26 is positive, and is 7, 1 if the integrated value is negative. , 3 or 5.

In this way, the output of the adder 28 becomes one of the four phase shifters 1, 3, 5 or 7 in FIG. That is, which of the four phase positions of π / 4 shift QPSK is determined here.
Then, this phase position data is transferred to the phase data conversion circuit 3
1 is input and converted into demodulated data.

On the other hand, the integrated value of the integrating circuit 26 is latched in the latch circuit 30 immediately before being reset by the reset signal output from the preamble detection circuit 29,
The control circuit 32 controls the delay amounts of the delay circuits 2, 5, 8 and 11 in accordance with the latch result. That is, when the value latched by the latch circuit 30 is positive, the frequency of the IF signal is shifted to the higher side, so that the control circuit 32 reduces the delay amount of the delay circuit 2, 5, 8 or 11. Control. On the contrary, when the value latched by the latch circuit 30 is negative, the frequency of the IF signal is shifted to the lower side.
Switching is performed so that the delay time in each delay circuit is lengthened.

Each of the delay circuits 2, 5, 8 and 11 has a built-in shift register of, for example, 100 stages, and the delay time is controlled by changing the number of stages. When the frequency of the intermediate frequency signal input to the IF amplifier 1 is 1.2 MHz and the clocks of the delay circuits 2, 5, 8 and 11 are 19.2 MHz, each symbol has a delay circuit of 192 K symbols / sec. Will be processed in.

As described above, according to the detection circuit of FIG. 4, it is possible to detect the frequency shift in the base band and to perform the accompanying correction.

[0040]

By the way, when such a detection circuit is actually manufactured, it is generally configured as an integrated circuit, but the low pass filter 4,
Since 7, 10, and 13 are analog circuits using components such as operational amplifiers, it is difficult to completely incorporate this low-pass filter in an integrated circuit. Therefore, some of the components forming the low-pass filter are integrated circuits. Had to be attached externally. Therefore, even if the detection circuit as described above is integrated into a circuit, there is a limit in increasing the degree of integration.

In view of the above point, an object of the present invention is to digitize a low-pass filter forming a detection circuit for performing differential detection so that the detection circuit can be formed well.

[0042]

The present invention provides an input signal of 1
First delay detection means for detecting a signal with a symbol delay, a first low-pass filter for passing an output of the first delay detection means, and a first level determination for determining an output level of the first low-pass filter Means, first phase determining means for determining the phase of the output of the first level determining means, second delay detecting means for detecting the input signal by delaying a plurality of symbols, and second delay detecting means. Second low-pass filter that passes the output of the second low-pass filter, second level determination means for determining the output level of the second low-pass filter, and second phase for determining the phase of the output of the second level determination means. Determination means, third level determination means for determining the output level of the first detection means, and third phase determination means for determining the phase of the output of the third level determination means,
In a detection circuit including a detection unit that detects a frequency shift of an input signal from the output of the second phase determination unit and the output of the third phase determination unit, digital arithmetic processing is performed as the first and second low pass filters. It uses a digital filter according to.

Further, in this case, as a digital filter, input data is sequentially delayed by a shift register, and the delayed signals are sequentially added by a 1-bit adder to obtain a filtered output.

[0044]

According to the present invention, by using a digital filter by digital arithmetic processing as the low-pass filter, all the detection circuits for performing differential detection are digitalized, and the degree of integration when integrated into a circuit is increased. It will be possible.

Further, in this case, the input data is sequentially delayed by the shift register, and the delayed signals are sequentially added by the 1-bit adder to obtain the filtered output, whereby the data at the zero cross point is saved. , Good digital processing suitable for phase modulated waves is performed.

[0046]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

This example is applied to a detection circuit for differentially detecting the π / 4 shift DQPSK-modulated digital data shown in FIG. 4, and low-pass filters 4, 7, 10, and 13 of the detection circuit are shown in FIG. It is configured as shown in FIG. That is, each low pass filter 4, 7, 10, 13
The outputs of the Ex-OR circuits 3, 6, 9 or 12 that have the same configuration and are obtained at the data input terminal 51 are connected in series to the 32-bit addition blocks 70a, 70b, 70c.
Supply in order. This 32-bit addition block 70
The configurations of a, 70b and 70c will be described later. Then, the output of the final 32-bit addition block 70c is supplied to the shift register 53. Reference numeral 52 denotes a clock input terminal, and the clock (clock synchronized with the input data) obtained at the input terminal 52 is supplied to each of the 32-bit addition blocks 70a, 70b, 70c and the shift register 53. Here, the clock frequency is 19.2 MHz.
And 192k symbols / second are to be processed.

Here, each 32-bit addition block 70
2, the 32-bit addition blocks 70a, 70b, 70c have the same configuration, and the data obtained at the data input terminal 71 is supplied to the shift register 80a for clock input. In synchronism with the clock obtained at the terminal 72, the clocks are sequentially delayed by one clock and delayed by eight clocks. That is, the shift register 80a
Is eight D flip-flops 8 as shown in FIG.
., 88, each D flip-flop 8
The input data is delayed by 1 clock by 1 to 88, and finally the data delayed by 8 clocks is obtained at the output terminal 89.

Returning to the explanation of FIG. 2, the data delayed by 8 clocks by the shift register 80a thus configured is supplied to the shift register 80b of the next stage, and further delayed by 8 clocks by the shift register 80b. The generated data is supplied to the shift register 80c of the next stage, and the data delayed by 8 clocks by the shift register 80c is supplied to the shift register 80d of the next stage. Then, by the shift register 80d at the final stage,
The clock delayed data is supplied to the output terminal 73. Therefore, the data obtained at the output terminal 73 becomes the data obtained by delaying the data obtained at the input terminal 71 by 32 clocks. In addition, each shift register 80a, 80b, 8
0c and 80d have the same configuration.

The four shift registers 80a-8
The data delayed by 1 bit by 0d is extracted from each shift register 80a to 80d. Therefore, a total of 32 bits of data are extracted from the four shift registers 80a-80d. Then, each shift register 80a-
The 8-bit data extracted from 80d is converted into 8-bit addition blocks 90a, 90b, 90c and 90d, respectively.
Supply to.

Each of these 8-bit addition blocks 90
a to 90d have the same configuration and are configured as shown in FIG. That is, the shift register 80a (or 80b, 8
0c, 80d) output 8-bit data to 2
Supply to the bit half adder. This 2-bit half adder is composed of Ex-OR circuits 91a, 92a, 93a, 94a and
It is composed of ND circuits 91b, 92b, 93b and 94b. For example, the outputs of the D flip-flops 81 and 82 of the shift register 80a are supplied to the Ex-OR circuit 91a and the AND circuit 91b, respectively, and the EX-OR circuit 91a takes the exclusive OR, and the AND circuit 91b performs the logical operation. Take the product.

The Ex-OR circuits 91a, 92a, 93
a, 94a and AND circuits 91b, 92b, 93b, 94
By the 2-bit half adder configured by b and b, data of adjacent bits are added to form 2-bit data. In this case, the Ex-OR circuits 91a, 92a, 93a, 94a
Output becomes the lower bit, and AND circuits 91b and 92
The outputs of b, 93b and 94b become the upper bits.

Then, 2 output from each half adder
The bit data is supplied to the 2-bit adder 95 or 96. That is, the 2-bit output of the half adder composed of the Ex-OR circuit 91a and the AND circuit 91b and the 2-bit output of the half adder composed of the Ex-OR circuit 92a and the AND circuit 92b are combined. 3 to which each 2-bit data is added by the arithmetic processing
Obtain bit data (4-bit added value). Also, Ex-
The 2-bit output of the half adder composed of the OR circuit 93a and the AND circuit 93b, and the AND of the Ex-OR circuit 94a
The 2-bit output of the half adder configured by the circuit 94b and the 2-bit output are supplied to the 2-bit adder 96, and 3-bit data (4-bit addition value) obtained by adding the respective 2-bit data by the arithmetic processing is obtained. obtain.

Then, each 2-bit adder 95,
The data of 3-bit data output from 96 is supplied to the 3-bit adder 97, and 4-bit data obtained by adding the respective 3-bit data is obtained by arithmetic processing. Then, the 4-bit data is converted into the 8-bit addition block 9
1 as the output of 0a (or 90b, 90c, 90d)
Each bit is supplied to the output terminals 98a, 98b, 98c, 98d.

Returning to the explanation of FIG. 2 again, the 4-bit data (8-bit addition value) output from each 8-bit addition block 90a, 90b, 90c, 90d is supplied to the 4-bit adders 74, 75. To do. That is, the 4-bit data output by the 8-bit addition block 90a and the 4-bit data output by the 8-bit addition block 90b are set to 4
The data is supplied to the bit adder 74, and 5-bit data (16-bit addition value) obtained by adding the respective 4-bit data is obtained by arithmetic processing. Also, the 8-bit addition block 90
5-bit data obtained by supplying the 4-bit data output by c and the 4-bit data output by the 8-bit addition block 90d to the 4-bit adder 75 and adding the respective 4-bit data through arithmetic processing. (16-bit added value) is obtained.

Then, each 4-bit adder 74,
5-bit data output by 75 (16-bit addition value)
The lower 4 bits of the above are supplied to the 4-bit adder 76,
By the arithmetic processing, 5-bit data obtained by adding each 4-bit data is obtained. Then, the lower 4 bits of the 5-bit data are output to the output terminal 78 bit by bit.
a, 78b, 78c, 78d.

The most significant bit of the output of the 4-bit adder 74 and the most significant bit of the output of the 4-bit adder 75 are supplied to both the AND circuit 77a and the Ex-OR circuit 77b. Then, the output of the Ex-OR circuit 77b and the most significant bit of the 5-bit data output by the 4-bit adder 76 are supplied to the OR circuit 77c, and the output of the OR circuit 77c is output to the output terminal 78e. Supply. Then, the output of the AND circuit 77a is supplied to the output terminal 78f.

In this way, the 32-bit addition block 7
0a (or 70b, 70c) output terminals 78a to 78f
Then, 6-bit data obtained by adding the 5-bit data that is the 16-bit addition value output from each of the 4-bit adders 74 and 75 is obtained. This 6-bit data is a 32-bit added value.

Next, FIG. 1 in which the 32-bit addition blocks 70a, 70b and 70c configured as described above are incorporated.
The overall configuration of the low-pass filter shown in FIG. 2 will be described. 6-bit data (32-bit addition value) output by the 32-bit addition block 70a and 6-bit data (32-bit addition value) output by the 32-bit addition block 70b. Is supplied to the 6-bit adder 54, and 7-bit data (64-bit addition value) added by the arithmetic processing is added.
To get Then, the 7-bit data (64-bit addition value) is supplied to the 7-bit adder 58.

The 6-bit data (32-bit addition value) output from the 32-bit addition block 70c is supplied to the 6-bit adder 55 and the shift register 53 is also provided.
The added value of the output on the side is supplied to the 6-bit adder 55.

The configuration from the shift register 53 to the 6-bit adder 55 will be described below.
3 is configured to delay the output data of the 32-bit addition block 70c by 4 bits, and the data delayed by 1 bit and the data delayed by 2 bits are transferred to the Ex-OR circuit 56a.
To the AND circuit 56b and the 2-bit data (2
Bit addition value). In addition, the data delayed by 3 bits and the data delayed by 4 bits are transferred to the Ex-OR circuit 56.
c and the AND circuit 56d to supply 2-bit data (2-bit added value).

Then, the 2-bit data as each 2-bit addition value is supplied to the 2-bit adder 57, and the 3-bit data (4-bit addition value) added by the arithmetic processing is obtained. Then, 3 as this 4-bit addition value
The bit data is supplied to the 6-bit adder 55.

In the 6-bit adder 55, the 6-bit data (32-bit addition value) supplied from the 32-bit addition block 70c and the 3-bit data (4-bit addition) supplied from the 2-bit adder 57 are added. Value) and addition processing to obtain 7-bit data (36-bit addition value),
The 7-bit data is supplied to the 7-bit adder 58.

In the 7-bit adder 58, the 7-bit data (64-bit addition value) supplied from the 6-bit adder 54 and the 7-bit data supplied from the 6-bit adder 55 are supplied.
Add processing with bit data (36-bit addition value),
8-bit data. This 8-bit data is 1
It is an added value of 00 bits. Then, the 8-bit data as the 100-bit addition value is output to the output terminals 61, 6 of the low-pass filter 4 (or 7, 10, 13).
2, 63, 64, 65, 66, 67, 68 are supplied bit by bit.

According to the low-pass filter having such a configuration, the data obtained at the input terminal 51 is sequentially delayed by 100 clocks in synchronization with the clock obtained at the clock input terminal 52, and the delay signal for each clock is 100. Bit addition is performed, and the 100-bit addition signal is obtained as 8-bit data at the output terminals 61 to 68. This 100-bit addition signal is output as filtered data that cuts high frequencies by a low-pass filter.

The output of the low-pass filter obtained by such processing is the IIR type digital filter or FIR.
Unlike a digital filter of the type, the signal at the zero-cross point is stored in the output in its original phase. Therefore, accurate symbol synchronization can be achieved based on the output of the low-pass filter of this example in which the signal at the zero-cross point is stored as it is, and the phase difference determination connected to the subsequent stage of the low-pass filters 4, 7, 10, and 13 can be performed. Can be done accurately. Therefore, the low-pass filters 4, 7, 10, 13 of the configuration of this example are
According to the detection circuit shown in FIG. 4 that uses, the phase-modulated π / 4 shift DQPSK modulated wave can be accurately detected. Further, when the detection circuit is configured by an integrated circuit, all circuits such as the low-pass filter are converted into digital circuits, and the integrated circuit can be configured as a highly integrated circuit with no external parts, which simplifies the configuration. Furthermore, since all the circuits can be configured by digital circuits, they are less likely to be affected by noise, and the detection circuit can be driven at a low voltage, which reduces the load on the power supply circuit.

In the above embodiment, the present invention is applied to the detection circuit for receiving the π / 4 shift DQPSK modulated digital data, but it can also be applied to the detection circuit for detecting other phase modulated data.

[0068]

According to the present invention, by using a digital filter by digital operation processing as the low-pass filter, all the detection circuits for performing differential detection are digitalized, and the degree of integration when integrated into a circuit is increased. It will be possible.

In this case, the input data is sequentially delayed by the shift register, and the delayed signals are sequentially added by the 1-bit adder to obtain the filtered output. Good digital processing in which is stored is performed, and differential detection based on the output of this low-pass filter can be accurately performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a low-pass filter according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a 32-bit addition block of a low pass filter according to an embodiment.

FIG. 3 is a configuration diagram showing configurations of an 8-bit addition block and a shift register of a low pass filter according to an embodiment.

FIG. 4 is a configuration diagram of a detection circuit to which an embodiment is applied.

FIG. 5 is an explanatory diagram showing π / 4 shift DQPSK modulation.

FIG. 6 is an explanatory diagram showing a determination state by a detection circuit.

FIG. 7 is an explanatory diagram showing π / 4 shift DQPSK modulation.

FIG. 8 is an explanatory diagram showing a determination state by a detection circuit.

[Explanation of symbols]

 4, 7, 10, 13 Low-pass filter 51 Data input terminal 52 Clock input terminal 61, 62 ... 68 Data output terminal

Claims (2)

[Claims] 1. A first differential detection means for detecting an input signal by delaying it by one symbol, a first low-pass filter for passing an output of the first differential detection means, and an output of the first low-pass filter. First to judge the level
Level determining means, first phase determining means for determining the phase of the output of the first level determining means, second delay detecting means for detecting the input signal by delaying it by a plurality of symbols, and second Second low-pass filter for passing the output of the differential detection means of the above, and a second low-pass filter for judging the output level of the second low-pass filter
Level determining means, second phase determining means for determining the phase of the output of the second level determining means, third level determining means for determining the output level of the first detecting means, and The frequency shift of the input signal is detected from the third phase determining means for determining the phase of the output of the third level determining means, and the output of the second phase determining means and the output of the third phase determining means. A detection circuit comprising a detection means, wherein a digital filter by digital operation processing is used as the first and second low-pass filters. 2. As the digital filter, input data is sequentially delayed by a shift register, and the delay signal is set to 1
2. The detection circuit according to claim 1, wherein a bit adder is sequentially added to obtain a filtered output.