JPH0730848A - Image signal playback device - Google Patents

Abstract

(57) [Abstract] [Purpose] When reproducing data of undecodable block, inter-frame interpolation data is generated diagonally from the surrounding blocks of the undecodable block, and inter-frame interpolation and conventional intra-field interpolation are performed. Provided is an image signal reproducing device capable of obtaining a reproduced image with little visual deterioration by being selectively used. An image signal reproducing apparatus is an image signal reproducing apparatus which decodes data obtained by block-encoding an image signal for each of a plurality of pixels in block units and reproduces the image signal. The image signal reproducing apparatus is decoded using error-correctable data. Interpolating means for interpolating the data, and the interpolating means is configured to perform the interpolation by using the interpolating data generated in the diagonal direction from the surrounding block of the undecoding block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal reproducing apparatus, and more particularly to an image signal reproducing apparatus for correcting and reproducing error-uncorrectable data of a highly efficient coded television moving image signal. is there.

[0002]

2. Description of the Related Art An orthogonal transform coding system is known as a technique for compressing and coding an image signal with high efficiency. this is,
After the image signal is grouped into a plurality of prime numbers and divided into blocks, orthogonal transformation such as discrete cosine transformation is performed, and the transformed coefficients are quantized and entropy coded.

In this system, since coding is performed in block units, when an error occurs in coded data, a code error occurs in block units. In addition, since variable-length codes are often used, decoding errors propagate over a plurality of blocks, leading to large image deterioration. Then, out of such decoding errors, data that cannot be completely corrected even if error correction processing is performed is interpolated by data of blocks temporally and spatially close as error-correctable data (hereinafter, undecodable data). I was going.

Conventionally, when interpolating image data of such undecodable blocks, interframe interpolation and intrafield interpolation are often used selectively. That is, the inter-frame correlation of the image data of the upper and lower blocks of the missing block (the intra-block addition result of the absolute difference between the pixel of the current frame and the pixel of the previous frame) is obtained, and the presence or absence of motion of the undecodable block is estimated. , If there is motion, the field is selected, and if there is no motion, interframe interpolation is selected.

[0005]

However, when such a conventional method is applied to the case where the undecodable block moves in a fine image, the surroundings of the undecodable block are fine images. Intrafield interpolation is selected regardless. In this case, the intra-field interpolation has a temporal correlation but a spatially rather weak correlation, and the interpolated block has a reduced resolution, and a low-resolution block exists in a fine image. However, the image becomes unbalanced.

In consideration of the above problem, the present invention generates intra-field interpolation data in an oblique direction from a peripheral block of the non-decodable block when reproducing the data of the non-decodable block, and performs inter-frame interpolation, An object of the present invention is to provide an image signal reproducing device capable of obtaining a reproduced image with little visual deterioration by selectively using the conventional intra-field interpolation.

[0007]

SUMMARY OF THE INVENTION In order to solve the problems conventionally held and to achieve the above-mentioned object, the present invention decodes image data block-encoded for each plurality of pixels in the block unit, An image signal reproducing apparatus for obtaining a signal, comprising interpolation means for interpolating the data of the undecodable block by interpolation data generated from the surrounding blocks of the undecodable block, wherein the interpolation means is data for the surrounding block. By this, interpolation data is generated in an oblique direction, and interpolation is performed by the interpolation data.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First, the data flow of an image signal reproducing apparatus including an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing the configuration of a digital VTR including an embodiment. In FIG. 1, the input terminal 1
From 01, digitized image data is input, and is blocked by the blocking circuit 102 in 8 × 8 pixel units in frame units. The image data divided into blocks is orthogonally transformed by the DCT circuit 103 and transformed from the spatial domain to the frequency domain.

The image data converted into the frequency domain is quantized by the quantization circuit 104, and the variable length coding circuit 1 is further quantized.
Coded at 05 to get the desired data transfer rate. The encoded data is error-correction encoded by the error-correction encoding circuit 106, and recorded on the recording medium by the recording / reproducing circuit 107.

At the time of reproduction, the data reproduced by the recording / reproducing circuit 107 is input to the error correction circuit 108 to correct the code error, and then decoded by the variable length decoding circuit 109. The decoded data is inversely quantized by the inverse quantization circuit 110, then inverse DCT is performed by the inverse DCT circuit 111, converted from frequency domain data to spatial domain data, and written in the frame memory 112. Frame memory 11
The written data is read in accordance with the raster scan of a monitor or the like, the error data is interpolated by the interpolation circuit 113, and then output from the output terminal 114 to be displayed on the monitor or the like.

Next, the image signal reproducing apparatus according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a block diagram of this embodiment. In this embodiment, it is assumed that the coded block of the image signal is coded by 8 pixels × 8 pixels (line) in the frame. Further, in the present embodiment, the processing of input data is performed in field units, that is, 4 pixels (line) × 8 pixels (horizontal) as one block.

In FIG. 2, image data to which an error correction code such as Reed-Solomon product coding is added is subjected to error correction decoding by error correction processing, and is input from the input terminal 1 in the order of normal interlaced scanning. Further, in synchronization with this input data, an error flag indicating that the input data cannot be decoded is input from the error flag input terminal 8. The input image data is written in the memory 2 having a capacity of 2 frames. The reading of the image data is performed by the control circuit 6 described later.

The input image data is also input to the motion determination circuit 4, where the motion of the undecodable block is estimated by the motion of the surrounding blocks, and the estimation result is output to the control circuit 6. In addition to this motion estimation result, the above-mentioned error flag is also input to the control circuit 6. Control circuit 6
Is based on this motion estimation result and error flag,
From the data stored in the memory 2, the data necessary for the interpolation operation at the subsequent stage is read and output. The control circuit 6 also controls the switching circuit 3 to connect to the a side when the data read from the memory 2 is not undecodable data and to the b side when undecodable data is read. Connecting.

Data required for interpolation is read from the memory 2 and input to the interpolation circuit 5. The interpolator 5 interpolates between frames based on the control signal from the control circuit 6.
Interpolation data of the intra-field interpolation a and the intra-field interpolation b is generated, interpolated and output.

A block diagram showing the structure of the interpolation circuit 5 is shown in FIG. The data read from the memory 2 and the data corrected correctly are input to the switch circuit 301. Then, the switch circuit 301 receives the error flag, and when the data read from the memory 2 is undecodable data, the data side (a side) that has been corrected correctly
Switch to. The output of the switch 301 is input to the frame memory 302 and the intra-field interpolation circuit 303, and inter-frame interpolation data and intra-field interpolation data are generated as will be described later and output to the switch circuit 304.
The switch circuit 304 receives the signal from the control circuit 6 and switches the switch circuit 304 to output interframe interpolation / intrafield interpolation data.

Now, the above-mentioned inter-frame interpolation and intra-field interpolation methods will be described. In FIG.
When the block X of the frame #N is a non-decodable block, the data of the block X is replaced by the decoded data of the block A at the same position on the screen in the previous frame # N-1 to interpolate.

Next, the operation of the intra-field interpolation circuit 303 will be described. In this interpolation circuit, interpolation is performed with the pixel closest to the undecodable block in the two blocks adjacent to the undecodable block in the diagonal direction.

First, interpolation is performed from the data of the odd field. In FIG. 5, image data (x ₇₀ , x ₅₂ , x ₃₄ ,
x ₁₆ ), using c ₁₆ which is the data of the odd field of the block C and closest to the block X, and e ₇₀ which is the data of the odd field of the block E which is closest to the block X, Linear interpolation is performed according to the distance to the data to be interpolated. That is, in odd fields, x ₇₀ = (4 × c ₁₆ + e ₇₀ ) / 5, x ₅₂ = (3 × c
₁₆ + 2 × e ₇₀ ) / 5, x ₃₄ = (2 × c ₁₆ + 3 × e ₇₀ ) /
5, x ₁₆ = (c ₁₆ + 4 × e ₇₀ ) / 5 is interpolated.

After the interpolation processing of the odd field is completed, the even field processing is similarly performed. In the even field, the image data (x ₆₁ , x ₄₃ , x ₂₅ , x ₀₇ ) is interpolated by the data c _{07 of the} block C and the data e _{61 of the} block E.

Also, the interpolation of the data other than the diagonal line is basically performed in the same manner as the case shown in FIG. This state is shown in FIGS. 6 and 7. In FIG. 6, the image data (x ₇₁ , x ₅₃ , x ₃₅ , x ₁₇ ) is converted into the data h of the block H.
₀₁ and the data e _{71 of the} block E are interpolated by the image data (x ₆₂ , x ₄₄ , x ₂₆ ) to obtain the data h _{00 of the} block H.
And the data e ₇₀ of the block E are interpolated. In FIG. 7, the image data (x ₇₄ , x ₅₆ ) is interpolated by the data h _{04 of the} block H and the data f ₄₀ of the block F,
The image data (x ₆₅ , x ₄₇ ) is interpolated by the data h _{03 of the} block H and the data f ₄₁ of the block F.

The intra-field interpolation circuit 303 will be described with reference to FIGS. 8 to 10. FIG. 8 is a block diagram showing the intra-field interpolation circuit 303. The image data is input in units of fields, and the 6-line delay circuit 80
At 1, the data required for interpolation is selected. FIG. 9 shows the configuration of the 6-line delay circuit 801, and the configuration for one line is such that 1 data delay elements 901 to 916 and 1H-16 delay circuit 997 are connected in series, and both ends of each delay element are connected. (17 types) of data can be output. Further, by connecting six lines for one line of this configuration in series (however, the sixth stage is composed of only one data delay element), the surrounding image data of the non-decodable block ( 17 x 6 types) output is possible. Each stage outputs the image data of the delay amount of 8 data times before and after, i.e., 17 types of delay amount, using i as the reference (current) data of the line, and the selector circuits 1001 to 1016 of the next stage output each delay amount. 16 types of data are selected for each. This selection operation is determined by the address of undecodable data.

In this way, 16 types of data from i-8 to i + 8 are selected by the 6-line delay circuit 801,
Further, it is output to the next selection circuits 802 and 803. The selection circuit 802 receives the address of the undecodable data from the address generator 808, and selects the delay amount necessary for the above-mentioned diagonal interpolation from the data i-8 to i-1 in the horizontal direction with respect to the data i. Select data. Selection circuit 80
Similarly for 3 as well, data 1 is selected from data i + 8 to i + 1.
Choose one. The data selected by the selection circuits 802 and 803 are output to the multiplication circuits 805 and 806, respectively, and are multiplied by the coefficient read from the coefficient ROM 804.

The error flag indicates the address generator 8
08 and the switch circuit 809. The address generator 808 receives the error flag, detects the address in the block of undecodable data, and outputs it to the 6-line delay circuit 801, the selection circuits 802, 803 and the coefficient ROM 804. The coefficient ROM 804 receives the address of the undecodable data, detects the position of the data in the block, and outputs the optimum coefficient at each position.

The data multiplied by the coefficients in the multiplication circuits 805 and 806 are output to the addition circuit 807, added, and output to the switch circuit 809. Switch circuit 8
09 is controlled by an error flag, and is switched to the E (Error) side only when the error flag is set.

Now, the above-described interpolation operation will be compared with the output data of the selection circuits 802 and 803 shown in FIG. Figure 9
In the delay circuit in, the data 0-i + 5 (0th stage) is
If the data c ₁₆ in FIG. 5 is output, the first
The data in the row is the data two lines below in FIG. 5, and 16 data are selected for each line. Therefore, the data 5-i-5 (fifth stage) is the data e
It means that ₇₀ is output. Then, in the selection circuits 1001 to 1016 shown in FIG. 10, a total of 16 data are selected from the 16 data of each line based on the address of the undecodable data, one for each delay amount. . The data selected here indicates that among the data of the blocks around the undecodable block, when the lines are taken vertically, one data is selected from each line. From the data thus selected, the selection circuits 802 and 803 finally select which delay amount data is to be used for interpolation.
That is, the data (x _70, x ₅₂ , x ₃₄ ,
x ₁₆ ), the data c ₁₆ and the data e ₇₀ are selected.

As described above, the undecodable data on which the respective interpolations have been performed (actually, only one interpolation process is performed under the control of the control circuit) is output to the switch circuit 304. The switch circuit 304 receives the signal from the control circuit 6, selects one from these two interpolation data, and outputs it.

The interpolated data is transferred to the switching circuit 3
Is output to the terminal b. As described above, the switching circuit 3 selects the non-error data from the terminal a or the interpolated data from the terminal b and outputs it from the output terminal 7.

In the present embodiment, since the intra-field interpolation is performed in an oblique direction when there is a motion in the image, it is possible to perform the interpolation with the data having a stronger visual correlation.

Next, a second embodiment of the present invention will be described with reference to FIGS. 11 to 15. It should be noted that components having the same or similar functions to those of the first embodiment are designated by the same reference numerals and detailed description thereof will be omitted.

In this embodiment, in order to determine the interpolation process, the estimation result of estimating the spectrum of the data block is used in addition to the motion information.

In FIG. 11, the spectrum estimation circuit 9
Estimates and outputs that of the non-decodable block from the spectrum level of the blocks around the non-decodable block. The operation of the spectrum estimation circuit 9 will be described with reference to FIGS. In FIG. 12, the input image data is DCT processed by the DCT circuit 121. The DCT coefficient is shown in FIG. 13, and the DCT coefficient is divided into areas as shown in FIG. 14 by the frequency area dividing circuit 122. Then, the rank determination circuit 123 evaluates and outputs the energy intensity of each area. Specifically, the rank of the movement is determined by comparing the level of the DCT coefficient of each area with a certain threshold value. Here, rank signals are output for a case where a large number of horizontal high frequency components (areas 3 and 4 in FIG. 14) are included and a case where a large amount of diagonal high frequency components (areas 7 and 8 in FIG. 14) are included. Then, the spectrum status of the undecodable block is estimated from the data of the blocks surrounding the undecodable block, here the blocks adjacent to the upper and lower sides of the undecodable block.

The control circuit 6 inputs the motion determination result and the spectrum detection result, and when it is determined that there is a small amount of high frequency components in the horizontal direction with respect to the interpolating circuit 5 and there is motion, inter-field interpolating in line units described later is performed. If there is little high frequency component in the diagonal direction and it is determined that there is motion, a signal is output so as to perform the above-described diagonal intra-field interpolation.

Here, the intra-field interpolation in line units will be described with reference to FIG.

Now, suppose that the block X in FIG. 15 is an undecodable block. As described above, in this embodiment, the processing is executed in field units. Therefore, odd field line x of non-decodable block X
1, x3, x5, and x7 are the same as the line a7 of the block A, which is the line of the same field closest to the uppermost line x1 of the odd field among the lines of the correctly decoded block, and the closest to the lowermost line x7. In-field linear interpolation is performed by the line b1 of the block B, which is the line of the field. That is, as shown in FIG.
In the odd field, x1 = (4 × a7 + b1)
/ 5, x3 = (3 × a7 + 2 × b1) / 5, x5 = (2
Xa7 + 3xb1) / 5, x7 = (a7 + 4xb1) /
It becomes 5.

After the interpolation processing of the odd field is completed, the processing of the even field is similarly performed. In the even field, the lines x2, x4, x6, and x8 are interpolated by the line a8 of the block A and the line b2 of the block B. In this way, the intra-field interpolation in line units is performed.

In this embodiment, in the case where there is a motion in the image and the frequency component in the horizontal direction is the main component, intra-field interpolation is performed on a line unit basis, and when the frequency component in the diagonal direction is the main component, the diagonal interpolation is performed. By performing the intra-field interpolation of the direction, the interpolation suitable for the correlation between the image block and the surrounding blocks can be performed. Therefore, the deterioration of the image is visually inconspicuous.

[0039]

As is apparent from the above description, according to the present invention, in the correction of the block-coded image signal, the diagonal interpolation is performed as the intra-field interpolation when the data of the non-decodable block is corrected. ing.

Generally, in view of human eyes, the sensitivity in the diagonal direction is lower than that in the horizontal / vertical direction.
In a system that performs compression / encoding using orthogonal transformation or the like, the frequency characteristic of the image signal in the diagonal direction is suppressed in advance. Since the image signal has a low occupancy ratio of diagonal components and a high correlation between pixels as compared with the vertical / horizontal directions, data of blocks located diagonally of undecodable blocks is used as in the present invention. When intra-field interpolation is performed by using a field, distortion of an image (discontinuity of a pattern, etc.) becomes less noticeable, and the effect of interpolation correction is high.

Further, in addition to the motion status of the surrounding blocks,
By estimating the spectrum of the undecodable block based on the spectrum of the surrounding blocks,
In order to switch between intra-field interpolation in line units and inter-field interpolation in diagonal directions, if there is strong correlation in the horizontal direction in a moving image, inter-field interpolation in line units is performed, and motion is strongly correlated in the diagonal direction in the image. In this case, diagonal in-field interpolation is performed. Therefore, when a non-decodable block moves in a fine image, it becomes possible to interpolate with data having a stronger correlation, and the low resolution block does not exist in the fine image. Further, even in an image in which an undecodable block is interpolated, there is no change in resolution that gives a sense of discomfort, and an image with a good balance is obtained.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a data flow in an embodiment of the present invention.

FIG. 2 is a block diagram of an image signal reproducing apparatus according to the first embodiment of the present invention.

FIG. 3 is a block diagram of an interpolation circuit in the embodiment of the present invention.

FIG. 4 is a diagram for explaining interframe interpolation in the embodiment of the present invention.

FIG. 5 is a diagram for explaining intra-field interpolation in the embodiment of the present invention.

FIG. 6 is a diagram for explaining intra-field interpolation in the embodiment of the present invention.

FIG. 7 is a diagram for explaining intra-field interpolation in the embodiment of the present invention.

FIG. 8 is a block diagram of an intra-field interpolation circuit in the embodiment of the present invention.

FIG. 9 is a diagram for explaining the internal operation of the intra-field interpolation circuit in the embodiment of the present invention.

FIG. 10 is a block diagram for explaining the internal operation of the intra-field interpolation circuit in the embodiment of the present invention.

FIG. 11 is a block diagram of an image signal reproducing device according to a second embodiment of the present invention.

FIG. 12 is a diagram showing DCT coefficients for explaining the operation of the spectrum detection circuit in the second exemplary embodiment of the present invention.

FIG. 13 is a diagram for explaining the operation of the spectrum detection circuit in the second exemplary embodiment of the present invention.

FIG. 14 is a block diagram of a spectrum detection circuit according to a second embodiment of the present invention.

FIG. 15 is a diagram for explaining inter-field interpolation in line units according to the second embodiment of the present invention.

[Explanation of symbols]

 4 Motion determination circuit 5 Interpolation correction circuit 9 Spectrum detection circuit 302 In-field interpolation circuit

Claims (2)

[Claims] 1. An image signal reproducing apparatus for reproducing the image signal by decoding the block-encoded data of an image signal for each of a plurality of pixels and reproducing the image signal. Interpolation data generated from a peripheral block of an undecodable block. According to the above, there is provided an interpolating means for interpolating the data of the undecodable block, wherein the interpolating means generates the interpolated data in an oblique direction by at least the data of the surrounding blocks, and performs the interpolating by the interpolated data. Image signal reproducing device. 2. An image signal reproducing apparatus which reproduces an image signal by decoding the block-encoded data of an image signal for each of a plurality of pixels and reproducing the image signal by a predetermined method from a block surrounding an undecodable block. The generated interpolation data, the interpolation means for interpolating the data of the undecodable block is provided, the interpolation means generates interpolation data in an oblique direction by the data of at least the surrounding block, and performs interpolation by the interpolation data, The image signal reproducing apparatus, wherein the predetermined method can be changed based on frequency information of the surrounding blocks.