JPH0730847A - Image playback device - Google Patents

Abstract

(57) [Summary] [Objective] When reproducing image data, by selecting a data block to be used for intra-field interpolation based on the decoding state of a peripheral block of an error-correctable block, a part of the peripheral block is error-corrected. (EN) Provided is an image reproducing apparatus capable of performing a reproduced image with little visual deterioration even if interpolation is not possible. An image reproduction device is an image reproduction device that decodes encoded image data and reproduces an image, and an interpolation unit that interpolates target image data using its surrounding data, and the surrounding data of the surrounding data. The decoding means includes a detection means for detecting a decoding state, and a selection means for selecting data to be used for interpolation from the surrounding data based on the detection result of the detection means, and the interpolation means is selected by the selection means. The target image data is interpolated using the obtained data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal reproducing apparatus, and more particularly, to an image reproducing apparatus for correcting and reproducing error-correctable data of a highly efficient encoded television moving image signal. .

[0002]

2. Description of the Related Art An orthogonal transform coding system is known as a technique for compressing and coding an image signal with high efficiency. this is,
After the image signal is grouped into a plurality of prime numbers and divided into blocks, orthogonal transformation such as discrete cosine transformation is performed, and the transformed coefficients are quantized and entropy coded.

In this system, since coding is performed in block units, when an error occurs in coded data, a code error occurs in block units. In addition, since variable length codes are often used, decoding errors often propagate over a plurality of blocks, resulting in large image deterioration. Then, among such decoding errors, data that cannot be completely corrected even if error correction processing is performed is interpolated by data of blocks that are temporally and spatially close as error uncorrectable data (hereinafter, undecodable data). I was going.

Conventionally, when interpolating image data of such undecodable blocks, interframe interpolation and intrafield interpolation are often used selectively. That is, the inter-frame correlation of the image data of the upper and lower blocks of the undecodable block (in-block addition result of the absolute value of the difference between the pixel of the current frame and the pixel of the preceding frame) is obtained, and the presence or absence of motion of the undecodable block is determined. It was estimated that intra-field was selected when there was motion, and inter-frame interpolation was selected when there was no motion.

Of the above-mentioned interpolations, the intra-field interpolation is performed by using the image data of the upper and lower blocks of the non-decodable block due to the structure of the above-mentioned coding block.

[0006]

However, when performing the intra-field interpolation, the blocks used for the interpolation are determined in advance, and the upper and lower blocks of the undecodable block can both be error-corrected (hereinafter, decodable). In-field interpolation is possible only in certain cases. But,
As described above, when a code error occurs, it propagates over multiple blocks. Therefore, it is not always possible for both upper and lower blocks to be decoded. If at least one of the upper and lower blocks is undecodable, inter-frame interpolation is performed. I had to do.

In consideration of the above problem, the present invention checks the decoding states of the blocks surrounding the undecodable block when reproducing the data of the undecodable block, and performs the intra-field interpolation based on this decoding state. By selecting the data block to be used, even if a part of the surrounding blocks of the undecodable block is undecodable, it is possible to interpolate in the field and obtain a reproduced image with little visual deterioration. The present invention aims to provide a simple image reproducing device.

[0008]

SUMMARY OF THE INVENTION In order to solve the problems conventionally held and to achieve the above object, the present invention is an image reproducing apparatus for decoding encoded image data and reproducing the image, Interpolation means for interpolating the target image data by using the surrounding data, detecting means for detecting the decoding state of the surrounding data, and used for interpolation from the surrounding data based on the detection result of the detecting means. Selecting means for selecting data, and the interpolating means is configured to interpolate the target image data using the data selected by the selecting means.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the overall construction of an image signal reproducing apparatus including an embodiment of the present invention. First, the operation of recording an image signal will be described. In FIG. 1, digitized image data is input from an input terminal 101, and a blocking circuit 102 outputs 8 × in frame units.
It is divided into blocks in units of 8 pixels. The image data divided into blocks is orthogonally transformed by the DCT circuit 103 and transformed from the spatial domain to the frequency domain.

The image data converted into the frequency domain is quantized by the quantization circuit 104, and the variable length coding circuit 1 is further quantized.
Coded at 05 to get the desired data transfer rate. The encoded data is recorded on the recording medium by the recording / reproducing circuit 106.

At the time of reproduction, the data reproduced by the recording / reproduction circuit 106 is input to the error correction circuit 2 to correct the code error, and then decoded by the variable length decoding circuit 108. The decoded data is inversely quantized by the inverse quantization circuit 109, then inversely DCTed by the inverse DCT circuit 110, and converted from the frequency domain to the spatial domain data. The variable length decoding circuit 107, the dequantization circuit 108, and the inverse DCT circuit 109 form one block decoding circuit 4. The output of the inverse DCT circuit 109 is written in the frame memory 6. The data written in the frame memory 6 is read out in accordance with the raster scan of the monitor or the like, and after interpolating the undecodable data by the interpolation circuit 9, it is output from the output terminal 110 and displayed on the monitor or the like. .

Next, the image signal reproducing apparatus according to the first embodiment of the present invention will be described with reference to FIGS.

In FIG. 2, an image signal reproduced from a recording medium such as a magnetic tape is input from an input terminal 1, and an error correction circuit 2 corrects a code error, and
If the code error cannot be corrected, an error flag indicating that the error cannot be corrected is output in block units. The image signal whose code error has been corrected by the error correction circuit 2 is input to the data separation circuit 3 and divided into block address data and image data. Then, the address data is output to the memory control circuit 5, and the image data is output to the block decoding circuit 4.

The block decoding circuit 4 outputs the decoded image data to the frame memory 6 in block units, and
The number of correctly decoded data in the block is counted, and the number (hereinafter, decoding level data) is output to the block selection circuit 7. The memory control circuit 5, based on the block address data from the data separation circuit 3,
The write address of the decoded image data of each block to the frame memory 6 is determined, and whether or not the decoded image data of the corresponding block is written to the frame memory 6 is determined by the error flag output from the error correction circuit 2. When the image data is not written in the frame memory 6, the image data of the previous frame remains as it is. Image data of each frame is read from the frame memory 6 in the order of raster scanning in block units.

The block selection circuit 7 determines the decoding state of the adjacent block of the non-decoding block based on the decoding level data from the block decoding circuit 4, and determines the block to be used for interpolation. The operation of the block selection circuit 7 will be described below with reference to FIGS.

FIG. 3 is a diagram for explaining the operations of the block selecting circuit 7 and the interpolating circuit 9 in this embodiment. In the figure, each square represents one coding block, and the diagram shows an actual screen. The arrangement is shown. Further, the block B ′ _{x, y} is a block located at the same position in the previous frame # N−1 with respect to the block B _{x, y} of the frame #N.

FIG. 4 is a block diagram showing the structure of the block selection circuit 7.

4, it is assumed that the decoding level data for the block B _{x, y + 1} in FIG. 3 is input to the input terminal 401. DL402, DL403, D
L404 and DL405 are delay circuits for delaying the input decoding level data, and are block B in FIG.
_The delay time is set so that the decoding level data for _{x, y-1} , _{Bx-1, y} , _{Bx + 1, y} , and _{B'x, y} are output. Each of the comparators 406 to 409 has a block B _{x, y}
Block B, which is an upper, lower, left and right block adjacent to
Decoding level data of _{x, y-1} , B _{x-1, y} , B _{x + 1, y} , and B _{x, y + 1} are input, and by comparing with the predetermined threshold value, For a block in which data is decoded, a High level signal (hereinafter, block use flag) indicating that the block can be used for intra-field interpolation is output.

For the block _{B'x, y} of the previous frame,
When this block is interpolated, the correlation between pixels becomes low, so it is not used for interframe interpolation. However,
If all adjacent blocks above, below, to the left and right of the block B _{x, y} cannot be used for intra-field interpolation, intra-field interpolation cannot be performed and therefore it is used for inter-frame interpolation. This determination is performed as follows.

The decoding level data of the block _{B'x, y} of the previous frame is input to the comparator 410, and when it is compared with the threshold value and the block _{B'x, y} is completely decodable, H
If the signal is high level, not completely decodable and is interpolated, a low level signal is output. AND circuit 41
1, the signals obtained by inverting the block use flags of the upper, lower, left, and right blocks adjacent to the non-decodable block are input to the comparator 1, and when all the upper, lower, left, and right blocks cannot be used for intra-field interpolation, that is, the comparator
When all the output signals of 6 to 409 are low level, a high level signal is output. Comparator 410,
The output of the AND circuit 411 is input to the OR circuit 412,
It is output as a block use flag for the block B ′ _{x, y} of the previous frame.

The shift register 413 includes comparators 406 ...
409, the block use flag of each block is input from the OR circuit 412, and sequentially output to the output terminal 414 as data indicating the used block.

Returning to FIG. 2, the motion judging circuit 8 judges the presence or absence of motion of the non-decodable block by using the data of the surrounding blocks, and when it is judged that there is motion, a high level signal (hereinafter, motion). Data) is output. The image data decoded by the block decoding circuit 4 is interpolated by the interpolation circuit 9.
Is input to the CPU, and interpolation is performed based on the error flag, the block use flag, and the motion data. Next, the operation of the interpolation circuit 9 will be described with reference to FIG.

FIG. 5 is a block diagram showing a configuration example of the interpolation circuit 9. Now, from the block decoding circuit 4 to the input terminal 5
It is assumed that the decoded image data of block B _{x, y + 1} in FIG. DL505, DL506, D
L507 is a delay circuit, and blocks B _{x, y-1} and B, respectively.
_The delay time is set so that the decoded image data of _{x-1, y} , B _{x + 1, y} is output. The upper interpolating circuit 508, the upper and lower interpolating circuit 509, and the lower interpolating circuit 510 are a vertical in-field interpolating circuit, a left interpolating circuit 511, and a left and right interpolating circuit 51.
2. The right interpolation circuit 513 is a horizontal in-field interpolation circuit.

The upper interpolation circuit 508 is for the data of block B _{x, y-1} , the lower interpolation circuit 509 is for the data of blocks B _{x, y-1} and B _{x, y + 1} , and the lower interpolation circuit 510 is for the data of block B _{x, y + 1} . To generate interpolation data of block B _{x, y in} the vertical direction, respectively,
The interpolation data is output to the selection switch 514. The left interpolation circuit 511 uses the data of the block B _{x-1, y} , the left and right interpolation circuit 512 uses the data of the blocks B _{x-1, y} and B _{x + 1, y} , and the right interpolation circuit 513 uses the data of the block B _{x + 1, y.} To generate the interpolation data of the block B _{x, y in} the horizontal direction, respectively, and select the switch 515.
Output interpolation data to. Selection switches 514, 515
Selects the vertical / horizontal intra-field interpolation method according to the used block data input to the input terminal 504. If the upper and lower blocks are both unusable and the left and right blocks are both unusable, the switch 51
4,515 are connected to GND. Switches 514, 5
The output of 15 is input to the switches 516 and 517. The switches 516 and 517 switch according to the ratio of blocks used for vertical / horizontal interpolation to all blocks used for intra-field interpolation, and the coefficient multiplication circuit 51
8 to 523 weight the values shown in the figure. The adder 524 adds the weighted vertical / horizontal in-field interpolation data and outputs it to the # 2 side of the selection switch 528.

Image data from the frame memory 6 is input to the input terminal 501. DL502 is a delay circuit, an adder 524 is set the delay time so as to output the block B _'x, the image data of the _y When outputting intra-field interpolation data for a block B _{x, y.}
The DL 502 outputs the decoded image data when the block B _{x, y} can be decoded, and outputs the image data of the block B ′ _{x, y} of the previous frame when the block B _{x, y} cannot be decoded.

The motion data of the block B _{x, y} is input from the motion determination circuit 8 to the input terminal 525. Input terminal 5
An error flag is input to the error correction circuit 2 from the error correction circuit 2 when the error correction impossible data exists in the block B _{x, y} . The output determination circuit 527 controls the selection switch 528 according to the used block data from the input terminal 504, the motion data, and the error flag to determine the output image data to the output terminal 529. Normally, when outputting correctly decoded image data of a block and when outputting inter-frame interpolation data, it is connected to # 1. When outputting the inter-field interpolation data, it is connected to the selection switch 528 # 2.

The intra-field interpolation data is selected in two cases A and B shown in FIG. In FIG. 6, an error flag is a flag indicating whether the block B _{x, y} is decodable or not, and becomes high level when the block B _{x, y} cannot be decoded. The in-field interpolation flag is a flag indicating whether or not in-field interpolation is possible, and when it is possible, it becomes High level. The inter-frame interpolation flag is a flag indicating whether inter-frame interpolation is possible, and if possible, High
It becomes a level. The motion data indicates the presence or absence of motion of the block B _{x, y} , and when there is motion, it becomes High level. "-" Indicates that it does not depend on the state of the flag.

FIG. 7 is a diagram showing a configuration example of the output determination circuit 527 for realizing the determination shown in FIG. In FIG. 7, the input terminal 701 stores the error flag of the block B _{x, y} , the input terminal 702 stores the motion data of B _{x, y} , and the input terminal 70.
A block use flag of a block used for B _{x, y} intra-field interpolation is input to 3. Now input terminal 703
It is assumed that the block use flag for the block B _{x, y + 1} has been input to. This flag is used as an interframe interpolation flag. At this time, the delay circuits DL704,
Blocks 705, 706, and 707 delay the block B _{x, y so} that the block use flags of the block one frame before and the adjacent upper block, left block, and right block are output.

The OR circuit 708 takes the logical sum of the block use flags of the upper, lower, left and right blocks and outputs a high level signal indicating that inter-field interpolation is possible when at least one block is available. This signal is used as an intra-field interpolation flag.

The AND circuit 709 calculates the logical product of the error flag, the motion data, and the intra-field interpolation flag, and
The determination in the case of A is performed. Further, the AND circuit 710 uses an error flag, motion data, in-field interpolation flag,
The logical product of the interpolation flags in the frame is calculated, and the determination in the case of B in FIG. 10 is performed.

The OR circuit 711 is composed of AND circuits 709, 7
The output of 10 is ORed and output to the output terminal 712. The selection switch 528 is connected to the # 1 side when this output is at the Low level, and outputs inter-frame interpolation data,
At the High level, it is connected to the # 2 side and outputs inter-field interpolation data.

As described above, in the present embodiment, by selecting the block to be used for interpolation according to the decoding state of the block adjacent to the non-decodable block, the interpolation is performed using the block having the good decoding state. And it is possible to perform intra-field interpolation even if not all adjacent blocks are decodable. Therefore, it is possible to improve the interpolation image quality.

Next, a second embodiment of the present invention will be described with reference to FIG.
It will be described with reference to FIGS. It should be noted that components having the same or similar functions as those of the first embodiment described above are designated by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 8, the block decoding circuit 4 does not output the decoding level data to the interpolation circuit 9, and the motion determination circuit 7 also outputs the motion information of the corresponding block to the block selection circuit 8.

In this embodiment, the block selection circuit 8
Selects a block to be used for intra-field interpolation based on the motion data from the motion determination circuit 7 and the decoding level data from the block decoding circuit 4. The block selection circuit 8 selects a block that meets any one of the following conditions as a block to be used for the intra-field interpolation, from the upper, lower, left, and right blocks adjacent to the undecodable block.

(A) Decodable block (B) Undecodable block interpolated by interframe interpolation A block that meets any of these conditions is selected. An example of the configuration of the block selection circuit 8 is shown in FIG.

Decoding level data is input to the input terminal 901 from the block decoding circuit 4. Now input terminal 9
Lower block B adjacent to undecodable block at 01
_If the decoding level data of _{x, y + 1} is input,
In the delay circuits DL904, 905, and 906, the comparators 907, 909, and 910 have blocks B _{x, y−1} and B, respectively.
_The delay time is set so as to output the comparison result of _{x-1, y} and B _{x + 1, y} .

Further, the motion data from the motion judging circuit 7 is inputted to the input terminal 902 and inverted by the NOT circuit 903. As described above, the input terminal 902 is the block B.
Assuming that _{x, y + 1} motion data is input, the delay circuits DL911, 912, 913 delay to output inverted motion data of each block adjacent to the undecodable block. The time is set.

DLs 904, 905, and 906 output the decoding level data of the upper, left, and right adjacent blocks of the undecodable block. The comparators 907 to 910 compare the decoding level data of adjacent blocks on the upper, lower, left and right sides of the non-decodable block with a predetermined threshold value to determine whether or not each block is decodable, and the decodable block can be deciphered. If there is, a High level signal is output. In this case, the condition (A) is met. Also, DL91
1, the outputs of the NOT circuits 903, DL912, and DL913 become High level signals when adjacent blocks above, below, left and right of the non-decodable block do not move.
The block determined to have no motion is a part of the block that meets the above condition (A) if it can be decoded, and if it cannot be decoded, it depends on the data of the previous frame. This is a block that meets the above condition (B) because it becomes an image on which inter-frame interpolation has been performed.

The OR circuits 914 to 917 output block use flags for adjacent blocks above, below, left and right of the undecodable block. In the OR circuit 914, the data of the upper block from the comparators 907 and DL911 is ORed.
The lower block data from the comparator 908 and the NOT circuit 903 are stored in the circuit 915, and the comparator 90 is stored in the OR circuit 916.
9, the data of the left block from DL912 is the OR circuit 9
The data of the right block is input to the comparator 17 from the comparators 910 and DL 913, respectively, and a block use flag is output for a block that meets any of the conditions (A) and (B).

The shift register 918 is an OR circuit 914.
The block use flags of the blocks from to 917 are sequentially output to the output terminal 919 as use block data.

FIG. 10 is a diagram showing a configuration example of the interpolation circuit 9. In FIG. 10, the image data from the frame memory 6 is input to the input terminal 1001.
Used block data is input to 3. Then, after performing the interpolation operation as in the case of the above-described first embodiment, the interpolation data of each of the inter-frame interpolation and the intra-field interpolation is output to the selection switch 1028. Input terminal 102
5, the motion data of the undecodable block is input from the motion determination circuit 7, and the error correction circuit 2 is input to the input terminal 1026.
The error flag is input from. Output determination circuit 1027
Controls the selection switch 1028 based on the used block data, the motion data, and the error flag to determine the output image data to the output terminal 1029.

In the present embodiment, the intra-field interpolation data is output in the case shown in FIG. Figure 11
The error flag, the intra-field interpolation flag, and the motion data in are the same as those in FIG. FIG. 12 is a diagram showing a configuration example of the output determination circuit 1027 that determines the output of such intra-field interpolation data. Input terminal 121
, An error flag is input to the input terminal 122, motion data of an undecodable block is input to the input terminal 122, and used block data is input to the input terminal 123. Now, assuming that the block use flag of B _{x, y + 1,} which is the lower adjacent block to the block B _{x, y} , is input to the input terminal 123, at this time, the delay circuits DL124, DL125, and DL126 ,
Delay is performed so that the usage flags of adjacent blocks on the right, left, and upper sides are output.

The OR circuit 127 takes the logical sum of the block use flags of the upper, lower, left and right blocks of the non-decodable block, and when at least one block is available, outputs a high level signal indicating that intra-field interpolation is possible. This signal is used as an intra-field interpolation flag.

The AND circuit 128 calculates the logical product of the error flag, the motion data, and the inter-field interpolation flag, and
The determination of No. 1 is performed, and a High level signal is output to the output terminal 129 when the signal is conforming, and a Low level signal is output when the signal is not conforming. Selection switch 1028
Is connected to the # 1 side to output interframe interpolation data or decoded data when the input signal from the output determination circuit 1027 is at the Low level, and when it is at the High level, #
It is connected to the 2 side and outputs inter-field interpolation data.

As described above, also in the present embodiment, the adjacent block cannot be decoded by selecting the block to be used for interpolation according to the decoding state / interpolation state of the adjacent block of the undecodable block. Even if
In-field interpolation can be performed using image data interpolated by inter-frame interpolation.

[0048]

As is apparent from the above description, the present invention detects the decoding state of the surrounding data when correcting the error data in the correction of the coded image data. The data used for interpolation is selected based on this.

Therefore, even when a part of the surrounding data is not decodable, the usable data can be effectively used to perform the interpolation.

Further, when the image data is data of a block which is divided into a plurality of pixels, the error block is a moving image and even if a part of the surrounding blocks is not decodable, the frame Inter-field interpolation can be performed without interpolating.

Therefore, even the interpolated image is temporally
Spatial discomfort with surrounding images is eliminated, and a better reproduced image can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a data flow in an embodiment of the present invention.

FIG. 2 is a block diagram of an image signal reproducing apparatus according to the first embodiment of the present invention.

FIG. 3 is a diagram for explaining intra-field interpolation in the embodiment of the present invention.

FIG. 4 is a block diagram of a block selection circuit according to an embodiment of the present invention.

FIG. 5 is a block diagram of an interpolation circuit in the embodiment of the present invention.

FIG. 6 is a diagram for explaining the operation of the output determination circuit in the example of the present invention.

FIG. 7 is a block diagram of an output determination circuit according to an embodiment of the present invention.

FIG. 8 is a block diagram of an image signal reproducing device according to a second embodiment of the present invention.

FIG. 9 is a block diagram of a block selection circuit according to a second embodiment of the present invention.

FIG. 10 is a block diagram of an interpolation circuit in the second embodiment of the present invention.

FIG. 11 is a diagram for explaining the operation of the output determination circuit in the second embodiment of the present invention.

FIG. 12 is a block diagram of an output determination circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 4 block decoding circuit 7 block selection circuit 8 motion determination circuit 9 interpolation circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H04N 7/30 H04N 7/133 A

Claims (2)

[Claims] 1. An image reproducing device for decoding encoded image data and reproducing an image, comprising: an interpolation means for interpolating target image data using its surrounding data; and a decoding state of the surrounding data. Detecting means for detecting, and, based on the detection result of the detecting means, a selecting means for selecting data to be used for interpolation from the surrounding data, the interpolation means, the data selected by the selecting means An image reproducing apparatus characterized in that the target image data is interpolated using the image reproducing apparatus. 2. The image reproducing apparatus according to claim 1, wherein the image data is image data of a block that is divided into blocks for each of a plurality of pixels.