JPH07312355A - Semiconductor wafer - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the line width uniformity of a pattern within a semiconductor chip and between semiconductor chips, reduce the variation in characteristics, and improve the yield. The semiconductor chip 13 has an overall planar shape close to a square, but four corners are smooth curved parts, or isosceles right triangle parts of the four corners are cut off. Therefore, even if the resist is spin-coated on the semiconductor wafer after the scribe line is formed on the semiconductor wafer, the coating unevenness 15 in which the resist film thickness is not uniform is reduced. As a result, if the line width of the mask at the time of exposure is uniform, the line width of the resist after development is less uneven.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shape of a scribe line for separating a semiconductor wafer into individual semiconductor chips.

[0002]

2. Description of the Related Art FIG. 2A shows a semiconductor wafer 11. In order to manufacture a semiconductor device with this semiconductor wafer 11, as shown in FIG. 2B, a width S of several tens to 100 μm and a depth of several tens nm to several μm are obtained by performing lithography and etching a plurality of times. Of the semiconductor wafer 1 is formed on the semiconductor chip 13 having a rectangular or square planar shape by forming scribe lines 12 having
Divide 1.

After forming a semiconductor device on each semiconductor chip 13 through the formation of an insulating film, a conductive film, etc., and the subsequent patterning of these films by lithography and etching, individual semiconductor chips 13 are formed along the scribe lines 12. The semiconductor chips 13 are separated from each other, and the separated semiconductor chips 13 are packaged.

[0004]

However, as described above, since the semiconductor chip 13 has a rectangular shape or a square shape in plan view, the interior angles of the vertices of the semiconductor chip 13 are right angles, and the respective semiconductor chips 13 are also rectangular. The scribe line 12 formed between them has a depth of about several μm.

For this reason, when the scribe line 12 is formed and the semiconductor wafer 11 is divided into the semiconductor chips 13, and then a resist is spin-coated on the semiconductor wafer 11, it is shown by broken lines in FIGS. In this manner, the coating unevenness 15 in which the resist film thickness is nonuniform is generated on the straight line extending from the center 14 of the semiconductor wafer 11 to each vertex of each semiconductor chip 13.

When such coating unevenness 15 occurs, the line width of the resist after development is not uniform even if the line width of the mask during exposure is uniform. Therefore, the resist after development is used as a mask. The line width of the wiring formed by etching and the pattern of various regions is also non-uniform. For this reason,
In the conventional example shown in (1), there was a large variation in characteristics within and between semiconductor chips, and the yield was low.

[0007]

A semiconductor wafer 11 according to a first aspect of the present invention is characterized by including a semiconductor chip 13 whose planar shape does not have an apex whose interior angle is a right angle or less.

A semiconductor wafer 11 according to a second aspect of the invention is characterized in that the planar shape is constituted by a smooth curved portion and a linear portion which are concave with respect to the inside of the planar shape.

A semiconductor wafer 11 according to a third aspect is characterized in that the planar shape has the apex with the interior angle being an obtuse angle.

[0010]

In the semiconductor wafer 11 according to the present invention, when the resist is applied in the lithography process for manufacturing the semiconductor device, the resist film thickness is high within the semiconductor chip 13 and between the semiconductor chips 13, and the wiring is And the uniformity of the line width of the pattern in various areas is high.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first and second embodiments of the present invention will be described below with reference to FIG.
Will be described with reference to. The components corresponding to those of the conventional example shown in FIG. 2 are designated by the same reference numerals.

FIG. 1A shows a semiconductor chip 13 included in the semiconductor wafer 11 of the first embodiment. This semiconductor chip 13 has an overall planar shape close to a square, but one conventional structure shown in FIG. 2 except that the four corners are smooth curved parts having a radius of curvature of about several tens to several hundreds of μm. It has substantially the same configuration as the semiconductor chip 13 included in the semiconductor wafer 11 of the example.

In the first embodiment, the semiconductor wafer 1 is manufactured after the semiconductor device manufacturing process progresses and the step between the scribe line 12 and the semiconductor chip 13 becomes large.
Even if the resist is spin-coated on the surface of FIG.
As is clear from the comparison with (c), the coating unevenness 15 in which the resist film thickness is nonuniform is reduced.

As a result, if the line width of the mask at the time of exposure is uniform, there is little nonuniformity in the line width of the resist after development. Therefore, the wiring formed by etching using the resist after development as a mask. Also, there is little non-uniformity in the line width of patterns in various areas. Therefore, in this first embodiment,
The characteristics are small within the semiconductor chip 13 and between the semiconductor chips 13, and the yield is high.

FIG. 1B shows a semiconductor chip 13 included in the semiconductor wafer 11 of the second embodiment. The semiconductor chip 13 has an overall planar shape close to a square, but has a shape in which the right-angled isosceles triangle portions at the four corners are cut off. Therefore, except that it is exactly an octagon. The semiconductor chip 13 included in the conventional semiconductor wafer 11 shown in FIG. 2 has substantially the same structure.

Also in the second embodiment as described above, it is possible to obtain the same effects as those of the first embodiment shown in FIG. In order to make the semiconductor chip 13 have a planar shape as in the first or second embodiment, it should be formed in the mask (reticle) used during exposure in the lithography process for forming the scribe line 12. Semiconductor chip 1
It is only necessary to change the pattern of the light-shielding band in the peripheral portion of No. 3 from the conventional example.

[0017]

In the semiconductor wafer according to the present invention, the line width of the pattern of the wiring and various regions is highly uniform within the semiconductor chip and between the semiconductor chips, so that the characteristic variation is small and the yield is high.

[Brief description of drawings]

1 (a) and (b) are the first and second aspects of the present invention, respectively.
It is a top view of a semiconductor chip contained in a semiconductor wafer of an example.

2A and 2B show a conventional example of the present invention, in which FIG. 2A is a plan view of a semiconductor wafer, FIG. 2B is a side sectional view taken along a scribe line, and FIG. 2C is a plan view of a semiconductor chip.

[Explanation of symbols]

 11 semiconductor wafer 12 scribe line 13 semiconductor chip 15 coating unevenness

Claims (3)

[Claims] 1. A semiconductor wafer comprising a semiconductor chip whose planar shape does not have a vertex whose interior angle is less than or equal to a right angle. 2. The semiconductor wafer according to claim 1, wherein the planar shape is constituted by a smooth curved portion and a linear portion which are concave with respect to the inside of the planar shape. 3. The semiconductor wafer according to claim 1, wherein the planar shape has the apex with the interior angle being an obtuse angle.