JPH07318902A - Display semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the number of input terminals of a display semiconductor device incorporating a pair of vertical drive circuits. [Structure] The display semiconductor device 1 includes a pixel array section 4 that constitutes a screen 3, a peripheral circuit section that drives the pixel array section 4, and a plurality of input terminals 5 that supply signals thereto from the outside. The pixel array unit 4 has pixels arranged in rows and columns. The peripheral circuit section has a vertical driving unit that sequentially selects and drives each row of pixels according to the supplied signal, and a horizontal driving unit that writes and drives the selected pixels in a column-sequential manner. The vertical driving means is a pair of vertical driving circuits 6 and 7 arranged on both sides of the screen 3.
And each row of pixels is selectively driven from both sides simultaneously.
The plurality of input terminals 5 include common input terminals 5a, 5b and 5c which are commonly assigned to both vertical drive circuits 6 and 7. Internal wirings 9R and 9S for connecting the common input terminals 5a, 5b and 5c to the vertical drive circuits 6 and 7 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display semiconductor device used as a drive substrate of an active matrix liquid crystal display device. More specifically, the present invention relates to an external signal input terminal structure provided in a display semiconductor device.

[0002]

2. Description of the Related Art The structure of a conventional display semiconductor device will be briefly described with reference to FIG. As shown, the display semiconductor device has a row-shaped gate line X and a column-shaped signal line Y.
And a pixel array arranged in a matrix at each intersection of the two. Each pixel is, for example, a fine pixel electrode PX.
It consists of L and the thin film transistor Tr which drives this.
A single vertical driving circuit 101 is connected to one end side of each gate line X, and gate pulses V _N , V _{N + 1} ,
V N _{+ 2,} and sequentially applies the ... to the gate line X to selectively drive the pixels in each row. The vertical drive circuit 101 outputs the above-mentioned gate pulse by sequentially transferring the vertical start signal VST in synchronization with externally input clock signals VCK and VCKX. Note that VCK and VCKX are clock signals having opposite polarities. On the other hand, the video line 10 is connected to the end of each signal line Y via the horizontal switch HSW.
2 is connected and the video signal VS input from the outside
Receive IG supply. The horizontal switch HSW is controlled to be opened / closed by the horizontal scanning circuit 103, and sequentially scans each signal line Y to sequentially select the pixels for one row in a column sequential video signal VS.
Write IG. The horizontal scanning circuit 103 outputs a sampling pulse for controlling the opening / closing of the horizontal switch HSW by sequentially transferring the horizontal start signal HST in synchronization with predetermined clock signals HCK and HCKX. The horizontal scanning circuit 103 and the horizontal switch HSW form a horizontal drive circuit.

[0003]

FIG. 6 is an operation timing chart of the conventional display semiconductor device shown in FIG. As shown in the figure, the horizontal start signal HST is input to the horizontal scanning circuit 103 every horizontal period to start writing the video signal to the pixels for one row. On the other hand, the vertical drive circuit 101 outputs a gate pulse every horizontal period by sequentially transferring the vertical start signal VST. The gate pulse basically has a rectangular waveform, but in reality, since the gate line X includes the resistance component r, the waveform is rounded. This rounding becomes more remarkable as the distance from the input side of the vertical drive circuit 101 increases. In the timing chart of FIG. 6, the gate pulses observed in the first row, near the vertical drive circuit 101 side, the intermediate middle row, and the last row on the other end side are shown. In the first row, each gate pulse V _N ,
V _{N + 1} , V _{N + 2} , ... Have a substantially rectangular shape and are temporally separated from each other. However, in the middle row, the waveform of the gate pulse becomes blunt due to the resistance component included in the gate line X. In particular, the resistance component r is added in series in the final row, which is a worst case condition, and the waveform blunting is remarkable and the preceding gate pulse V _N and the subsequent gate pulse V _{N + 1} overlap each other. Similarly, V _{N + 1} and V _{N + 2} also overlap. In such a state, there is a problem that shading occurs in a displayed image or a video signal is mixed between rows of pixels, which significantly deteriorates image quality.

In particular, when a bidirectional type is adopted as the horizontal scanning circuit 103 shown in FIG. 5, signal mixing becomes remarkable. In the bidirectional type, each signal line Y is connected along a forward direction (right direction in the figure) from one end side of the gate line X or a reverse direction (left direction in the figure) from the other end side to one end side. Sequential scanning is performed to enable left-right inverted display of images. This left-right inversion function becomes necessary when the active matrix liquid crystal display device is applied to a light valve of a projector, for example. As described above, since the resistance component r is added in series in the last row, it becomes a worst case condition, the waveform rounding is remarkable, and the leading gate pulse and the trailing gate pulse overlap each other. In such a state, there arises a problem when the backward dot sequential scanning is performed on the pixel row. As shown in the timing chart of FIG. 6, when for example, the gate pulse V _N Advance does not fall up completely, the gate pulse V _{N + 1} of the next onset are starting up. At this time, the horizontal start signal HST
Is input to start writing the video signal to the pixels in the (N + 1) th row. However, since the preceding gate pulse V _N has not yet fallen at the time when HST is input, the video signal is written to the pixels in the Nth row. As a result, another video signal assigned to the (N + 1) th row is written in the pixel of the Nth row, and signal mixing occurs.

FIG. 7 schematically shows the mixing of the above video signals. As described above, in the case of forward scanning, since the horizontal start signal HST is input in a state where the gate pulse is not rounded, there is no fear of mixing video signals.
However, in the case of reverse scanning, since writing starts from the final stage column side where the gate pulse becomes noticeable, an overlap occurs at the input time of the horizontal start signal HST and the falling time point of the gate pulse of the preceding row. Will end up. As a result, the video signal assigned to the row is written in the preceding row pixel, and as shown in the figure, the image signal is disturbed by the mixing of the video signals on the right end side of the screen.

In order to prevent the rounding of the gate pulse as described above, a structure in which vertical drive circuits are provided on both sides of the gate line is also considered, and an example thereof is shown in FIG. This display semiconductor device includes a pixel array section that constitutes a screen 201, a peripheral circuit section that drives the pixel array section, and a plurality of input terminals 202 that supply signals to the pixel circuit section from the outside. The pixel array portion has pixels arranged in rows and columns. The peripheral circuit section has a vertical drive unit that sequentially selects and drives each row of pixels in accordance with the supplied signal, and a horizontal drive unit that writes and drives the selected pixels in column order. Vertical drive means screen 201
A pair of vertical drive circuits 203, 204 arranged on both sides of the
And each row of pixels is selectively driven from both sides simultaneously.
On the other hand, the horizontal driving means is composed of a single horizontal driving circuit 205.

In the display semiconductor device described above, an input terminal is provided independently for each of the pair of vertical drive circuits 203 and 204. In the example of FIG. 8, input terminals a, b, and c are provided for one vertical drive circuit 203,
A vertical start signal or vertical clock signal was input.
For the other vertical drive circuit 204, input terminals d,
e and f are provided, and the vertical start signal and the vertical clock signal are similarly input.

However, in the above-mentioned configuration, by providing two vertical drive circuits, shading and mixing of image signals can be prevented, but the number of input terminals is increased as compared with the configuration having a single vertical drive circuit. Other drawbacks have come to the fore. First, since the area occupied by the input terminals with respect to the substrate forming the display semiconductor device is increased, it is more susceptible to static electricity damage. Second, as the number of input terminals increases, the number of inspection steps increases accordingly, which is disadvantageous in the manufacturing process. Thirdly, the number of internal wirings that connect the input terminals and the drive circuit section increases, and defects easily occur in the assembly and mounting process.

[0009]

In view of the above-mentioned problems of the conventional technique, the present invention makes it possible to integrally form a pair of vertical drive circuits in a display semiconductor device without increasing the number of input terminals. With the goal. The following measures have been taken in order to achieve this object. That is, the display semiconductor device according to the present invention has, as a basic configuration, a pixel array section that constitutes a screen, a peripheral circuit section that drives the pixel array section, and a plurality of externally supplied signals to the peripheral circuit section. And an input terminal of. The pixel array unit has pixels arranged in rows and columns.
The peripheral circuit portion has a vertical driving means for selectively driving each row of pixels in accordance with the supplied signal, and a horizontal driving means for writing-driving the selected pixels in column order. The vertical driving means includes a pair of vertical driving circuits arranged on both sides of the screen, and selectively drives each row of pixels from both sides at the same time. As a feature of the present invention, the plurality of input terminals include a common input terminal commonly assigned to both vertical drive circuits. Further, an internal wiring for connecting the common input terminal to each vertical drive circuit is provided. The display semiconductor device having such a configuration is used, for example, as a drive substrate of an active matrix type liquid crystal display device.

In the embodied invention, the internal wiring directly connects the shared input terminal to one vertical driving circuit, and indirectly connects to the other vertical driving circuit through the one vertical driving circuit. And indirect internal wiring. In another specific example, the internal wiring has branch internal wiring for branch-connecting the common input terminal to both vertical drive circuits. Further, in addition to the branch internal wiring, an auxiliary internal wiring for auxiliary connecting both vertical drive circuits to each other is provided.

[0011]

In the present invention, a pair of vertical drive circuits are arranged on both sides of the screen, and each row of pixels is selectively driven from both sides at the same time. As a result, image shading and mixing of video signals can be suppressed, and image quality can be significantly improved, as compared with a system in which a single vertical drive circuit drives from one side of the screen. Further, a common input terminal commonly assigned to both vertical drive circuits is provided, and an internal wiring for connecting the common input terminal to each vertical drive circuit is provided. As a result, the number of input terminals can be reduced as compared with the conventional example in which independent input terminals are separately provided, which is advantageous in terms of manufacturing process, quality, and reliability. In this case, it is important to reduce the resistance of the internal wiring, so that the start signal and the clock signal can be supplied to both vertical drive circuits at the same timing. As a result, both vertical drive circuits can operate in synchronization with each other, and selective drive of each pixel row that is timing-matched can be performed. In particular, since the vertical drive circuit uses a clock signal having a lower frequency than that of the horizontal drive circuit, problems such as signal delay due to internal wiring are not caused.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic plan view showing a first embodiment of a display semiconductor device according to the present invention. As shown in the figure, the display semiconductor device 1 is configured by using an insulating substrate 2 such as quartz or glass, and includes a pixel array section 4 included in a screen 3, a peripheral circuit section for driving the pixel array section 4, and an external circuit. A plurality of input terminals 5 for supplying a signal from the are integratedly formed.

The pixel array section 4 has pixels arranged in rows and columns. Each pixel includes a pixel electrode PXL and a switching thin film transistor Tr. Further, the gate lines X are arranged in rows and the signal lines Y are arranged in columns. The gate electrode of each thin film transistor Tr is connected to the corresponding gate line X, the source electrode is connected to the corresponding signal line Y, and the drain electrode is connected to the corresponding pixel electrode PXL.

The peripheral circuit section has vertical drive means for selectively driving each row of pixels in response to a signal supplied from the input terminal 5, and horizontal drive means for writing and driving the selected pixels in column order. There is. In the present invention, the vertical driving means is composed of a pair of vertical driving circuits 6 and 7 arranged on both left and right sides of the screen 3, and selectively drives each row of pixels from both sides simultaneously. Specifically, the first vertical drive circuit 6 is connected to the left end side of the gate line X, while the second vertical drive circuit 7 is connected to the right end side of the gate line X. Both vertical drive circuits 6 and 7 sequentially output gate pulses at the same timing to open / close the thin film transistors Tr for each row to perform the selective drive of the pixels described above. Since the gate pulses are input simultaneously from both sides of each gate line X, overlapping which is a conventional problem due to waveform rounding is suppressed. On the other hand, the horizontal drive means is composed of a single horizontal drive circuit 8 and is connected to one end of the signal line Y. The horizontal drive circuit 8 samples and distributes a video signal supplied from the outside through the input terminal 5 to each signal line Y, and drives the selected pixels in a column sequential writing mode.

As a feature of the present invention, the plurality of input terminals 5 include common input terminals 5a, 5b and 5c which are commonly assigned to both vertical drive circuits 6 and 7. These common input terminals 5a, 5b and 5c supply a vertical start signal and vertical clock signals having mutually opposite polarities to the vertical drive circuits 6 and 7. Although not shown,
A common input terminal for supplying a power supply voltage to the vertical drive circuit is also provided. In addition, input terminals 5d, 5e, 5 for supplying a predetermined signal and power supply voltage to the horizontal drive circuit 8
f, ... Are also provided. Shared input terminals 5a, 5b,
Reference numeral 5c is connected to each vertical drive circuit 6 and 7 using internal wiring. In this embodiment, the common input terminals 5a, 5b, 5
Direct internal wiring 9 for directly connecting c to the first vertical drive circuit 6
R and the second vertical drive circuit 7 via the first vertical drive circuit 6
And an indirect internal wiring 9S that is indirectly connected to. That is, a signal applied to the common input terminals 5a, 5b, 5c from an external timing generator (not shown) or the like is first directly supplied to the first vertical drive circuit 6 via the internal wiring 9R to control its operation. To do. Next, the signal is transferred to the second vertical drive circuit 7 via the indirect internal wiring 9S after passing through the first vertical drive circuit 6. Since the indirect internal wiring 9S is longer than the direct internal wiring 9R, there is a concern that the resistance may be increased. However, since the lower side of the normal screen 3 is often a dead space, wide wiring using, for example, aluminum or aluminum alloy is possible, and the resistance value can be sufficiently lowered. Therefore, when a clock signal having a low frequency is used as in the vertical drive circuit, the delay in signal transfer does not substantially pose a problem, and the first vertical drive circuit 6 and the second vertical drive circuit 7 are sufficiently synchronized in timing. is doing.

In the present invention, the common input terminals 5a, 5b and 5c are assigned to both the vertical drive circuits 6 and 7, and the independent input terminals shown in FIG. 8 are assigned to the respective vertical drive circuits. It has the following advantages. First, since the number of input terminals connected to the vertical drive circuit is reduced, the area of the input terminals occupying the insulating substrate 2 is reduced, and it becomes stronger against electrostatic damage. Moreover, since the number of input terminals is reduced, the inspection process can be shortened. Further, it is possible to drive by using the same timing generator as the timing generator connected to the display semiconductor device incorporating the single vertical drive circuit shown in FIG. In addition, since the common input terminal is used, the first vertical drive circuit 6
Therefore, no relative delay appears in the operation timing of the second vertical drive circuit 7. As can be understood from the above description, the image quality superior to that of the single vertical drive circuit configuration can be realized without the problems that have been conventionally caused by the pair of vertical drive circuit configurations.

FIG. 2 is a schematic plan view showing a second embodiment of the display semiconductor device according to the present invention. The basic structure is the same as that of the first embodiment shown in FIG. 1, and corresponding parts are designated by corresponding reference numerals to facilitate understanding.
The difference is that the shared input terminals 5a, 5b and 5c are branched and connected to both vertical drive circuits 6 and 7 using a branch internal wiring 9T. By doing so, the first vertical drive circuit 6 and the second vertical drive circuit 7 share the common input terminals 5a, 5b,
5c can be connected under substantially equal conditions, and the operation timings of both can be perfectly synchronized.

FIG. 3 is a schematic plan view showing a third embodiment of the display semiconductor device according to the present invention. Basically, it is the same as the second embodiment shown in FIG. 2, and corresponding parts are designated by corresponding reference numerals to facilitate understanding. A different point is that, in addition to the branch internal wiring 9T, an auxiliary internal wiring 9P for auxiliary connecting the vertical drive circuits 6 and 7 to each other is provided. In this way, by utilizing the dead spaces left above and below the screen 3, the pair of vertical drive circuits 6 and 7 are
It is possible to further reduce the resistance by dually interconnecting the pair of internal wirings 9T and 9P.

Finally, FIG. 4 is a schematic sectional view showing an example of an active matrix type liquid crystal display device assembled by using the display semiconductor device according to the present invention. As shown in the figure, the liquid crystal display device has a panel structure including a drive substrate, a counter substrate 21, and a liquid crystal 22 held between them. As the drive substrate, for example, the display semiconductor device 1 shown in FIG. 1 is used. That is, a pair of vertical drive circuits 6 and 7 and a pixel array portion forming a screen are integrally formed on the inner surface of the drive substrate. The pixel array section includes pixel electrodes PXL arranged in rows and columns and corresponding switching thin film transistors Tr. On the other hand, the counter electrode 23 is entirely formed on the inner surface of the counter substrate 21. Counter substrate 2
1 and the drive substrate are attached to each other by a sealing material 24. Although not shown, the input terminal is arranged outside the sealing material 24. Therefore, a part of the wiring that connects the outer input terminal and the inner drive circuit portion crosses the sealing material 24. In the present invention, since the input terminals are partially shared, the number of wirings that cross the sealing material can be reduced,
Problems such as liquid crystal leakage and seal breakage that occur during panel assembly are also reduced.

[0020]

As described above, according to the present invention, a pair of vertical driving circuits are arranged on both sides of the screen to selectively drive each row of pixels from both sides simultaneously. At this time, the shared input terminal is commonly assigned to both vertical drive circuits, and an internal wiring for connecting the shared input terminal to each vertical drive circuit is provided. With such a configuration, it is possible to improve the display image quality as compared with the single vertical drive circuit configuration. Further, it is advantageous in terms of countermeasures against static electricity as compared with a structure in which input terminals are provided independently of each other for a pair of vertical drive circuits. Also, the inspection process can be shortened. Further, it is possible to reduce defects that occur when the liquid crystal panel is assembled and mounted. In addition, the degree of freedom in designing peripheral circuits such as the timing generator is increased. Finally, the degree of freedom in designing the layout of the display semiconductor device itself is increased.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of a display semiconductor device according to the present invention.

FIG. 2 is a schematic plan view showing a second embodiment of the display semiconductor device according to the present invention.

FIG. 3 is a schematic plan view showing a third embodiment of the display semiconductor device according to the present invention.

FIG. 4 is a schematic cross-sectional view showing an example of an active matrix type liquid crystal display device assembled by using the display semiconductor device according to the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional display semiconductor device.

FIG. 6 is a timing chart for explaining the operation of the conventional example shown in FIG.

FIG. 7 is a schematic diagram for explaining the problems of the conventional example shown in FIG.

FIG. 8 is a schematic plan view showing another example of a conventional display semiconductor device.

[Explanation of symbols]

 1 Display Semiconductor Device 2 Insulating Substrate 3 Screen 4 Pixel Array Section 5 Input Terminal 5a Shared Input Terminal 5b Shared Input Terminal 5c Shared Input Terminal 6 First Vertical Drive Circuit 7 Second Vertical Drive Circuit 8 Horizontal Drive Circuit 9R Direct Internal Wiring 9S Indirect internal wiring 9T Branch internal wiring 9P Auxiliary internal wiring 21 Counter substrate 22 Liquid crystal

Claims (5)

[Claims] 1. A pixel array section comprising a screen, a peripheral circuit section for driving the pixel array section, and a plurality of input terminals for supplying signals to the peripheral circuit section from the outside. The unit has pixels arranged in rows and columns, and the peripheral circuit unit has vertical driving means for selectively driving each row of pixels in accordance with a supplied signal, and horizontal driving means for writing-driving the selected pixels in column order. In the display semiconductor device having, the vertical driving means is composed of a pair of vertical driving circuits arranged on both sides of the screen, and simultaneously selectively drives each row of pixels from both sides, and the plurality of input terminals are A display semiconductor device including a shared input terminal commonly assigned to both vertical drive circuits, and having an internal wiring for connecting the shared input terminal to each vertical drive circuit. 2. The internal wiring includes a direct internal wiring that directly connects the shared input terminal to one vertical drive circuit and an indirect internal wiring that indirectly connects to the other vertical drive circuit through the one vertical drive circuit. The display semiconductor device according to claim 1, further comprising: 3. The display semiconductor device according to claim 1, wherein the internal wiring has a branch internal wiring for branch-connecting the shared input terminal to both vertical drive circuits. 4. The display semiconductor device according to claim 3, wherein the internal wiring has an auxiliary internal wiring that auxiliary-connects both vertical drive circuits to each other in addition to the branch internal wiring. 5. A panel structure having a driving substrate, a counter substrate, and liquid crystal held between the driving substrate and the counter substrate, wherein the driving substrate drives a pixel array portion forming a screen and the pixel array portion. A liquid crystal display device having a peripheral circuit section and a plurality of input terminals for supplying signals to the peripheral circuit section from the outside, wherein the pixel array section has pixels arranged in rows and columns. Has a vertical drive means for selectively driving each row of pixels in accordance with the supplied signal and a horizontal drive means for writing and driving the selected pixels in a column-sequential manner, and the vertical drive means are provided on both sides of the screen. Each row of pixels is selectively driven from both sides by a pair of arranged vertical drive circuits, and the plurality of input terminals include common input terminals commonly assigned to both vertical drive circuits. Input terminal The liquid crystal display device, characterized in that provided inside wiring connected to the vertical drive circuit.