JPH0731909B2 - Method of operating semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a method of operating a semiconductor memory device, wherein a minute difference voltage between bit lines generated by reading information stored in a memory cell is applied to a sense amplifier. After capturing, the charge / discharge current of the bit line is reduced to about 1/2 by operating only the bit line on the side to which the read memory cell is connected.

[Industrial application field]

The present invention is a one-transistor / one-capacitor type dynamic random access memory.
The present invention relates to improvement of a method of operating a semiconductor memory device known as ccess memory (DRAM).

[Conventional technology]

Generally, in a one-transistor / one-capacitor type DRAM, a minute signal is read as a difference voltage between a pair of bit lines, so that bit lines are formed electrically and symmetrically. There is.

FIG. 5 is an explanatory diagram of a main circuit for explaining a conventional semiconductor memory device.

In the figure, BL and ▲ ▼ are bit lines, WL ₀ and WL ₁ are word lines, MC ₁ and MC ₂ are memory cells, C ₁ and C ₂ are information storage capacitors, and SA is a sense amplifier. There is.

FIG. 6 is a timing chart for explaining the operation timing of the semiconductor memory device shown in FIG.
The same symbols as those used in the drawings indicate the same parts or have the same meanings.

In the figure, V _CC is the positive power supply voltage, and V _SS is the ground power supply voltage.

The information read operation in such a semiconductor memory device is well known, and its outline will be described below with reference to FIGS. 5 and 6.

Initially, precharge bit line BL and ▲ ▼ to 1 / 2V _CC .

Next, for example, the level of the word line WL ₀ is raised and the memory cell MC ₁ is selected.

The level of the information storage capacitor C _{1 in} the memory cell MC ₁ is VV _SS , for example, 0 [V] when the information “0” is stored, and the information “1” is stored. In this case, it is V _CC , for example, 5 [V].

The information is read out as a minute difference voltage to the bit lines BL and {circle around ()}, and then the sense amplifier SA operates to amplify the difference voltage.

[Problems to be solved by the invention]

As can be seen from the above description, in the conventional semiconductor memory device, even if a memory cell connected to the bit line BL is selected as a read target, the bit line BL and the bit line BL It is charged and discharged in the same manner as.

The reason for doing so is that the word line WL ₀
Bit line BL and ▲
▼ A difference voltage is generated between the two, but this is because the difference voltage is extremely small.

That is, in general, the capacity of the bit line is about 10 times as large as the capacity of the memory cell. Therefore, even if the accumulated charge of the memory cell is discharged to the bit line, the difference voltage between the bit lines does not change during reading. It is small, and therefore, there is a high possibility that it will be buried in noise.

Therefore, the bit lines BL and {circle around ()} are folded and operated symmetrically. Therefore, the bit lines which are unnecessary for reading information itself are also operated.

However, in recent years, the 1M-bit
In DRAM, there are about 4000 pairs of bit lines, that is, 80
Since there are as many as 00 lines, the current consumption due to charging and discharging is extremely large, and 4000 of them are not directly involved in reading information.

The present invention has a structure in which the operation of a bit line paired with a bit line to which a memory cell to be read is connected can be prohibited from a certain point in time to reduce current consumption. Provide a storage device.

[Means for solving problems]

In the method of operating a semiconductor memory device according to the present invention, two bit lines (for example, bit lines) to which memory cells (for example, memory cells MC ₁ MC ₂ ) are connected and which are charged to an intermediate potential of a power supply voltage. BL and ▲ ▼) are connected to a sense amplifier (for example, sense amplifier SA) and gate transistors (for example, bit line disconnection and connection transistors Q1 and Q2) are turned on at the time of reading a memory cell to sense both bit lines. A memory which is electrically connected to an amplifier and then amplified with a difference voltage (eg, α in 1 / 2V _CC ± α) in the sense amplifier with the gate transistor turned off, and then read cells (e.g., memory cell MC ₁₎ is the gate tiger side corresponding in order to conduct only the bit lines of the side connected (eg, bit line BL) and the sense amplifier Register (e.g. bit cutting and connection transistors Q1) is to be turned on.

[Action]

By adopting the above-mentioned means, after the minute difference voltage between the bit lines generated by reading the information stored in the memory cell is taken into the sense amplifier, the read memory cell is connected. Since only the bit line on the operating side is operated, the charge / discharge current of the bit line can be reduced to about 1/2, which is suitable for operating a large-scale semiconductor memory device.

〔Example〕

FIG. 1 is a circuit diagram of an essential part of an embodiment of the present invention.
The same symbols as those used in the figures indicate the same parts or have the same meanings.

In the figure, Q1 and Q2 are bit line disconnection and connection transistors, φL is a control signal for the transistor Q1, φR is a control signal for the transistor Q2, and N1 and N2 are nodes.

As is clear from the figure, in this embodiment, a transistor is provided between the sense amplifier SA and the bit line BL and ▲ ▼.
By interposing Q1 and Q2 and turning on / off the transistors Q1 and Q2, the bit lines BL and ▲ ▼ can be connected to or cut off from the sense amplifier SA. This is different from the conventional example shown in FIG.

FIG. 2 shows a timing chart for explaining the operation timing in the embodiment of the present invention shown in FIG. 1, which is the same as the symbols used in FIGS. 1, 5, and 6. Symbols indicate the same part or have the same meaning.

The operation of the embodiment of the present invention shown in FIG. 1 will be described with reference to the timing chart shown in FIG. still,
In the present embodiment, information “0” is stored in the information storage capacitor C ₁ of the memory cell MC ₁ selected for reading information,
That is, it is assumed that V _SS (for example, 0 [V]) is accumulated as the level.

Initially, the levels of the control signals φL and φR are raised to V _CC + Vth or more to turn on the transistors Q1 and Q2.

Next, pre-charge is performed and bit line BL and ▲
▼ Bring nodes N1 and N2 to the level of 1/2 V _CC .

Next, the level of the word line WL ₀ is raised and the memory cell M
Select C ₁ .

Since the level of the information storage capacitor C ₁ is V _SS , the charge flows into the memory cell MC ₁ from the bit line BL, so that the level of the bit line BL is slightly lowered and the transistor Q 1 is turned on. Therefore, the bit line BL and the node N1 are connected to each other, and thus the level of the node N1 also drops.

In such a state, a differential voltage is generated between the nodes N1 and N2.

Next, the levels of the control signals φL and φR are lowered, and accordingly the transistors Q1 and Q2 are turned off.

Next, the sense amplifier SA is activated to amplify the voltage difference between the nodes N1 and N2.

Due to this operation, the level of the node N1 becomes V _SS , and the level of the node N2 maintains 1 / 2V _CC .

Next, the active restore circuit (not shown) is activated to raise the level at the node N2 to V _CC .

Next, in order to turn on the transistor Q1 interposed bit line BL on the side where the memory cell MC ₁ selected connected again raises the control signal .phi.L. Incidentally, in order to select and raise only the control signal φL in this way, it can be easily carried out if the memory cell MC ₁ is selected based on the selected address signal.

The level at the bit line BL is 1 / 2V _CC as described above.
Although it is in a slightly lower state, the level at the node N1 is V _SS , and when the transistor Q1 is turned on, electric charge flows from the bit line BL to the node N1. As a result, the level of the bit line BL is increased. Since it also becomes V _SS , the information “0” is written again in the memory cell MC ₁ .

On the bit line ▲ ▼ side, since the level of the control signal φR is V _SS , the transistor Q2 is cut off.
It remains off, the level remains unchanged at 1/2 V _CC , and charging / discharging is not performed, so current consumption is reduced.

By the way, the sense amplifier SA in the semiconductor memory device shown in FIG. 1 is actually a flip-flop, so that the difference voltage between the bit line BL and {circle around (1)} is amplified.

The flip-flop leaves the high level (“H” level) side of the bit lines BL and ▲ ▼,
The low level (“L” level) side can be set to V _SS . Therefore, in a normal semiconductor memory device, it is necessary to raise the level of the bit line on the "H" level side later, and the active restore circuit does this.

Conventionally, the active restore circuit is provided in the sense amplifier, and although not shown,
In the embodiment shown in the figure, it is also installed in the sense amplifier SA.

With such a configuration, the levels of the control signals φL and φR for operating the transistors Q1 and Q2 are set to V _CC + Vth
It is necessary to be above.

The reason is, at operation of the Figure 1 and the semiconductor memory device described in regard to FIG. 2, if at the level at the node N1 becomes V _CC, to convey the level comprising the V _CC to the bit lines BL In order to turn on the transistor Q1, the control signal φL applied to the gate of the transistor Q1 must be V _CC + Vth or more.

However, it is troublesome to use a bootstrap circuit to obtain a voltage higher than the power supply voltage.

In order to avoid such complication in the embodiment shown in FIG. 1, the embodiment described below may be used.

FIG. 3 is a circuit diagram for explaining a main part of another embodiment of the present invention. The same symbols as those used in FIGS. 1 and 2 indicate the same parts or have the same meanings. And

In the figure, AR ₁ and AR ₂ are active restore circuits,
φARL and φARR indicate control signals of the active restore circuit, respectively.

As is apparent from the figure, in this embodiment, the active restore circuits AR ₁ and AR ₂ are provided outside the sense amplifier SA and connected to the corresponding bit lines BL and ▲ ▼, respectively. It differs from the example found in.

FIG. 4 shows a timing chart for explaining the operation timing in the embodiment shown in FIG. 3, and whether the same symbols as those used in FIGS. 1 to 3 indicate the same parts. Or they have the same meaning.

The operation of the embodiment of the present invention shown in FIG. 4 will be described with reference to the timing chart shown in FIG. still,
In this embodiment, information "1" is stored in the information storage capacitor C ₁ of the memory cell MC ₁ selected for reading information.
That is, it is assumed that V _CC (for example, 5 [V]) is accumulated as the level.

Initially, the levels of the control signals φL and φR are raised to V _CC to turn on the transistors Q1 and Q2.

Next, pre-charge is performed and bit line BL and ▲
▼ Bring nodes N1 and N2 to the level of 1/2 V _CC .

Next, the level of the word line WL ₀ is raised and the memory cell M
Select C ₁ .

Since the level of the information storage capacitor C ₁ is V _CC , the charge is discharged from the memory cell MC ₁ to the bit line BL,
Therefore, the level of the bit line BL rises slightly, and since the transistor Q1 is turned on, the bit line BL
And node N1 are connected and therefore node
The N1 level will increase as well.

In such a state, a differential voltage is generated between the nodes N1 and N2.

Next, the levels of the control signals φL and φR are lowered, and accordingly the transistors Q1 and Q2 are turned off.

Next, the sense amplifier SA is activated to amplify the difference voltage between the nodes N1 and N2.

Due to this operation, the level of the node N2 becomes V _SS , and the level of the node N1 maintains 1 / 2V _CC + α.

Next, in order to turn on the transistor Q1 interposed bit line BL on the side where the memory cell MC ₁ selected connected again raises the control signal .phi.L. The control signal φL
It goes without saying that the level of is V _CC .

The level at bit line BL is slightly higher than 1 / 2V _CC , and the level at node N1 is also 1 / 2V _CC.
Since it is in a slightly higher state, the level of the bit line BL does not change even if the transistor Q1 is turned on.

Next, in order to raise the level of the bit line BL on the side to which the selected memory cell MC ₁ is connected, the control signal φARL
To activate the active restore circuit AR ₁ .

Due to the action of the active restore circuit AR ₁ , the bit line BL is charged up from 1 / 2V _CC + α to V _CC ,
Information "1", V _CC, is stored again in the memory cell MC ₁ .

Bit line ▲ ▼
On the side, since the level of the control signal φR is V _SS , the transistor Q2 remains cut off, and the level of the control signal φARR is also V _SS , so the level is
Charging / discharging is not performed while maintaining 1 / 2V _CC .

〔The invention's effect〕

In a method of operating a semiconductor memory device according to the present invention, a memory cell is connected and a gate transistor connecting two bit lines charged to an intermediate potential of a power supply voltage to a sense amplifier is read out from the memory cell. Sometimes it is turned on to bring both of the bit lines into conduction with the sense amplifier, and then the sense amplifier amplifies the difference voltage with the gate transistor turned off, after which the memory In order to make only the bit line on the side to which the cell is connected conductive with the sense amplifier, the gate transistor on the corresponding side is turned on.

By adopting the above configuration, after the minute difference voltage between the bit lines generated by reading the information stored in the memory cell is taken into the sense amplifier, the read memory cell is connected. Since only the bit line on the operating side is operated, the charge / discharge current of the bit line can be reduced to about 1/2, which is suitable for operating a large-scale semiconductor memory device.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a main circuit of an embodiment of the present invention, FIG. 2 is a timing chart for explaining operation timing in the embodiment shown in FIG. 1, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a timing chart for explaining the operation timing in the embodiment shown in FIG. 3, and FIG. 5 is a main circuit diagram for the conventional example. , FIG. 6 are timing charts for explaining the operation timing in the conventional example shown in FIG. In the figure, BL and ▲ ▼ are bit lines, WL ₀ and WL ₁ are word lines, MC ₁ and MC ₂ are memory cells, C ₁ and C ₂ are information storage capacitors, SA is a sense amplifier, Q1 and Q2. Is a transistor for disconnecting and connecting the bit line, φL is a transistor Q1
Control signal, φR is the control signal for transistor Q2, N1 and
N2 indicates each node.

Continuation of the front page (56) Reference JP-A-58-171789 (JP, A) JP-A-60-239993 (JP, A) JP-A-60-256998 (JP, A) JP-A-61-5496 (JP , A) JP 60-212894 (JP, A) JP 54-101229 (JP, A)

Claims (1)

[Claims] 1. A gate transistor that connects two bit lines connected to a memory cell and charged to an intermediate potential of a power supply voltage to a sense amplifier is turned on when the memory cell is read, and the two bit lines are turned on. And the bit line on the side to which the read memory cell is connected, after which the differential voltage is amplified by the sense amplifier with the gate transistor turned off. A method for operating a semiconductor memory device, characterized in that the gate transistor on the corresponding side is turned on in order to bring only the gate transistor into conduction with the sense amplifier.