JPH07319763A - Address converter - Google Patents

Abstract

PURPOSE:To provide an address converter having a simple constitution which freely rotates and outputs a picture even in the case or the address space or a controller smaller than a frame memory. CONSTITUTION:A control circuit 14 sets offset signals Hoff and Voff, which change addresses in the horizontal and vertical directions of the storage area of a frame memory 12, to offset registers 20H and 20V in accordance with rotation of the picture read out from the frame memory 12. Addresses A0 to A9 and A10 to A13 which designate a window of the storage area of the frame memory 12 are outputted to outputs 110 and 112 respectively, and a vertical/ horizontal switching signal (ADRBLV) which controls address selection in address selectors 18H and 18V is outputted to an output 118. Offset signals Hoff and Voff and addresses A0 to A9 and A10 to A13 are added by adders 22H and 22V respectively, and address signals as operation results are given to the frame memory 12, and picture data expressing the rotated picture is read out and is outputted to a bus 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address conversion device for converting a storage address of image data stored in a frame memory, and to an image forming device for forming an image represented by the image data on a medium such as recording paper. The present invention relates to an address translation device suitable for use.

[0002]

2. Description of the Related Art In recent years, image data representing an image of an object obtained from an electronic device such as an electronic still camera has been stored in a frame memory and read out.
Since the size of the image data to be stored in this frame memory has increased due to the increase in the pixel density of the image sensor in recent electronic still cameras, a frame memory having a large storage capacity has been required. The image data stored in this frame memory can rotate the image represented by the image data by controlling the vertical and horizontal reading directions. For example, when image data representing an image such as a natural image is stored in the frame memory, a control circuit such as a microprocessor (Microprocessor) that controls the reading of the image data can read the image data from the frame memory at the same angle. It can be controlled to read. The control circuit reverses the vertical and horizontal read addresses so that, for example, the image data is rotated 90 ° counterclockwise and read, and the read image data is output to a display or printer to form an image represented by the image data. Can be made. Thereby, for example, an image rotated on the recording paper can be obtained without changing the setting direction of the recording paper on which the image is formed in the printer. Further, the image represented by the image data taken by rotating the camera by 90 ° can be output from the printer as an image of an erect image corresponding to the vertical direction of the recording paper.

[0003]

However, in such a frame memory, an address line for designating a storage address of image data is required for the storage capacity of the frame memory. Therefore, continuous data in the horizontal direction is changed in the vertical direction. When reading, there is a problem that the control circuit having an address space smaller than the address space of the frame memory cannot continuously read the image data. Therefore, for example, when an image represented by image data is recorded at a desired angle on a recording paper such as a postcard, there is a problem that the image cannot be easily rotated. Further, for example, the image is rotated, so that the address space cannot be rotated. There is a problem that a large control circuit is required.

In view of the above-mentioned problems of the prior art, the present invention provides a control circuit for supplying an address to a frame memory even if the address space of the control circuit is smaller than that of the frame memory.
It is an object of the present invention to provide an address conversion device having a simple structure in which image data can be freely rotated and read from a frame memory.

[0005]

In order to solve the above problems, the present invention provides an address conversion device for converting an address signal designating a predetermined storage area of a storage means for storing data such as image data. The apparatus comprises control means for generating an address designating a window in an address space smaller than the address space of the storage area, the control means comprising a first address according to a horizontal direction of the window and a first address according to a vertical direction of the window. Generate 2 addresses, this first
Address generating means for outputting the first address line and the second address line to the first address line and the second address line, respectively, and an offset value for shifting the address generated by the address generating means by a predetermined value. And offset selecting means for generating a selection signal for selecting the first address and the second address output to each of the first address line and the second address line. The device further includes a selection circuit for selectively connecting the first address line and the second address line to the first selection output and the second selection output, respectively, in response to the selection signal generated by the address selection means. Means and the offset value generated by the offset generation means, the horizontal address in the storage area of the storage means is changed. First setting means for setting the offset value to, and a second of setting an offset value for displacing the vertical address in the storage area of the storage means
And a first adding means for calculating the address signal designating the lateral address of the storage means by calculating the address selected by the selecting means and the offset value set in the first setting means. A second adding means for calculating an address signal designating the address in the vertical direction of the storage means by calculating the address selected by the selecting means and the offset value set in the second setting means. Characterize.

In this case, the selecting means selects one of the addresses appearing on the first address line and the second address line on the basis of the selection signal and outputs it to the first selection output. And the first address line and the second
Second selecting means for selecting the other address of the addresses appearing on the address line on the basis of the selection signal and outputting it to the second selecting output, wherein the first adding means is selected by the first selecting means. The offset value set in the first setting means is added to one of the addresses, and the second addition means is
The address supplied to the storage means may be converted by adding the offset value set by the second setting means to the other address selected by the second selection means.

Further, it is preferable that the address generating means generate an offset value that shifts one of the first address and the second address generated by the address generating means by a predetermined value.

The address generating means may output the first address and the second address in ascending order or descending order according to the rotation of the image.

[0009]

According to the present invention, the first address and the second address are read according to the area read from the storage means and the rotation direction of the image.
The offset value of the address is set in the first setting means and the second setting means, respectively. The first address and the second address according to the rotation of the image are output to the first address line and the second address line defined by the address space of the control means, and the addresses are selected by the selection means, It is output to the first selection output and the second selection output of the selection means, respectively. The offset value set in the first setting means and the address output to the first selection output are calculated by the first adding means, and the offset value set in the second setting means and the second selection output. And the address output to the second adder are operated to calculate an address signal designating the vertical and horizontal addresses of the storage means.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Referring to FIG. 1, there is shown a block diagram showing an embodiment of an address translation device according to the present invention. The address conversion device 1 stores image data representing an image to be printed, and when reading out the stored image data, an address for forming the image represented by the image data on a recording paper provided in the printer 10. Is an address generator for generating In addition, the address conversion device 1 in this embodiment is an address generation device that, when reading the image data stored in the frame memory 12, performs an aspect conversion process on the read image to generate an address signal for reading. In the following description, parts not directly related to the present invention will be omitted from illustration and description,
Further, the reference numeral of the signal is represented by the reference numeral of the connecting line in which it appears.

The address translation device 1 comprises a frame memory 12 for storing image data as shown in FIG. 1 and a control circuit.
(CPU) 14 and address conversion unit 16 are provided. The output 102 of the frame memory 12 is connected to the printer 10, and the image represented by the image data read from the frame memory 12 is formed on the recording paper by the printer 10.

The frame memory 12 in this embodiment is
An address signal generated by a control circuit (CPU) 14 which will be described later is further converted by an address conversion unit 16, and based on the converted address signal, the horizontal direction of the image represented by the image data appearing on the bus 100 (H ) And in the vertical direction (V), each of which is a frame buffer that stores image data representing an image composed of a total of approximately 1 million pixels of 1024 pixels in its storage area. This frame memory 12 has 1024 pixels x 10
Each pixel composed of 24 pixels has a storage area for storing image data of each of the RGB primary colors. The image data stored in the frame memory 12 may be data in a format such as YMC (yellow, magenta, cyan) suitable for printing by the printer 10. The storage area of the frame memory 12 is 1024 pixels × 1024 as shown in FIG.
It has a storage capacity for storing an image composed of pixels. Therefore, conventional addressing methods specify the horizontal (H) and vertical (V) directions for each pixel.
Each required a 10-bit address line.

As the control circuit 14 in this embodiment, for example, a microprocessor having 14-bit address lines A0 to A13 is applied, and the control circuit 14 is
Write control and read control for accumulating the image data appearing on the bus 100 in the frame memory 14 are performed, and the image data accumulated in the frame memory 12 is recorded in the horizontal direction (H) 1024 pixels × vertical direction (V) 16 lines or It is a control circuit that controls the address conversion unit 16 and the frame memory 12 so as to read out for each window configured by 16 pixels in the horizontal direction (H) × 1024 bits in the vertical direction (V).

More specifically, the control circuit 14 includes a frame memory 12
Has a function of generating an address signal designating an address of the storage area. For example, the control circuit 14 reads the image data stored in the frame memory 12 in the horizontal direction (H direction) or the vertical direction (V direction) of the frame memory 12.
Direction) address signal (A0 to A9) that indicates the value "0 to 1024" and address signal (A10 to A13) that indicates the value "0 to 15" according to the rotation of the image data. It has the function of generating in ascending or descending order. As a result, the control circuit 14 generates an address signal for accessing the storage area of the frame memory 12 shown in FIG. 2 for each window W defined by the address space of the control circuit 14.

The control circuit 14 also has a function of controlling address conversion in an address conversion unit 16 described later. More specifically, the control circuit 14 generates the generated address signal (A0
~ A9) and address signals (A10 ~ A13) are output 110 and 112, respectively. Output 110 of control circuit 14
Is a terminal a of the address selector 18H and a terminal b of the address selector 18V provided in the address conversion unit 16 described later.
Respectively connected to. Also, the output 11 of the control circuit 14
2 is connected to the terminal b of the address selector 18H and the terminal a of the address selector 18V, respectively. In addition, the control circuit 14 responds to the area corresponding to the window W read from the frame memory 12 and the rotation of the image.
For example, it has a function of generating a reference signal H _ref and a reference signal V _ref that serve as a reference for incrementing or decrementing the address in the horizontal direction (H) and the vertical direction (V), for example, every 16 lines. The control circuit 14 generates the H _ref
The signal and the V _ref signal are provided at outputs 114 and 116, respectively. Further, the control circuit 14 is configured to write the image data to the frame memory 12 or
Function to generate vertical / horizontal switching signal (ADRHLV) to change the reading direction of the image data, that is, horizontal direction (H) and vertical direction (V) in the frame memory 12 when reading the image data stored in have. The control circuit 14 outputs the generated vertical / horizontal switching signal (ADRHLV) to the output 118.

The outputs 110 to 118 of the control circuit 14 are connected to the address conversion section 16, which outputs an address signal designating a predetermined window W in the storage area of the frame memory 12 output from the control circuit 14. Is converted into an address signal for designating the entire storage area of the frame memory 12 for each window W, and is also converted into an address signal for rotating and reading the image represented by the image data stored in the frame memory 12. Is. Specifically, the address conversion unit 16 uses the address lines 110 (A0 to A9) from the control circuit 14.
And address lines 112 (A10 to A13) are selectively selected. The address selectors 18H and 18V connect the selected address lines to the outputs 120H and 120V, respectively. The address selectors 18H and 18V are connected to the vertical / horizontal switching signal (AD
Select and switch address lines based on RHLV) 118. Address selectors 18H and 18 in this embodiment
V becomes a connection state in which the same terminal a as shown is connected when the vertical / horizontal switching signal 118 is in the “Low” state, and the vertical / horizontal switching signal 118 is connected.
Is in a "Hi" state, a connection state in which the terminal b opposite to that shown in the figure is connected is established.

The address conversion unit 16 is set based on the reference signal H _ref generated by the control circuit 14, and increments or decrements the address in the horizontal direction (H) in the frame memory 12 by a predetermined value. Offset register 20H to generate the offset signal H _off for
And the frame memory set based on the reference signal V _ref
An offset register 20V for generating an offset signal _Voff for incrementing or decrementing the vertical (V) address in 12 by a predetermined value.

More specifically, the offset register 20H outputs an offset signal H _off "0" indicating that horizontal offset is not performed when the address line 110 (A0 to A9) is selected by the address selector 18H. Outputs to output 122H continuously for one screen and address line with address selector 18H.
When 112 (A10 to A13) is selected, an offset for incrementing or decrementing the address by 16 lines is generated every 16 lines of the address represented by the 4-bit address signal 112 output from the control circuit 14. The signal H _off is output 122H. In addition, the offset register 20V is connected to the address line 110 by the address selector 18V.
When (A0 to A9) is selected, the offset signal V _off "0" indicating that vertical offset is not performed is set to 1
Address selector 18
When the address line 112 (A10 to A13) is selected by V,
4-bit address signal 112 output from the control circuit 14
Every 16 lines of the address represented by, the offset signal V _off for incrementing or decrementing the address by 16 lines is output to the output 122V. The output 122H of the offset register 20H is connected to the adder 22H, and the output 122V of the offset register 20V is connected to the adder 22V.

The adders 22H and 22V are the offset signals H _off and V generated by the offset register 20, respectively.
_This is an arithmetic circuit that adds the address signal output from the address selector 18 to _off . Adders 22H and 22V
Generates an address signal in the H direction and an address signal in the V direction that specify the storage area of the frame memory 12 by adding the address signal to the offset signal. The adders 22H and 22V output the generated H direction address signal and V direction address signal respectively 124H and 124V.
Output to. The outputs 124H and 124V are connected to the H-direction address input and the V-direction address input of the frame memory 12, respectively.

The operation of the address translation device 1 in this embodiment having the above-mentioned configuration will be described below with reference to FIGS. 3 and 4. First, when writing the image data appearing on the bus 100 to the frame memory 12, the output of the control circuit 14
110 outputs 10-bit address signals (A0 to A9) representing "0" to "1023" in ascending order, and output 112 outputs 4-bit address signals (A0 to A9) representing "0" to "15".
10 to A13) are output in ascending order. On the other hand, the output of the control circuit 14
The vertical / horizontal switching signal 118 “Low” is output to 118, and the control circuit 14
In response to the "Low" vertical / horizontal switching signal 118 supplied from the address selector 18H, the input 110 on the terminal a side is selected by the address selector 18H, and the input 112 on the terminal a side is selected by the address selector 18V.
Is selected. As a result, the address signal output to the output 110 of the control circuit 14 is input to the input 120H of the adder 22H, and the address signal output to the output 112 of the control circuit 14 is input to the adder 22V.

Further, the offset amount "0" in the H direction is set in the offset register 20H according to the reference signal H _ref output from the control circuit 14, and the offset register 20V is set in accordance with the reference signal V _ref. First, the initial value "0" of the offset amount in the V direction is set. In this case, the offset amount set in the offset register 20H is
The offset amount set in the offset register 20V is held during the writing of one screen of image data stored in the frame 12 and is stored in the frame memory 12.
Each time the writing of the image data of a line is completed, the offset amount is updated by the value incremented by 16 lines. Offset amount set in the offset register 20H and 20V is output to the output 122H and 122V, respectively as an offset signal H _off and V _off, are respectively input to the adders 22H and 22V.

Offset signal H _off input to adder 22H
Is the address signal selected by the address selector 22H.
(A0 to A9) are added, and the result of this operation is the window W
Is given to the frame memory 12 as an address in the H direction. In this case, the offset signal H _off is the offset signal H representing the offset amount held over one screen.
_{Since off} "0" is added, the address signal having the same value as the address signal output to the output 110 of the control circuit 14 is sequentially input to the frame memory 12. On the other hand, the offset signal V _off input to the adder 22V includes the address selector 22V
The address signals (A10 to A13) selected at are added, and the result of this calculation is given to the frame memory 12 as an address signal in the V direction of the window W. As a result, the address for the frame memory 12 for each window W shown in FIG. 3 is sequentially determined. When address signals are sequentially input to the frame memory 12, the write control of the control circuit 14 causes the image data appearing on the bus 100 to be stored in the storage area of the frame memory 12.

When the image data written in the frame memory 12 is read out at the same angle for each horizontally long window W of 1024 horizontal pixels × 16 vertical lines, an address signal is generated in the same manner as described above, By being supplied to 12, the image data stored in the frame memory 12 is read. In addition, a horizontally long window W of 1024 pixels horizontally × 16 lines vertically written in the frame memory 12
Differences from the above case in which the image data is read at the same angle when the image data is read upside down, that is, rotated 180 ° for each reading, will be described below. The address signal representing "1023 to 0" is decremented and output from the output 110 of the control circuit 14 in the descending order, and the output 112 outputs "15" to "15".
The address signal representing ~ 0 "is decremented and output in descending order. In addition," 1008 "(1024-16) is set as the initial value of the offset amount in the V direction in the offset register 20V, and this offset amount is After every 16 lines of image data have been read, the offset amount is updated by a value reduced by 16 lines, whereby the image data stored in the frame memory 12 can be rotated 180 ° and read.

Next, the operation of rotating the image represented by the image data stored in the frame memory 12 by 90 ° counterclockwise and reading it will be described below with reference to FIG. First, the control circuit 14
Output 110 outputs 10-bit address signals (A0-A9) in ascending order, and output 112 outputs 4-bit address signals (A0-A9).
10 to A13) are output in descending order. At this time, the vertical / horizontal switching signal 118 in the “Hi” state is output to the output 118 of the control circuit 14,
Contrary to the illustration, the terminals b of the address selectors 18H and 18V are selected. As a result, the control circuit 14
The address signal 110 output from is input to the adder 22V, and the address signal 112 is input to the adder 22H. On the other hand, "1008" (1024-16) is set as the initial value of the offset amount in the H direction in the offset register 20H, and this offset amount is reduced by 16 lines each time the reading of 16 pixels of image data is completed. The value is updated to the offset amount. The offset amount is "0" in the offset register 20.
Is set. The set offset amount and the address signal selected by the address selectors 18H and 18V are added by the adders 22H and 22V, respectively,
The added calculation result is input to the input 124H and the input 124V of the frame memory 12 as an address signal designating the address of the window W for reading the image data accumulated in the frame memory 12. As a result, the image data stored in the frame memory 12 is read in a state of being rotated left by 90 °, and the read image data is transferred to the printer 10, so that an image rotated left by 90 ° is obtained. Formed on recording paper.

The difference between the case where the image represented by the image data stored in the frame memory 12 is read out by rotating it 90 ° to the right and the case where the image is rotated 90 ° to the left will be described. 110 to 10 bit address signal
(A0 to A9) are output in descending order, and the 4-bit address signals (A10 to A13) are output from the output 112 in ascending order. "0" is set as the initial value of the offset amount in the H direction in the offset register 20H, and this offset amount is the image data.
Every time the reading of 16 pixels is completed, the offset amount is increased by 16 lines. The other operation in this case may be the same operation as the case of rotating the image 90 ° to the left, whereby the image data accumulated in the frame memory is read out in the state of being rotated 90 ° to the right.

As described above, by controlling the offset amounts in the horizontal and vertical directions and the reading directions in the vertical and horizontal directions, the reading for each window is indicated by an arrow in FIGS. 5A to 5C. Image rotated 180 ° as shown, or 90
° You can get images rotated right or left.
Therefore, according to the above-described embodiment, even when the address space of the control circuit 14 is smaller than the address space of the frame memory 12, the image data can be freely rotated and read from the frame memory 12. In this case, in particular, the control circuit does not need to generate a special address signal for image rotation at the time of reading the image data stored in the frame memory, and the image data read without performing the normal image rotation. The configuration may be such that an address signal equivalent to the read address at that time is generated.

In the description of the embodiment, the address conversion device 1 is configured to rotate the image when reading the image data, but the present invention is not limited to this. For example, when writing the image data to the frame memory 12, the image is read. Is rotated in advance and written, and the image data stored in the frame memory 12 is read out in a different direction to rotate the image, thereby causing the printer to rotate.
Printing may be performed at 10. Further, at the time of outputting the address signal generated by the control circuit 14 and at the time of outputting the offset signal set by the offset register 20,
By outputting each in ascending or descending order and further changing the reading direction of the image data, it is possible to obtain an image representing a mirror image symmetrical with respect to a predetermined peripheral portion of the image represented by the image data.

[0028]

As described above, according to the present invention, even if the address space defined by the control means is smaller than the address space of the storage area of the storage means, the image data can be displayed by the window defined by the address space of the control means. Can be written to and read from the storage means. Further, since the first address line and the second address line are selected and connected to the first selection output and the second selection output by the selection means, respectively, the vertical and horizontal directions of the image data in the storage means are converted. It is possible to output the image data read from the storage means to an image forming means such as a printer and form the rotated image on an image recording medium such as recording paper. As a result, when the image is freely rotated and formed on the image recording medium, an address conversion device having a simple configuration that does not require, for example, an operation of changing the setting direction of the image recording medium is realized. In particular, since the address conversion for rotating the image can be performed by using the control means having a small address space, the device therefor can be constructed at a low cost. Further, in this case, the address generation means of the control means may be configured to generate an address designating the storage area in the window regardless of the rotation of the image, that is, the reading direction of the image data, so that the control having a small address space is possible. Even by the means, the image data can be continuously read without changing the generation method of the generated address.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an address translation device of the present invention.

FIG. 2 is a conceptual diagram showing a window defined by an address space of a control circuit shown in FIG. 1 and an address space of a frame memory.

FIG. 3 is a view showing windows horizontally long in the frame memory shown in FIG. 1;

FIG. 4 is a diagram showing windows vertically arranged in a vertical direction of the frame memory shown in FIG.

5A and 5B are explanatory diagrams showing the concept of the rotation read operation in the embodiment shown in FIG.

[Explanation of symbols]

 1 Address converter 10 Printer 12 Frame memory 14 Control circuit 16 Address converter 18H, 18V Address selector 20H, 20V Offset register 22H, 22V Adder

Claims (4)

[Claims] 1. An address conversion device for converting an address signal designating a predetermined storage area of storage means for storing data such as image data, wherein the device is a window of an address space smaller than the address space of the storage area. A control unit for generating an address designating the first address, the control unit generating a first address according to the horizontal direction of the window and a second address according to the vertical direction of the window, and generating the first address and the first address. Address generating means for outputting two addresses to the first address line and the second address line, and an offset value for shifting the address generated by the address generating means by a predetermined value. Offset generating means for generating, and a first address output to each of the first address line and the second address line. Address selection means for generating a selection signal for selecting the address and the second address, the apparatus further comprising: the first address line and the first address line in response to the selection signal generated by the address selection means. Selecting means for selectively connecting the two address lines to the first selecting output and the second selecting output respectively, and in the storage area of the storing means based on the offset value generated by the offset generating means. First setting means for setting an offset value for shifting the address in the horizontal direction, second setting means for setting an offset value for shifting the address in the vertical direction in the storage area of the storage means, and selection by the selection means The calculated address and the offset value set in the first setting means are calculated to specify an address in the lateral direction of the storage means. An address for calculating a dress signal, first address means, an address selected by the selecting means and an offset value set in the second setting means, and an address for specifying a vertical address of the storage means. An address conversion device, comprising: a second addition means for calculating a signal. 2. The address translation device according to claim 1, wherein the selection means sets one of the addresses appearing on the first address line and the second address line based on the selection signal. First selecting means for selecting and outputting to a first selecting output and another address of the addresses appearing on the first address line and the second address line are selected based on the selecting signal A second selecting unit for outputting to a selective output, wherein the first adding unit sets the offset set in the first setting unit to the one address selected by the first selecting unit. A value is added, the second adding means adds the offset value set in the second setting means to the other address selected by the second selecting means, and stores the value. Address converting apparatus and converting the address to be supplied to the stage. 3. The address conversion device according to claim 1, wherein the address generation unit determines a predetermined one of the first address and the second address generated by the address generation unit. An address translation device characterized by generating an offset value for shifting each value. 4. The address conversion device according to claim 1, wherein the address generation unit outputs the first address and the second address in ascending order or descending order according to the rotation of the image. Address translation device characterized by.