JPH07321609A - D type flip-flop circuit with hold function - Google Patents

Abstract

PURPOSE:To reduce layout area and power consumption by forcibly interrupting the connection between a 1st D latch circuit and a 2nd latch circuit of the D type flip-flop and using the 2nd D latch circuit to form a holding state. CONSTITUTION:When a low level signal being a signal H is given to a hold control terminal 3, a signal D received from a data input terminal 1 is received by the 1st D latch circuit 10 with a low level signal being a clock signal C received from a clock input terminal 2, transferred to a 2nd D latch circuit 29 by the rising of the signal C and outputted from a data output terminal 4 as an output signal Q. When a high level signal being the signal H is given to the terminal 3, since a dual direction bus gate 6 is conductive independently of the signal C, a feedback loop is produced in the inside of the circuit 20 and reaches a holding state. Since the dual direction bus gate 5 is nonconductive, the circuits 10, 20 are interrupted and data of the circuit 20 are not destructed in the circuit 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D-type flip-flop device, and more particularly to a D-type flip-flop device capable of holding an output signal.

[0002]

2. Description of the Related Art A conventional D-type flip-flop device includes
Some are shown in FIGS. 4 and 5. The flip-flop device shown in FIG. 4 is called a flip-flop device with a clock control hold function. The control circuit 55 is inserted in the input stage of the clock input terminal 52 of the flip-flop circuit 56, Data is held by stopping the input of. Further, the flip-flop device shown in FIG. 5 is a flip-flop device called a data select type, in which a selector circuit 57 is inserted in the input stage of the data 51 of the flip-flop circuit 56, the output data is fed back, and the D-type flip-flop device is fed back. The hold function is realized by using the input data of the circuit 56.

[0003]

Of the above-mentioned conventional techniques,
In the D-type flip-flop with the clock control hold function shown in FIG. 4, the clock 52 and the hold control signal 53
There is a possibility that the flip-flop becomes asynchronous with the clock depending on the phase of. Further, in the D-type flip-flop with the data select type hold function shown in FIG. 5, many transistors are required to configure the selector circuit 57, which causes a problem that the configuration area and power consumption increase.

Therefore, a technical object of the present invention is to provide a D-type flip-flop with a hold function, which is synchronous with a clock and has a hold function by adding a minimum number of transistors in a flip-flop device. is there.

[0005]

A D-type flip-flop device with a hold function according to the present invention includes a first D-latch circuit having a first feedback loop, and a first D-latch circuit for controlling an output of the first D-latch circuit. One switch circuit, a second D latch circuit connected in series with the first switch circuit and having a second feedback loop, and a second switch circuit for controlling the second feedback loop. It is characterized by having.

Further, in the D-type flip-flop device with hold function of the present invention, the first D latch circuit sets the output levels of the first bidirectional pass gate and the first bidirectional pass gate which are turned on by a clock signal. A first inverter that outputs an inverted signal, and the first feedback loop includes a second inverter that outputs a signal obtained by inverting the level of the output of the first inverter;
The second D-latch circuit includes a third bidirectional pass gate turned on by the clock signal and a third inverter for inverting and outputting the output of the third bidirectional pass gate, and the second feedback loop. Is equipped with a fourth inverter that outputs a signal obtained by inverting the level of the output signal of the third inverter.

In the D-type flip-flop device with hold function according to the present invention, the first feedback loop is further serially connected to the second inverter and is turned on by a signal obtained by inverting the level of the clock. The second feedback loop further includes a fourth bidirectional pass gate connected to the output terminal of the fourth inverter and turned on by the clock signal, and the first switch circuit includes the second switch. A fifth bidirectional passgate interposed between the inverter and the third bidirectional passgate and turned on by the hold signal, the second switch circuit being inserted in parallel with the fourth bidirectional passgate. It is preferable to include a sixth bidirectional pass gate which is turned on by a signal obtained by inverting the level of the hold signal.

On the other hand, in the D-type flip-flop device with hold function according to the present invention, the first inverter and the first switch circuit each include a clocked inverter which is turned on by a hold signal, and the first feedback loop includes: A clocked inverter that turns on by a clock inversion signal is provided, and the fourth inverter, the fourth bidirectional pass gate, and the second switch circuit turn on by a signal obtained by inverting the levels of the clock signal and the hold signal. It is preferable that it is configured by one clocked inverter.

[0009]

According to the present invention, the connection between the first D latch circuit and the second D latch circuit of the D type flip-flop is forcibly cut off, and the hold state is formed by the second D latch circuit. Hold function can be realized.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing a D-type flip-flop device (hereinafter referred to as D-FF) according to a first embodiment of the present invention. In FIG. 1, the data input terminal 1 is the first D
It is connected to the data input of a master side D latch circuit (hereinafter referred to as a first D latch circuit) 10 which is a latch circuit.

The first D-latch circuit 10 includes a first bidirectional pass gate (hereinafter referred to as PG) connected to the data input terminal 1.
11), the first master inverter 13 connected to this, the second PG 12 and the second PG 12 forming a first feedback loop inserted in parallel to the first master inverter 13.
The master inverter 14 of FIG.

The slave D latch circuit (hereinafter referred to as the second latch circuit) includes a third PG 23 and a first slave inverter 22. Further, the second slave inverter 25 and the fourth PG 24 are connected in series, and both ends of this series circuit are connected to the output end of the first slave inverter 22 and the other end of the third PG 23, respectively. 2 feedback loops are configured. The output of the second D latch circuit 20 is connected to the data output terminal 4.

The first D latch circuit 10 and the second D latch circuit 20 are composed of a fifth PG5 which is a first switch circuit.
Connected through.

The sixth PG 6, which is connected to the data input side and controls the hold function of the output data, is arranged in parallel with the fourth PG 24 inside the second D latch circuit 20 so that the second PG 6 is connected to the second slave. The output side of the inverter 25 and the third P
It is connected to the output side of G23.

Further, the clock input terminal 2 is connected to a first clock inverter 7 and a second clock inverter 8, and these first and second clock inverters 7 and 8 have a level of a clock signal (C signal). And a clock signal (C signal) having its level inverted and a clock signal (C signal) having its level inverted.

Further, the hold control terminal 3 is connected to a first hold control inverter 15 and a second hold control inverter 16, and the first and second hold control inverters 15 and 16 are connected to the hold control signal (signal). H) or a hold control negation signal (to H signal) with its level inverted.

When the "low" level is input to the clock input terminal 2, the first D latch circuit 10 receives the first PG1.
1 is in a conductive state and the second PG 12 is in a non-conductive state, and the data of the data input terminal 1 is fetched inside. on the other hand,
When "high" level is input to the clock input terminal 2,
The first PG 11 becomes non-conductive and the second PG 12 becomes conductive, forming a feedback circuit and holding data.

In the second D-latch circuit 20, when a "high" level signal is input to the clock input terminal 2, the third PG 23 becomes conductive and the fourth PG 24.
Becomes non-conductive, the output data of the fifth PG5 at the preceding stage is taken in internally, and when a "low" level signal is input to the clock input terminal 2, the third PG23 becomes non-conductive, The PG 24 of 4 becomes conductive, forms a feedback circuit, and holds data.

The fifth PG5 which is the first switch circuit
Becomes conductive when a "low" level signal is input to the hold control terminal 3, outputs the data of the first D-latch circuit 10 to the second D-latch circuit 20, and outputs "high" to the hold-control terminal 3. When a "level" signal is input, the first D-latch circuit 10 and the second D-latch circuit 20 are cut off.

A sixth PG6 which is a second switch circuit
Becomes conductive when a "high" level signal is input to the hold control terminal 3, and the first slave inverter 2
2 output data is input to the second slave inverter 25, the second D-latch circuit 20 is forcibly placed in the hold state, and when a "low" level signal is input to the hold control terminal 3, it becomes non-conductive. Then, the second D latch circuit 20
Is controlled by the fourth PG 24.

As described above, the first D latch circuit 10 and the second D latch circuit 20 are cut off by the fifth PG 5, and the sixth P latch circuit 10 is disconnected.
By forcing the second D latch circuit 20 into the hold state by G6, the D-FF device with the hold function according to the embodiment of the present invention is realized.

Next, the circuit operation of this embodiment thus constructed will be described with reference to the timing chart shown in FIG.

When a "low" level signal is input as the signal H to the hold control terminal 3 as shown in FIG. 2C, it is input from the data input terminal 1 as shown in FIG. As shown in FIG. 2B, the signal D is taken into the first D-latch circuit 10 by the “low” level signal of the clock signal C input from the clock input terminal 2 and rises by the clock signal C. , And is transferred to the second D latch circuit 20 and is output to the data output terminal 4 as the output signal Q as shown in FIG.
That is, a general clock rising synchronization D-FF
Configure the device. In addition, as shown in FIG. 2D, the signal M is a master D latch output signal, which is the output of the first master inverter 13, and as shown in FIG.
Is the slave D-latch input signal S and indicates the output of the fifth PG 5.

When a "high" level signal is input to the hold control terminal 3 as the signal H as shown in FIG. 2C, the clock signal C input from the clock input terminal 2 is input.
Since the sixth PG 6 becomes conductive regardless of the value of, the second D-latch circuit 20 internally enters a feedback loop and enters the hold state. Further, since the fifth PG 5 becomes non-conducting, the first D latch circuit 10 and the second D latch circuit 20 are disconnected as shown in FIGS. The data of the D latch circuit 20 is not destroyed by the first D latch circuit 10.

The output signal Q shown in FIG. 2 (f) rises to the clock signal C shown in FIG. 2 (b) after the signal H shown in FIG. 2 (c) is released to the "low" level. It is held until the data of the second D latch circuit 20 is rewritten, and rewritten in synchronization with the rising edge of the clock signal C.

FIG. 3A shows a D according to the second embodiment of the present invention.
It is a diagram showing a -FF device, which is configured by using a clocked inverter (hereinafter, referred to as CINV). Figure 3
As shown in (a), the first CINV 17 disconnects the D latch circuit 10 and the D latch circuit 20, and the third CINV 26, which is a two-parallel clock inverter, forcibly puts the D latch circuit 20 into a hold state. By doing so, the D-FF device with the hold function according to the second embodiment is realized.

FIG. 3B is a diagram showing the configuration of the first and second CINVs 17 and 18 of FIG. 3A, and FIG.
The first and second CINVs 17, 18 shown in the above figure
Is composed of a transistor circuit as shown in the figure below. 3C is a diagram showing the configuration of the CINV 26, and the third CINV 26 shown in the upper diagram of FIG. 3B is shown.
Is composed of the transistor circuit shown in the lower diagram of FIG.

The operation of the D-FF device according to the second embodiment is as follows.
Substantially the same as the first embodiment.

That is, the master side forward inverter of the DFF is a clocked inverter (first CINV17),
The slave side feedback inverter is a two parallel clock inverter (third CINV26). This first CIN
V17 is turned off during hold by the hold control signal
(High impedance) state and the third CINV2
6 is forcibly replaced by a circuit equivalent to an inverter during hold. Due to the above, at the time of hold, the slave side forms a loop circuit to hold the data, the master side is fixed to the high impedance state, the external data destruction due to the clock change is prevented, and the gold function is realized. is doing.

[0031]

As described above, according to the present invention, in the D-type flip-flop device, 14 to 16 transistors are required for the synchronous hold function with respect to the clock. Since it can be realized, it is possible to provide a D-type flip-flop device which is effective in reducing the layout area and power consumption.

[Brief description of drawings]

FIG. 1 is a D with a hold function according to a first embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of a type flip-flop device.

FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG.

FIG. 3 is a D with a hold function according to the first embodiment of the present invention.
FIG. 3 is a circuit configuration diagram of a type flip-flop device.

FIG. 4 is a circuit configuration diagram showing an example of a conventional D-type flip-flop device with a hold function.

FIG. 5 is a circuit configuration diagram showing another example of a conventional D-type flip-flop device with a hold function.

[Explanation of symbols]

 1 Data Input Terminal 2 Clock Input Terminal 3 Hold Control Terminal 4 Data Output Terminal 5 Fifth Bidirectional Pass Gate (PG) 6 Sixth Bidirectional Pass Gate (PG) 7 First Clock Inverter 8 Second Clock Inverter 10th 1 D latch circuit 11 1st bidirectional pass gate (PG) 12 2nd bidirectional pass gate (PG) 13 1st master inverter 14 2nd master inverter 15 1st hold control inverter 16 2nd hold control Inverter 17 First clocked inverter circuit (CINV) 18 Second clocked inverter circuit (CINV) 20 Second D latch circuit 22 First slave inverter 23 Third bidirectional pass gate (PG) 24 Fourth Bidirectional pass gate (PG) 25 Second slave inverter 26 Third Clocked inverter (CINV) D input data signal C clock signal H hold control signal M master D latch output signal S slave D latch input signal Q output data signal

Claims (4)

[Claims] 1. A first D-latch circuit having a first feedback loop, a first switch circuit for controlling the output of the first D-latch circuit, and a series connection to the first switch circuit. A D-type flip-flop device with a hold function, further comprising a second D-latch circuit having a second feedback loop and a second switch circuit for controlling the second feedback loop. 2. The D-type flip-flop device with a hold function according to claim 1, wherein the first D latch circuit outputs a first bidirectional pass gate and an output of the first bidirectional pass gate which are turned on by a clock signal. A first inverter that outputs a signal whose level is inverted, and the first feedback loop includes a second inverter that outputs a signal whose level is inverted from the output of the first inverter. Of the D latch circuit includes a third bidirectional pass gate which is turned on by the clock signal, and a third inverter which inverts and outputs the output of the third bidirectional pass gate, and the second feedback loop includes the second feedback loop. D with a hold function, comprising a fourth inverter that outputs a signal obtained by inverting the level of the output signal of the third inverter. Type flip-flop device. 3. The D-type flip-flop device with hold function according to claim 2, wherein the first feedback loop is further serially connected to the second inverter and is turned on by a signal obtained by inverting the level of the clock. The second feedback loop is further connected to the output terminal of the fourth inverter and is turned on by the clock signal.
Switch circuit includes a fifth bidirectional pass gate which is interposed between the second inverter and the third bidirectional pass gate and is turned on by the hold signal, and the second switch circuit includes the fourth bidirectional pass gate. A D-type flip-flop device with a holding function, comprising a sixth bidirectional pass gate which is inserted in parallel with a corresponding pass gate and is turned on by a signal obtained by inverting the level of the hold signal. 4. The D-type flip-flop device with hold function according to claim 2, wherein the first inverter and the first switch circuit include a clocked inverter that is turned on by a hold signal, and the first feedback loop is A clocked inverter that is turned on by a clock inversion signal, wherein the fourth inverter, the fourth bidirectional pass gate, and the second switch circuit are provided with a signal obtained by inverting the levels of the clock signal and the hold signal. A D-type flip-flop device with a hold function, which is configured by one clocked inverter that is turned on.