JPH0732205B2 - Method of manufacturing nonvolatile semiconductor memory device - Google Patents

Description

The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device,
In particular, the present invention relates to a method for manufacturing a non-volatile semiconductor memory device that enables high integration of a memory device and improvement of characteristics.

[Prior Art] Conventionally, a method of manufacturing a nonvolatile semiconductor memory device of this type is
As shown in FIG. 2, first, a first insulating film 22 (for example, an oxide film formed by a thermal oxidation method, a film thickness of 200Å to 1000) is formed on a semiconductor substrate 21.
Å) is formed, and the first insulating film 22 and the semiconductor substrate 21 are selectively removed by etching using the photoresist 23 as a mask to form a groove to be an element isolation region [FIG. 2 (a)]. . Next, a second insulating film 24 (for example, an oxide film by chemical vapor deposition, film thickness 1 μm to 3 μm) is formed on the entire surface [FIG. 2 (b)]. Next, the second insulating film 24 is etched back and only the second insulating film 24 is formed in the trench to be the element isolation region.
Are embedded [Fig. 2 (c)].

Then, on the exposed surface of the semiconductor substrate 21, a fourth insulating film 26 (for example, an oxide film formed by a thermal oxidation method, a film thickness
200 Å ~ 1000 Å) is formed [Fig. 2 (d)]. A first polycrystalline silicon film 27 containing impurities (for example, phosphorus), which will become a floating gate electrode, is formed thereon [FIG. 2 (e)]. The first polycrystalline silicon film 27 is selectively removed by etching by a known photoetching technique using a photoresist [FIG. 2 (f)]. Then, a fifth insulating film 29 (for example, a nitride film formed by a chemical vapor deposition method, a film thickness of 200Å to 1000Å) is formed on the first polycrystalline silicon film 27, and an impurity (for example, a control gate electrode) (for example, A second polycrystalline silicon film 30 containing phosphorus is formed [FIG. 2 (g)]. After that, the second polycrystalline silicon film 30, the fifth insulating film 29, and the first polycrystalline silicon film 17 are selectively etched and removed by the photoetching technique.

[Problems to be Solved by the Invention] In the above-described conventional manufacturing method, the upper end of the groove formed in the semiconductor substrate is exposed when the fourth insulating film serving as the gate insulating film is formed. [See FIG. 2 (c)]. Therefore, when the semiconductor substrate in this state is subjected to the thermal oxidation method, the thickness of the fourth insulating film 26 becomes thin at the corners of the upper end of the groove as shown in FIG. That is, the fourth formed
The film thickness of the fourth insulating film is as thin as d ₂ at the corner of the upper end of the groove with respect to the film thickness d of the insulating film. Therefore, the dielectric strength voltage in this portion is reduced.

In addition, the first polycrystalline silicon film 27 that becomes the floating gate electrode 27
Must be etched and separated on the groove to be the element isolation region, but since the photo-etching technique is used for etching and separating the first polycrystalline silicon film 27, a margin for alignment is required. That is, as shown in FIG. 4, even when the first polycrystalline silicon film 27 is separated with the minimum separation dimension L ₁ , the groove width serving as an element isolation region requires a positioning allowance and the groove width. Must be greater than the minimum separation dimension L ₁ and L ₂ . This is an obstacle to high integration.

[Means for Solving Problems] A method for manufacturing a nonvolatile semiconductor memory device according to the present invention includes a step of forming a first insulating film on a surface of a semiconductor substrate, and selectively forming the first insulating film and the semiconductor substrate. A step of forming a groove by etching, a step of forming a second insulating film on the entire surface and then etching back the same to fill the groove, and a step of removing the first insulating film and then forming a third insulating film on the entire surface. Forming and etching back this to leave the third insulating film only on the side wall of the second insulating film; and forming the fourth insulating film on the surface of the semiconductor substrate and then forming the first polycrystalline silicon film on the entire surface. A step of forming a planarization material on the entire surface, etching back the planarization material and the first polycrystalline silicon film until the second insulating film is exposed, and removing the remaining planarization material. And form a fifth insulating film on the first polycrystalline silicon film. And then the second
And a step of forming a polycrystalline silicon film.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

1 (a) to 1 (i) are longitudinal sectional views showing the order of steps in one embodiment of the present invention. First, a thick first substrate on the semiconductor substrate 11
Insulating film 12 (for example, an oxide film formed by a thermal oxidation method, a film thickness of 0.5
.mu.m to 1.5 .mu.m) is formed, and the first insulating film 12 and the semiconductor substrate 11 are selectively removed by etching by a known photoetching technique using the photoresist 13 to form a groove to be an element isolation region [ FIG. 1 (a)]. After removing the photoresist 13, a second insulating film 14 (for example, a nitride film formed by a chemical vapor deposition method, a film thickness of 2000Å to 1 μm) is formed on the entire surface.
m) is formed [FIG. 1 (b)]. Then, the second insulating film 14 is etched back until the first insulating film 12 is exposed, and the second insulating film 14 is left only in the groove portion [FIG. 1 (c)].

Next, the entire surface is exposed to an etching liquid having a high reactivity with the first insulating film 12 (for example, an etching liquid containing hydrofluoric acid) to remove the first insulating film 12, and then the third insulating film 15 is removed.
Are formed on the entire surface [FIG. 1 (d)]. The entire surface is exposed to anisotropic plasma etching to leave the third insulating film 15 only on the side wall of the second insulating film 14 [FIG. 1 (e)].

Then, on the exposed semiconductor substrate 1, a fourth insulating film 16 (for example, an oxide film formed by a thermal oxidation method, a film thickness
200 Å ~ 1000 Å) is formed, and then a first polycrystalline silicon film 17 containing impurities (for example, phosphorus) to be a floating gate electrode is formed, and a planarizing material 18 (for example,
A photoresist) is formed [FIG. 1 (f)]. The planarizing material 18 and the first polycrystalline silicon film 17 on the entire surface are etched back until the second insulating film 14 is exposed, and the residual planarizing material 18 is removed [FIG. 1 (g)]. Next, the insulating film 19 of FIG. 5 (for example, a nitride film formed by chemical vapor deposition,
A film thickness of 200Å to 1000Å) is formed [Fig. 1 (h)]. Then, a second polycrystalline silicon film 20 containing an impurity (for example, phosphorus) to be a control gate electrode is formed [FIG. 1 (i)]. After that, the second polycrystalline silicon film 20, the fifth insulating film 19, and the first polycrystalline silicon film 17 are selectively removed by etching by a known photoetching technique using a resist.

In the above embodiments, the first insulating film is the oxide film and the second insulating film is the nitride film, but this may be reversed.

[Effects of the Invention] As described above, according to the present invention, the third insulating film 15 is formed on the side wall of the second insulating film 14 in the element isolation region. The upper end of the groove of the semiconductor substrate is not exposed, and the withstand voltage is improved. That is, as shown in FIG. 3, since the insulating film thickness d _{1 at} the corner portion of the upper end of the groove of the semiconductor substrate 1 is larger than the film thickness d of the formed fourth insulating film 16. The withstand voltage in this part is improved.

In addition, the first polycrystalline silicon film 17 serving as the floating gate electrode
Since the isolation is performed in self-alignment with the second insulating film 14 in the element isolation region, there is no need for a positioning margin in the width of the groove to be the element isolation region, and the minimum width equal to the groove width. It can be a separation width. That is, as shown in FIG. 3, the width of the trench which becomes the element isolation region and the isolation width of the first polycrystalline silicon film 17 which becomes the floating gate electrode can be set to the minimum isolation width L ₁ .

Further, the first polycrystalline silicon film that is the floating gate electrode
Since the cross-sectional shape of 17 is concave as shown in FIG. 1 (i), the facing area with the second polycrystalline silicon film, which is the control gate electrode, becomes large, and the memory speed of the device is high. There is also the effect of becoming.

[Brief description of drawings]

1 (a) to (i) are vertical sectional views showing a manufacturing process of an embodiment of the present invention, and FIGS. 2 (a) to (g) are vertical sectional views showing a manufacturing process of a conventional example. The figure is an enlarged view of the main part of FIG. 1 (i), and FIG. 4 is an enlarged view of the main part of FIG. 2 (g). 11, 21 ... Semiconductor substrate, 12, 22 ... First insulating film, 13,
23 ... Photoresist, 14, 24 ... Second insulating film, 15 ...
… Third insulating film, 16, 26 …… Fourth insulating film, 17,27 ……
First polycrystalline silicon film, 18 ... Planarizing material, 19, 29 ...
… Fifth insulating film, 20, 30 …… Second polycrystalline silicon film.

Claims (1)

[Claims] 1. A step of forming a first insulating film on a surface of a semiconductor substrate; a step of selectively etching the first insulating film and the semiconductor substrate to form a groove for element isolation; After forming the second insulating film, the film is etched back to fill the groove with the second insulating film, the step of removing the first insulating film, and the third insulating film is formed on the entire surface. Then, the film is etched back to leave the third insulating film only on the side wall of the second insulating film, and after the fourth insulating film is formed on the surface of the semiconductor substrate, polycrystalline silicon 4 is formed on the entire surface. And a step of forming a planarization material film, a step of etching back the planarization material film and the polycrystalline silicon film until the second insulating film is exposed to form a floating gate electrode, and a remaining planarization process. Non-volatile, characterized by comprising a step of removing the film. Method of manufacturing a conductor memory device.