JPH0732206B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same semiconductor substrate, and a high performance bipolar transistor and MO transistor are provided.
The present invention relates to a method for manufacturing a semiconductor device that realizes an S-type transistor.

(B) Conventional Technology As semiconductor integrated circuits have become more sophisticated and more sophisticated, composite devices that allow analog and digital functions to coexist on the same chip are drawing attention. One technology that realizes the demands for such circuit functions is Bi-CMOS technology in which a bipolar transistor and a MOS transistor are integrated on the same semiconductor substrate. This technique can make use of the characteristics of both the low-consumption electrode and high integration of the MOS type integrated circuit and the high speed and current drive capability of the bipolar type integrated circuit.

FIG. 2 is a sectional view showing a typical conventional Bi-CMOS semiconductor device as described in, for example, JP-A-59-117150. In the figure, (1) is a P-type semiconductor substrate,
(2) is an N-type epitaxial layer formed on the entire surface of the substrate (1), (3) is an N ⁺ -type buried layer formed on the surface of the substrate (1), and (4) is formed on the surface of the substrate (1). P ⁺ type buried layer,
(5) is a P ⁺ type isolation region, and (6) is a field oxide film. The NPN type bipolar transistor ( 7 ) has a P type base region (8), an N type emitter region (9) and an N type emitter region (9) on the surface of the epitaxial layer (2) on the N ⁺ type buried layer (3), respectively.
A type collector contact region (10) is formed and configured.
The P-channel MOS transistor ( 11 ) has a gate oxide film (12), a gate electrode (13), and a P-type source / drain on the surface of the epitaxial layer (2) on the N ⁺ -type buried layer (3). It is formed by the region (14). N channel
The MOS type transistor ( 15 ) has a gate oxide film (12), a gate electrode (13), and an N type source / drain on the surface of the P type well (16) on the P ⁺ type buried layer (4). Area (17)
It is formed by.

Then, after forming the base region (8) of the bipolar type transistor ( 7 ), the gate electrode (13) provided on the gate oxide film (12) is used as a mask to form the source / drain region of the P-channel MOS type transistor ( 11 ) ( 14) forming
Subsequently, the emitter region (9) and collector contact region (10) of the bipolar type transistor ( 7 ) and the source / drain region (1) of the N-channel MOS type transistor ( 15 ).
By forming 7) simultaneously, each device was integrated on the same substrate.

(C) Problems to be Solved by the Invention However, in the above-described conventional manufacturing method, the base region (8) is re-diffused by the thermal oxidation step of forming the gate oxide film (12) after the diffusion of the base region (8). However, as the diffusion depth increases, the diffusion time of the N-type source / drain region (17) cannot be lengthened in order to maintain the gate length of the N-channel MOS transistor ( 15 ). Since the diffusion depth of) is restricted, the base width of the bipolar transistor ( 7 ) becomes large, resulting in a high h
There was a drawback that _FE (current amplification factor) could not be expected.

For the same reason, the impurity concentration in the emitter region (9) cannot be increased, so that there is a drawback in that a bipolar transistor ( 7 ) having a high f _T (cutoff frequency) and a high Icmax (current capacity) cannot be obtained. .

(D) Means for Solving the Problems The present invention has been made in view of the above drawbacks, and forms a polycrystalline silicon layer (23) to be a gate electrode (13) of a MOS transistor ( 11 ) ( 15 ). A step of forming an etching hole in the polycrystalline silicon layer (23) on the area where the emitter region (9) of the bipolar transistor ( 7 ) is formed, and a step of forming phosphorus in the polycrystalline silicon layer (23) as an N-type impurity. (P)
And simultaneously forming a diffusive Eta region (9) of the bipolar transistor ( 7 ), selectively etching the polycrystalline silicon layer (23) to form a gate electrode (13), and 13) as a mask
Source / drain region (14) of channel MOS type transistor ( 11 ) and N channel MOS type transistor ( 15 )
And a step of forming the source / drain regions (17) of the same, respectively, so that a high performance bipolar transistor ( 7 ) and a MOS transistor ( 11 ) ( 15 ) can coexist. Is provided.

(E) Function According to the present invention, the base / emitter regions (8) and (9) of the bipolar transistor ( 7 ) can be independently formed, and the impurity concentration of the emitter region (9) can be sufficiently increased. Therefore, a high h _FE can be obtained with good controllability. Moreover, since the step of doping the gate electrodes (13) of the MOS transistors ( 11 ) and ( 15 ) with N-type impurities is used to form the emitter region (9), the steps can be simplified.

(F) Examples The present invention will be described in detail below with reference to FIGS. 1A to 1G.

As shown in FIG. 1A, the semiconductor device according to the present invention has a P
Boron (B) and N ⁺ type buried layer (3) with a surface concentration of 10 ¹⁹ cm ^-3 of antimony (Sb) on the surface of the type semiconductor substrate (1)
Deposit a P ⁺ -type buried layer (4) such as a surface concentration of 10 ¹⁸ cm ^-3 and a lower isolation region (18) of the isolation region (5) by
An N-type epitaxial layer (2) having an impurity concentration of about 10 ¹⁵ cm ^{−3 is formed on the} entire surface of the substrate (1) by, for example, 5 by a known vapor phase growth method.
It is formed by laminating to a thickness of μ.

Subsequently, as shown in FIG. 1B, after ion implantation of boron (B) forming the P well (16) of the N-channel MOS transistor ( 15 ) on the surface of the epitaxial layer (2), the surface of the epitaxial layer (2) is To P ⁺ type upper isolation region (1
The P-well (16) and the isolation region (5) are simultaneously formed by diffusing 9) and connecting with the lower isolation region (18). By thus separating the upper and lower sides from each other, the region where the bipolar type transistor ( 7 ) is formed and the region where the MOS type transistors ( 11 ) and ( 15 ) are formed are electrically separated from each other and the N ⁺ type buried layer ( 3) The re-diffusion in the upward direction is suppressed to prevent the breakdown voltage of the device from deteriorating.

Then, as shown in FIG. 1C, a silicon nitride film (Si ₃ N ₄ ) is deposited on the oxide film (20) covering the epitaxial layer (2) and selectively removed to remove the oxidation resistant mask (21).
Then, the thick field oxide film (6) for surface isolation is formed by performing oxidation under high temperature and high humidity conditions.

Next, as shown in FIG. 1D, after the oxidation resistant mask (21) is removed and a P type base region (8) is formed by using a well-known ion implantation method, a surface oxide film (20) is formed. Are removed to expose the epitaxial layer (2), and gate oxidation is performed to form a thin gate oxide film (12) on the surface of each element formation region. In addition to the method of forming the base region (8) after forming the field oxide film (6), the base region (8) is driven in to a desired depth by heat treatment of the field oxide film (6), before the formation of the field oxide film (6). The method of forming the same in advance and the method of using the same diffusion region as the P well (16) are considered.

Next, as shown in FIG. 1E, the gate electrodes (13) of the MOS transistors ( 11 ) ( 15 ) are formed on the entire surface of the epitaxial layer (2).
A polycrystalline silicon layer (23) in a non-doped state or a state close to that is deposited, and the polycrystalline silicon layer (9) on the emitter region (9) and collector contact region (10) of the bipolar transistor ( 7 ) is deposited using the photoresist as a mask. 23) and oxide film (22) are removed.

Next, as shown in FIG. 1F, a ring lath film (24) is formed on the polycrystalline silicon layer (23) by a known method, and phosphorus (P) is introduced into the polycrystalline silicon layer (23). The resistance of the polycrystalline silicon layer (23) is reduced, and phosphorus (P) is deposited on the surface of the base region (8) of the bipolar transistor ( 7 ) to form an N ⁺ -type emitter region (9) and a collector contact region. (10) and are formed by diffusion.

Next, as shown in FIG. 1G, after removing the ring lath film (24), the polycrystalline silicon layer (23) into which phosphorus (P) has been introduced is selectively etched to form a gate electrode (13), and then a photolithography is performed. The P-channel MOS type transistor ( 11 ) and N-channel MOS type transistor ( 15 ) are alternately exposed by the resist, and boron (B) and phosphorus (P) are sequentially ionized using each gate electrode (13) as a mask. By implanting, the source / drain regions (14) of the P-channel MOS type transistor ( 11 ) and the source / drain regions (17) of the N-channel MOS type transistor ( 15 ) are respectively formed and the manufacturing process is completed.

According to this manufacturing method, since the emitter region (9) of the bipolar transistor (7) is formed independently of the source / drain region (17) of the N-channel MOS transistor ( 15 ), the emitter region (9) is formed. ) Impurity concentration
It can be formed sufficiently high as 10 ²⁰ cm ^-3 and deep enough so that the base width becomes small. Therefore, high h _FE , high f
High performance bipolar transistor with _T and high Icmax ( 7 )
Can be realized. Moreover, the MOS transistor ( 11 ) ( 1
5 ) An essential step for forming, that is, imparting conductivity to the non-doped polycrystalline silicon layer (23) having an insulating property,
The emitter region (9) of the bipolar transistor ( 7 ) is formed by using the step of introducing phosphorus (P) into the polycrystalline silicon layer (23) in order to obtain a high speed device by reducing the resistance of the gate electrode (13). Since it is formed, there is an advantage that the process can be simplified as compared with the case where the emitter region (9) is formed solely. Also, the base region (8) and the emitter region (9)
Can be controlled independently of the characteristics of the MOS transistor ( 11 ) ( 15 ), and since the heat treatment at high temperature for a long time is not required after forming the emitter region (9), the bipolar transistor ( 7 ) h _FE can be controlled relatively easily.

(G) Effect of the Invention As described above, according to the present invention, the impurity concentration of the emitter region (9) can be made sufficiently high and the diffusion depth can be formed sufficiently deep, so that a bipolar transistor ( 7 ) having good characteristics can be realized. It has the advantage that it can. Further, when the emitter region (9) is formed, it is formed by positively utilizing the steps essential for the MOS type transistors ( 11 ) ( 15 ) using polycrystalline silicon for the gate electrode (13). It has an advantage that the process can be simplified as compared with the case where only one is formed. Furthermore, since the source / drain regions (14) (17) of the MOS type transistors ( 11 ) ( 15 ) and the base / emitter regions (8) (9) of the bipolar type transistor ( 7 ) can be controlled independently, It has the advantage that good MOS transistors ( 11 ) ( 15 ) and bipolar transistors ( 7 ) can coexist.

[Brief description of drawings]

1A to 1G are sectional views showing the manufacturing method of the present invention in the order of steps, and FIG. 2 is a sectional view for explaining a conventional example. (1) is a P type semiconductor substrate, ( 7 ) is a bipolar type transistor, (8) is a P type base region, (9) is an N ⁺ type emitter region, ( 11 ) is a P channel MOS type transistor, (1)
3) is a gate electrode, ( 15 ) is an N-channel MOS transistor, (23) is a polycrystalline silicon layer, and (24) is a ring lath film.

Claims (1)

[Claims] 1. A method of manufacturing a semiconductor device in which a MOS type transistor and a bipolar type transistor are formed on the same semiconductor substrate, wherein a thin insulating film serving as a gate insulating film of the MOS type transistor is formed on a surface of an element forming region of the MOS type transistor. A step of forming a film, a step of forming a polycrystalline silicon layer serving as a gate electrode of the MOS type transistor on the entire surface, and a step of forming the polycrystalline silicon on the emitter region formed on the surface of one conductivity type base region of the bipolar type transistor. A step of removing a silicon layer, and a step of introducing an impurity of opposite conductivity type into the polycrystalline silicon layer, and at the same time diffusing the impurity of opposite conductivity type into a base region surface of the bipolar transistor to form an emitter region. A step of forming a gate electrode of the MOS transistor by selectively etching the polycrystalline silicon layer. An impurity of one conductivity type and an impurity of opposite conductivity type are respectively introduced using the gate electrode as a mask to form a source / drain region of a MOS transistor of one conductivity type and a source / drain region of a MOS transistor of opposite conductivity type. And a step of forming each of them.