JPH0732209B2 - Ceramic container for semiconductor device - Google Patents

Ceramic container for semiconductor device

Info

Publication number
JPH0732209B2
JPH0732209B2 JP63034456A JP3445688A JPH0732209B2 JP H0732209 B2 JPH0732209 B2 JP H0732209B2 JP 63034456 A JP63034456 A JP 63034456A JP 3445688 A JP3445688 A JP 3445688A JP H0732209 B2 JPH0732209 B2 JP H0732209B2
Authority
JP
Japan
Prior art keywords
lid
layer
plating
ceramic
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP63034456A
Other languages
Japanese (ja)
Other versions
JPH01208845A (en
Inventor
召三 野口
佐藤  修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63034456A priority Critical patent/JPH0732209B2/en
Publication of JPH01208845A publication Critical patent/JPH01208845A/en
Publication of JPH0732209B2 publication Critical patent/JPH0732209B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Casings For Electric Apparatus (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用セラミック容器に関し、特に中空
部を有し、この中空部に半導体素子を収納した後、蓋部
材で気密封止する構造の半導体装置用セラミック容器に
関するものである。
Description: TECHNICAL FIELD The present invention relates to a ceramic container for a semiconductor device, and particularly to a structure having a hollow portion in which a semiconductor element is housed and then hermetically sealed with a lid member. The present invention relates to a ceramic container for a semiconductor device.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置用セラミック容器は、第3図
(a),(b)に示すように、半導体素子を載置し、半
導体素子の電極を外部に導出するための金属配線層2の
設けられたセラミック基板1上に、中央部が中空で上部
表面に蓋部材を取付ける為の蓋部金属化層5を有するセ
ラミック枠体3aを重ね一体焼成されたセラミック積層体
に、外部回路接続用の導出端子4をろう材を用い取付け
た後、半導体素子の固着ならびに半導体素子の電極と金
属配線層2とを電気的に接続する金属細線の結合を容易
にし、かつ蓋部材の取付けを容易にするために、金属配
線層2、蓋部金属化層5及び導出端子4の各表面には、
Ni及びAuの2層の配線めっき層7,蓋部めっき層8が電気
めっき法等により被覆形成された構造となっていた。
Conventionally, as shown in FIGS. 3A and 3B, a ceramic container for a semiconductor device of this type has a metal wiring layer 2 for mounting a semiconductor element and leading an electrode of the semiconductor element to the outside. On the ceramic substrate 1 provided, a ceramic frame 3a having a hollow central portion and a lid metallizing layer 5 for attaching a lid member to the upper surface is stacked and integrally fired, for connecting an external circuit. After attaching the lead-out terminal 4 of Fig. 1 by using a brazing material, it is easy to fix the semiconductor element and to bond the thin metal wire for electrically connecting the electrode of the semiconductor element and the metal wiring layer 2, and to easily attach the lid member. In order to do so, each surface of the metal wiring layer 2, the lid metallization layer 5 and the lead-out terminal 4 is
The structure was such that the two-layer wiring plating layer 7 of Ni and Au and the lid plating layer 8 were formed by coating by electroplating or the like.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

しかるに、上述した従来の半導体装置用セラミック容器
は、セラミック基板1上の金属配線層2及びこれらと電
気的に接続されている導出端子4には、導出端子4を利
用して電気めっきによりNi及びAuの配線めっき層7を容
易に被覆形成することができるが、セラミック枠体3a上
に設けられた蓋部金属化層5は導出端子4と電気的に絶
縁されている為、電気めっきを行なう際には、金属ワイ
ヤーを用いて導出端子4と結線するか、あるいはめっき
用治具に設けられた針状の導通ピンを蓋部金属化層5に
接触させて電気的導通をとることによりNi及びAuの蓋部
めっき層8を被覆形成する構成となっていた。
However, in the above-described conventional ceramic container for a semiconductor device, the metal wiring layer 2 on the ceramic substrate 1 and the lead-out terminal 4 electrically connected to the metal wiring layer 2 are Ni and Ni by electroplating using the lead-out terminal 4. The Au wiring plating layer 7 can be easily formed by coating, but since the lid metallization layer 5 provided on the ceramic frame 3a is electrically insulated from the lead-out terminal 4, electroplating is performed. At this time, by connecting to the lead-out terminal 4 with a metal wire, or by bringing a needle-shaped conductive pin provided on the plating jig into contact with the lid metallized layer 5 to establish electrical conduction, And the lid plating layer 8 of Au is formed by coating.

このため、電気めっきの際にセラミック枠体3a上の蓋部
金属化層5を電気的に接続すくことが困難で作業性が悪
く、高価になるという欠点に加え、金属ワイヤーあるい
は導通ピンの接触を確実に行なおうとする蓋部金属化層
5との接触部にめっきが被覆されず、また金属ワイヤ
ー、導通ピンとの接触を緩くすると、密着の悪いめっき
層が形成されたり厚さが不均一となり、いづれの場合に
於ても、低融点のろう材を用い蓋部材を気密封止する際
に、ろう材の濡れが悪く気密不良を生じたり、めっき層
が剥離して蓋部材が脱落するという信頼性品質上の欠点
があった。
For this reason, it is difficult to electrically connect the lid metallization layer 5 on the ceramic frame 3a during electroplating, resulting in poor workability and high cost, as well as contact with metal wires or conductive pins. When the contact portion with the lid metallized layer 5 is not covered with plating and the contact with the metal wire or the conduction pin is loosened, a poorly adhered plating layer is formed or the thickness is uneven. In any case, when the lid member is hermetically sealed using the low melting point brazing filler metal, the brazing filler metal is poorly wetted and causes poor airtightness, or the plating layer peels off and the lid member falls off. There was a drawback in terms of reliability and quality.

本発明の目的は、作業性が上り安価となり、気密不良や
蓋部材脱落を防止して信頼性品質の向上をはかることが
できる半導体装置用セラミック容器を提供することにあ
る。
An object of the present invention is to provide a ceramic container for a semiconductor device, which has improved workability, is inexpensive, can prevent airtightness and the lid member from falling off, and can improve reliability quality.

〔課題を解決するための手段〕[Means for Solving the Problems]

本発明の半導体装置用セラミック容器は、中央部に半導
体素子を搭載するためのセラミック基板と、このセラミ
ック基板上の中央部から周辺部へかけて形成され前記半
導体素子の電極と接続するための金属配線層、前記セラ
ミック基板上に、中央に前記半導体素子を収納するため
の中空部をもち前記セラミック基板と一体形成されたセ
ラミック枠体と、このセラミック枠体の外側で前記金属
配線層と接続する外部回路接続用の導出端子と、前記セ
ラミック枠体上部表面に形成され蓋部材を取付けるため
の蓋部金属化層と、この蓋部金属化層と接続しかつ前記
金属配線層及び導出端子と絶縁され、前記セラミック枠
体から前記セラミック基板の周辺部にかけて形成され前
記セラミック枠体の外部へ導出された蓋部めっき用金属
化層と、この蓋部めっき用金属化層及び前記導出端子を
電極として前記金属配線層、導出端子及び蓋部金属化層
の各表面に形成されためっき層とを有している。
A ceramic container for a semiconductor device of the present invention is a ceramic substrate for mounting a semiconductor element in a central portion, and a metal for connecting to an electrode of the semiconductor element formed from the central portion to the peripheral portion on the ceramic substrate. A wiring layer, a ceramic frame body having a hollow portion for accommodating the semiconductor element in the center on the ceramic substrate and integrally formed with the ceramic substrate, and the metal wiring layer is connected to the outside of the ceramic frame body. A lead terminal for connecting an external circuit, a lid metallization layer formed on the upper surface of the ceramic frame for attaching a lid member, connected to the lid metallization layer, and insulated from the metal wiring layer and the lead terminal. And a lid plating metallization layer formed from the ceramic frame to the peripheral portion of the ceramic substrate and led out of the ceramic frame, and the lid. The metal wiring layer metallization layer and the leading terminals use the Ki Tsu as an electrode, and a lead-out terminal and plating layer formed on the surface of the lid portion metallization layer.

また、セラミック基板周辺外側に、導出端子及び蓋部め
っき用金属化層と共通接続し金属配線層、前記導出端子
及び蓋部金属化層の各表面にめっき層を形成後前記導出
端子及び蓋部めっき用金属化層と切断されるめっき用リ
ード電極を設けた構成を有している。
Further, outside the periphery of the ceramic substrate, the lead terminal and the lid are commonly connected to the plating metallization layer, and after forming a plating layer on each surface of the metal wiring layer, the lead terminal and the lid metallization layer, the lead terminal and the lid. It has a structure in which a plating metallization layer and a plating lead electrode to be cut are provided.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a),(b)はそれぞれ本発明の第1の実施例
を示す平面図及びA−A′断面図である。
1 (a) and 1 (b) are a plan view and an AA 'sectional view showing a first embodiment of the present invention, respectively.

この実施例は、中央部に半導体素子を搭載するためのセ
ラミック基板1と、このセラミック基板1上の中央部か
ら周辺部へかけて形成され、半導体素子の電極と接続す
るための金属配線層2と、セラミック基板1上に、中央
に半導体素子を収納するための空中部をもちセラミック
基板1と一体焼成されたセラミック枠体3と、このセラ
ミック枠体3の外側で金属配線層2とろう材で接続する
外部回路接続用の導出端子4と、セラミック枠体3の上
部に形成され蓋部材を取付けるための蓋部金属化層5
と、この蓋部金属化層5と接続しかつ金属配線層22及び
導出端子4と絶縁され、セラミック枠体3の側面からセ
ラミック基板1の周辺部にかけて形成され、セラミック
枠体3の外部へ導出された蓋部めっき用金属化層6と、
この蓋部めっき用金属化層6及び導出端子4を電極とし
て電気めっき法により、金属配線層2,導出端子4の各表
面に形成された配線めっき層7及び蓋部金属化層5の表
面に形成された蓋部めっき層8とを備えた構成となって
いる。
In this embodiment, a ceramic substrate 1 for mounting a semiconductor element in the central portion thereof, and a metal wiring layer 2 for connecting to the electrodes of the semiconductor element, which is formed from the central portion to the peripheral portion of the ceramic substrate 1. A ceramic frame body 3 having an aerial portion for accommodating semiconductor elements in the center on the ceramic substrate 1 and integrally fired with the ceramic substrate 1, and a metal wiring layer 2 and a brazing material on the outside of the ceramic frame body 3. External circuit connection lead-out terminal 4 to be connected by means of, and lid metallization layer 5 formed on the top of ceramic frame 3 for attaching a lid member.
And is connected to the lid metallization layer 5 and insulated from the metal wiring layer 22 and the lead-out terminal 4, is formed from the side surface of the ceramic frame 3 to the peripheral portion of the ceramic substrate 1, and is led out of the ceramic frame 3. The metallized layer 6 for plating the lid,
On the surface of the metal plating layer 7 and the lid metallization layer 5 formed on each surface of the metal wiring layer 2 and the lead-out terminal 4 by electroplating with the metallization layer 6 for lid plating and the lead-out terminal 4 as electrodes. The lid plating layer 8 thus formed is provided.

従って、蓋部めっき用金属化層6を電極として蓋部金属
化層5に触れることなくこと表面に電気めっきすること
ができ、作業性がよく均一かつ確実にめっき層を形成す
ることができる。この結果、蓋部材の密着がよく、気密
不良を防止することができる。
Therefore, the metallization layer 6 for plating the lid can be used as an electrode for electroplating the surface without touching the metallization 5 for the lid, and the plating layer can be formed uniformly and reliably with good workability. As a result, the lid member adheres well, and poor airtightness can be prevented.

第2図は本発明の第2の実施例の中間工程における半導
体装置用セラミック容器の平面図である。
FIG. 2 is a plan view of a ceramic container for a semiconductor device in an intermediate step of the second embodiment of the present invention.

この実施例においては、セラミック基板1周辺外側に、
金属配線層2と接続する導出端子4と同一材料で一体形
成され、蓋部めっき用金属化層6と接続するめっき用リ
ード電極9を設け、このめっき用リード電極9を電極と
して、電気めっき法により金属配線層2,導出端子4及び
蓋部金属化層5の各表面にめっき層を形成後、切断線10
の部分で切断する構成となっている。
In this embodiment, outside the periphery of the ceramic substrate 1,
A lead electrode 9 for plating, which is integrally formed of the same material as the lead-out terminal 4 connected to the metal wiring layer 2 and connected to the metallization layer 6 for lid plating, is provided, and the lead electrode 9 for plating is used as an electrode for electroplating. After forming a plating layer on each surface of the metal wiring layer 2, lead-out terminal 4 and lid metallization layer 5 by
It is configured to be cut at the part.

従って、電気めっき用の電極接続が極めて容易になると
いう利点がある。
Therefore, there is an advantage that connection of electrodes for electroplating becomes extremely easy.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、セラミック枠体上部表面
に設けられた蓋部金属化層と接続しセラミック枠体の外
部へ導出する蓋部めっき用金属化層を設け、これを電気
めっき用の電極として蓋部金属化層の表面にめっき層を
形成する構成とすることにより、蓋部金属化層に触れず
に確実に電気めっき用の電極と接続することができるの
で、蓋部金属化層の表面全体に密着が良くかつ厚さの均
一なめっき層を作業性良く被覆形成することができ、気
密不良や蓋部材脱落を防止し、安価で信頼性品質に優れ
た半導体装置用セラミック容器を得ることができる効果
がある。
INDUSTRIAL APPLICABILITY As described above, the present invention provides a lid plating metallization layer which is connected to the lid metallization layer provided on the upper surface of the ceramic frame body and is led out to the outside of the ceramic frame body. By forming the plating layer on the surface of the lid metallization layer as an electrode, it is possible to reliably connect to the electrode for electroplating without touching the lid metallization layer. A ceramic container for a semiconductor device that can form a plating layer with good adhesion and uniform thickness over the entire surface of the device with good workability, prevent airtightness and falling of the lid member, and be inexpensive and have excellent reliability quality. There is an effect that can be obtained.

また、導出端子4及び蓋部めっき用金属化層と接続する
めっき用リード電極を設けることにより、更に作業性を
向上させることができる効果がある。
Further, by providing the lead electrode for plating which is connected to the lead-out terminal 4 and the metallized layer for plating the lid, workability can be further improved.

【図面の簡単な説明】[Brief description of drawings]

第1図(a),(b)はそれぞれ本発明の第1の実施例
を示す平面図及びA−A′断面図、第2図は本発明の第
2の実施例の中間工程における半導体装置用セラミック
容器の平面図、第3図(a),(b)はそれぞれ従来の
半導体装置用セラミック容器の一例の平面図及びA−
A′断面図である。 1…セラミック基板、2…金属配線層、3,3a…セラミッ
ク枠体、4…導出端子、5…蓋部金属化層、6…蓋部め
っき用金属化層、7…配線めっき層、8…蓋部めっき
層、9…めっき用リード電極、10…切断線。
1 (a) and 1 (b) are a plan view and a sectional view taken along the line AA 'of the first embodiment of the present invention, respectively, and FIG. 2 is a semiconductor device in an intermediate step of the second embodiment of the present invention. 3A and 3B are plan views of a conventional ceramic container for a semiconductor device and FIG. 3A and FIG.
It is an A'cross section figure. DESCRIPTION OF SYMBOLS 1 ... Ceramic substrate, 2 ... Metal wiring layer, 3, 3a ... Ceramic frame, 4 ... Derivation terminal, 5 ... Lid metallization layer, 6 ... Lid plating metallization layer, 7 ... Wiring plating layer, 8 ... Lid plating layer, 9 ... Lead electrode for plating, 10 ... Cutting line.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】中央部に半導体素子を搭載するためのセラ
ミック基板と、このセラミック基板上の中央部から周辺
部へかけて形成され前記半導体素子の電極と接続するた
めの金属配線層、前記セラミック基板上に、中央に前記
半導体素子を収納するための中空部をもち前記セラミッ
ク基板と一体形成されたセラミック枠体と、このセラミ
ック枠体の外側で前記金属配線層と接続する外部回路接
続用の導出端子と、前記セラミック枠体上部表面に形成
され蓋部材を取付けるための蓋部金属化層と、この蓋部
金属化層と接続しかつ前記金属配線層及び導出端子と絶
縁され、前記セラミック枠体から前記セラミック基板の
周辺部にかけて形成され前記セラミック枠体の外部へ導
出された蓋部めっき用金属化層と、この蓋部めっき用金
属化層及び前記導出端子を電極として前記金属配線層、
導出端子及び蓋部金属化層の各表面に形成されためっき
層とを有することを特徴とする半導体装置用セラミック
容器。
1. A ceramic substrate on which a semiconductor element is mounted in the central portion, a metal wiring layer formed from the central portion to the peripheral portion of the ceramic substrate for connecting to an electrode of the semiconductor element, and the ceramic. A ceramic frame body integrally formed with the ceramic substrate having a hollow portion for accommodating the semiconductor element on the substrate, and an external circuit connecting outside the ceramic frame body to the metal wiring layer. A lead terminal, a lid metallization layer formed on the upper surface of the ceramic frame for attaching a lid member, connected to the lid metallization layer, and insulated from the metal wiring layer and the lead terminal, and the ceramic frame A metallization layer for plating the lid, which is formed from the body to the periphery of the ceramic substrate and is led out to the outside of the ceramic frame, and the metallization layer for plating the lid and the conductor. The metal wiring layer terminal as an electrode,
A ceramic container for a semiconductor device, comprising: a lead-out terminal and a plating layer formed on each surface of the lid metallization layer.
【請求項2】セラミック基板周辺外側に、導出端子及び
蓋部めっき用金属化層と共通接続し金属配線層、前記導
出端子及び蓋部金属化層の各表面にめっき層を形成後前
記導出端子及び蓋部めっき用金属化層と切断されるめっ
き用リード電極を設けた請求項(1)記載の半導体装置
用セラミック容器。
2. A lead-out terminal after forming a plating layer on each surface of the metal wiring layer, the lead-out terminal and the lid-portion metallization layer on the outside of the periphery of the ceramic substrate in common connection with the lead-out terminal and the lid-plating metallization layer. The ceramic container for a semiconductor device according to claim 1, further comprising a metallizing layer for plating the lid and a lead electrode for plating that is cut.
JP63034456A 1988-02-16 1988-02-16 Ceramic container for semiconductor device Expired - Lifetime JPH0732209B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63034456A JPH0732209B2 (en) 1988-02-16 1988-02-16 Ceramic container for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63034456A JPH0732209B2 (en) 1988-02-16 1988-02-16 Ceramic container for semiconductor device

Publications (2)

Publication Number Publication Date
JPH01208845A JPH01208845A (en) 1989-08-22
JPH0732209B2 true JPH0732209B2 (en) 1995-04-10

Family

ID=12414750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63034456A Expired - Lifetime JPH0732209B2 (en) 1988-02-16 1988-02-16 Ceramic container for semiconductor device

Country Status (1)

Country Link
JP (1) JPH0732209B2 (en)

Also Published As

Publication number Publication date
JPH01208845A (en) 1989-08-22

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