JPH0732309B2 - Method of manufacturing imposition mounted printed circuit board - Google Patents
Method of manufacturing imposition mounted printed circuit boardInfo
- Publication number
- JPH0732309B2 JPH0732309B2 JP62236186A JP23618687A JPH0732309B2 JP H0732309 B2 JPH0732309 B2 JP H0732309B2 JP 62236186 A JP62236186 A JP 62236186A JP 23618687 A JP23618687 A JP 23618687A JP H0732309 B2 JPH0732309 B2 JP H0732309B2
- Authority
- JP
- Japan
- Prior art keywords
- imposition
- layer
- copper foil
- mask layer
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、集積回路のリード等の面付け部品が接続され
る面付けランドを有する面付け実装プリント板の製造方
法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing an imposition mounting printed board having imposition lands to which imposition components such as leads of an integrated circuit are connected.
従来の面付け実装プリント板は、例えば、特開昭61−15
2090号公報に記載されているように、薄層化等のための
外観形状、あるいは位置ずれ防止のための面付けランド
の形状等に主眼が置かれており、面付けランドの形成方
法、あるいは面付けランドの厚さ等に配慮がされていな
かった。A conventional imposition mounting printed circuit board is disclosed, for example, in JP-A-61-115.
As described in Japanese Patent No. 2090, the main focus is on the appearance shape for thinning or the like, or the shape of the imposition land for preventing misalignment, a method for forming the imposition land, or No consideration was given to the thickness of the imposition land.
従来の面付け実装プリント板の製造方法について、第2
図〜第5図に一般的なサブトラクティブ法による面付け
ランドの形成工程断面図を示す。Regarding the conventional method of manufacturing an imposition mounting printed circuit board,
FIGS. 5A to 5C show sectional views of the forming process of the imposition land by the general subtractive method.
また、第6図〜第9図に化学銅めっきを用いたアディテ
ィブ法による面付けランドの形成工程断面図を示す。以
下、それぞれの工程の詳細な説明を行なう。Further, FIGS. 6 to 9 are sectional views showing a process of forming imposition lands by an additive method using chemical copper plating. Hereinafter, a detailed description of each step will be given.
まず、従来のサブトラクティブ法の一例について説明す
る。まず、第2図に示すように、銅箔2が形成された銅
張り積層板1の所定位置に部品接続挿入用の貫通孔3を
設ける。次いで、貫通孔3の内壁を含む銅張り積層板1
の全面に化学銅めっきを析出させるための触媒層9を設
けた後、触媒層9を設けた全面に、薄付け化学銅めっき
(電気銅めっき)層4を所定の厚さ析出させ、第3図の
状態となる。次いで、回路を形成すべき所定の部分にエ
ッチングレジスト層5(通常、感光性ドライフィルムを
用いる)を形成し、第4図の状態となる。続いて、第5
図に示すように、レジスト層5をエッチングマスクとし
て所定回路部分以外の銅めっき層4および銅箔2をエッ
チングにより除去した後、必要部分に後の工程で必要と
なるはんだ付けに耐え得る永久ソルダーレジスト層8を
印刷法または露光法により塗布形成し、貫通孔導体10お
よび面付けランド7を形成する。First, an example of the conventional subtractive method will be described. First, as shown in FIG. 2, a through hole 3 for inserting and connecting a component is provided at a predetermined position of the copper-clad laminate 1 on which the copper foil 2 is formed. Next, the copper-clad laminate 1 including the inner wall of the through hole 3
After providing the catalyst layer 9 for depositing the chemical copper plating on the entire surface of, the thin chemical copper plating (electrolytic copper plating) layer 4 is deposited on the entire surface provided with the catalyst layer 9 to a predetermined thickness, It becomes the state of the figure. Next, an etching resist layer 5 (usually using a photosensitive dry film) is formed on a predetermined portion where a circuit is to be formed, and the state shown in FIG. 4 is obtained. Then, the fifth
As shown in the figure, after the copper plating layer 4 and the copper foil 2 other than the predetermined circuit portion are removed by etching using the resist layer 5 as an etching mask, a permanent solder capable of withstanding soldering required in a subsequent step in a necessary portion. The resist layer 8 is applied and formed by a printing method or an exposure method to form the through hole conductor 10 and the imposition land 7.
すなわち、本方法は、貫通孔3の内壁を含む銅張り積層
板1の全面に銅めっき層4を形成した後、レジスト層5
を用いて銅箔2および銅めっき層4を同時にパターニン
グすることを特徴とする。That is, in this method, after forming the copper plating layer 4 on the entire surface of the copper-clad laminate 1 including the inner wall of the through hole 3, the resist layer 5 is formed.
Is used to simultaneously pattern the copper foil 2 and the copper plating layer 4.
次に、従来のアディティブ法の一例について説明する。
まず、第6図に示すように、銅箔2が形成された銅張り
積層板1の所定位置に貫通孔3を設け、貫通孔3の内壁
を含む銅張り積層板1の全面に化学銅めっき層析出用の
触媒層9を形成する(ここまでは、上記サブトラクティ
ブ法と同じである)。その後、所定回路部分にエッチン
グレジスト層5(通常、感光性ドライフィルム)を形成
し、第7図の状態となる。次いで、レジスト層5をマス
クとして所定回路部分以外の銅箔2をエッチングにより
除去した後、レジスト層5を除去し、続いて、必要部分
に化学銅めっき工程およびはんだ付け工程に耐え得る永
久ソルダーレジスト層8を印刷法または露光法により塗
布形成すると、第8図に示す状態となる。次に、露出し
ている部分に第9図に示すように化学銅めっき層4を析
出させ、貫通孔導体10および面付けランド7を形成す
る。Next, an example of the conventional additive method will be described.
First, as shown in FIG. 6, a through hole 3 is provided at a predetermined position of a copper clad laminate 1 on which a copper foil 2 is formed, and the entire surface of the copper clad laminate 1 including the inner wall of the through hole 3 is chemically plated with copper. A catalyst layer 9 for layer deposition is formed (up to this point, it is the same as the subtractive method). Then, an etching resist layer 5 (usually a photosensitive dry film) is formed on a predetermined circuit portion, and the state shown in FIG. 7 is obtained. Next, the copper foil 2 other than the predetermined circuit portion is removed by etching using the resist layer 5 as a mask, and then the resist layer 5 is removed, and subsequently, a necessary portion is a permanent solder resist capable of withstanding the chemical copper plating step and the soldering step. When the layer 8 is formed by coating by the printing method or the exposure method, the state shown in FIG. 8 is obtained. Next, a chemical copper plating layer 4 is deposited on the exposed portion as shown in FIG. 9 to form a through hole conductor 10 and an imposition land 7.
すなわち、本方法は、貫通孔3の内壁を含む銅張り積層
板1の全面に、銅めっき層析出用の触媒層9を形成した
後、レジスト層5を用いて、まず、銅箔2をパターニン
グした後、所定部分に永久ソルダーレジスト層8を形成
し、その後、触媒層9が残っている部分に化学銅めっき
層4を析出させることを特徴とする。That is, in this method, after the catalyst layer 9 for depositing a copper plating layer is formed on the entire surface of the copper-clad laminate 1 including the inner wall of the through hole 3, the copper foil 2 is first formed using the resist layer 5. After patterning, the permanent solder resist layer 8 is formed on a predetermined portion, and then the chemical copper plating layer 4 is deposited on the portion where the catalyst layer 9 remains.
次に、面付けランドにめっきを析出させない従来の方法
の一例について説明する。例えば、特公昭55−43274号
公報、特開昭55−75288号公報に記載されているよう
に、第10図〜第12図に示すごとく、めっき工程前に、め
っき不要部に感光性フィルムレジスト11を貼り付け、め
っき工程後に、表面を露出させる導体部分の感光性フィ
ルムレジスト11を剥離除去するものである。Next, an example of a conventional method in which plating is not deposited on the imposition land will be described. For example, as described in JP-B-55-43274 and JP-A-55-75288, as shown in FIG. 10 to FIG. 11 is attached, and after the plating step, the photosensitive film resist 11 on the conductor portion which exposes the surface is peeled and removed.
上述のサブトラクティブ法のように、面付け実装プリン
ト板の面付けランド7を形成するため、銅箔2および化
学銅めっき層4をエッチングにより同時に除去すると、
析出により形成される化学銅めっき層4の厚さにバラツ
キがあるため、形成された面付けランド7の形状にバラ
ツキが発生する問題があった。When the copper foil 2 and the chemical copper plating layer 4 are simultaneously removed by etching in order to form the imposition land 7 of the imposition mounting printed board as in the subtractive method described above,
Since the thickness of the chemical copper plating layer 4 formed by deposition varies, there is a problem that the shape of the formed imposition land 7 varies.
また、上述のアディティブ法のように、銅箔2をエッチ
ングによりパターニングした後、化学銅めっき層4を析
出させると、面付けランド7の側面にも化学銅めっき層
4が析出するので、面付けランド7どうしの間隙寸法が
小さくなり、高密度に面付けランド7を設けた場合、ラ
ンド7間で短絡が発生し易くなり、高密度の面付け実装
に対応できなくなる。Further, when the chemical copper plating layer 4 is deposited after the copper foil 2 is patterned by etching as in the above-described additive method, the chemical copper plating layer 4 is also deposited on the side surface of the imposition land 7. When the gap size between the lands 7 becomes small and the imposition lands 7 are provided at a high density, a short circuit easily occurs between the lands 7 and it becomes impossible to cope with high density imposition mounting.
このように、上述の従来技術では、面付けランドの製造
法、厚さ、形状、間隔のバラツキ、あるいは高密度化に
よるランド間の短絡について考慮されておらず、そのた
め、面付け実装作業工程の作業性、および品質面に問題
があった。As described above, the above-described conventional technique does not consider variations in the manufacturing method, thickness, shape, and spacing of the imposition lands, or short circuits between lands due to high density. There was a problem in workability and quality.
また、上述の感光性フィルムレジスト11で部分的にマス
キングしてめっきが析出しないようにし、めっき工程後
に除去する方法では、フィルムレジストを用いるため、
凹凸の追従性が悪く、導体パターン間にすき間12が生じ
て、めっき工程において、そのすき間12にめっき液がし
み込み、面付けランド間を汚染してしまう問題があっ
た。Further, in order to prevent plating from being partially masked by the above-mentioned photosensitive film resist 11 to prevent plating from being deposited, the method of removing after the plating step uses a film resist,
There is a problem that the conformability of the unevenness is poor, and a gap 12 is formed between the conductor patterns, and the plating solution permeates into the gap 12 in the plating step and contaminates the imposition lands.
本発明の目的は、面付け実装作業の作業性向上、品質向
上ならびに、高精度の面付けランドを製造することにあ
る。An object of the present invention is to improve workability and quality of imposition mounting work, and to manufacture an imposition land with high accuracy.
上記目的は、面付け実装プリント板の面付けランドを銅
張り積層板の銅箔のみで形成することにより達成され
る。The above-mentioned object is achieved by forming the imposition lands of the imposition-mounting printed board with only the copper foil of the copper-clad laminate.
すなわち、本発明の面付け実装プリント板の製造方法
は、表面に銅箔を有する基板で、該基板に形成された貫
通孔の内壁を含む該基板の表面にめっき層析出用触媒層
を形成する工程と、上記銅箔上の所定の部分にエッチン
グレジスト層を形成する工程と、上記エッチングレジス
ト層をマスクとして上記銅箔をエッチング除去する工程
と、少なくとも上記銅箔上を銅めっき工程に耐え得るマ
スク層で覆う工程と、少なくとも上記貫通孔の内壁を含
む所定の領域上にめっき層を所定の厚さに析出させる工
程と、少なくとも一部の上記銅箔上の上記マスク層を除
去する工程とを含み、かつ、上記マスク層が上記貫通孔
および表面に露出させる必要のある部分を除く所定の領
域上を覆う第1のマスク層と、上記貫通孔を除き、少な
くとも一部の上記銅箔上を覆う第2のマスク層からな
り、上記第2のマスク層は印刷法または露光法により塗
布形成するレジスト層からなり、かつ、上記マスク層を
除去する工程において、上記第2のマスク層のみを除去
することを特徴とする。That is, the method for manufacturing an imposition-mounted printed board of the present invention is a substrate having a copper foil on the surface, and a plating layer deposition catalyst layer is formed on the surface of the substrate including the inner walls of through holes formed in the substrate. A step of forming an etching resist layer at a predetermined portion on the copper foil, a step of etching away the copper foil using the etching resist layer as a mask, and at least resisting a copper plating step on the copper foil. A step of covering with a mask layer to be obtained, a step of depositing a plating layer to a predetermined thickness on a predetermined area including at least the inner wall of the through hole, and a step of removing the mask layer on at least a part of the copper foil And a first mask layer covering a predetermined region of the mask layer excluding the through hole and the portion that needs to be exposed on the surface, and at least a part of the copper except the through hole. A second mask layer that covers the upper surface, the second mask layer is a resist layer formed by coating by a printing method or an exposure method, and in the step of removing the mask layer, only the second mask layer is formed. Is removed.
また、上記第1のマスク層が、後の銅めっき工程および
はんだ付け工程に耐え得る永久ソルダーレジスト層であ
ることを特徴とする。Further, the first mask layer is a permanent solder resist layer capable of withstanding the subsequent copper plating step and soldering step.
析出により形成される銅めっき層の厚さにはバラツキが
あり、従って、形成された面付けランドの形状にバラツ
キが生じる。また、銅箔をエッチングした後に、銅めっ
きを析出させると、面付けランドの側面にも銅めっきが
析出し、面付けランドどうしの間隙寸法が小さくなり、
高密度化に対応できなくなる。このことから、面付けラ
ンドを銅張り積層板の銅箔のみで形成することにより、
銅めっき層の厚さのバラツキに起因する面付けランドの
形状のバラツキ、および面付けランドどうしの間隙寸法
の縮小化を防止できる。There is variation in the thickness of the copper plating layer formed by deposition, and thus the shape of the imposition land formed varies. In addition, when copper plating is deposited after etching the copper foil, copper plating is also deposited on the side surfaces of the imposition lands, and the gap dimension between the imposition lands becomes small,
It becomes impossible to cope with high density. From this, by forming the imposition land only with the copper foil of the copper-clad laminate,
It is possible to prevent variations in the shape of the imposition lands due to variations in the thickness of the copper plating layer and reduction in the gap size between the imposition lands.
また、本発明では、貫通孔を除き、少なくとも一部の銅
箔上をマスキングし、かつ、めっき工程後に除去する手
段として、印刷法または露光法により塗布形成するレジ
スト層を用いるので、凹凸追従性が良いため、導体パタ
ーンとの間にすき間が生じず、めっき液のしみ込みによ
る面付けランド間の汚染が発生しない。Further, in the present invention, since the resist layer formed by coating by a printing method or an exposure method is used as a means for masking at least a part of the copper foil except the through holes and removing it after the plating step, the unevenness followability Therefore, no gap is formed between the imprint pattern and the conductive pattern, and contamination of the imposition lands due to penetration of the plating solution does not occur.
本発明の面付け実装プリント板の製造方法の一実施例を
第1図(A)〜(F)の工程断面図に従って説明する。An embodiment of a method for manufacturing an imposition mounted printed board according to the present invention will be described with reference to process sectional views of FIGS.
まず、第1図(A)に示すように、銅箔2が形成された
銅張り積層板1(あるいは、積層プレスされた多層プリ
ント板基材)の所定位置に貫通孔3を設け、次いで、貫
通孔3の内壁を含む銅張り積層板1の全面に化学銅めっ
き層析出用触媒層9を形成する。次いで、所定回路部分
にエッチングレジスト層5を感光性ドライフィルムを用
いて形成し、第1図(B)に示す状態となる。次いで、
レジスト層5をマスクとして所定回路部分以外の不要な
銅箔2をエッチングにより溶解除去し、続いて、エッチ
ングレジスト層5も除去して、第1図(C)の状態とな
る。次に、銅めっき層を必要とする回路部分のみを露出
させる形状で、後の工程の化学銅めっきに耐え、なおか
つ、後の工程のはんだ付けにも耐え得る永久ソルダーレ
ジスト層8を印刷法または露光法により塗布形成し、第
1図(D)の状態となる。次いで、面付けランド7のみ
に、後の工程の化学銅めっきのみに耐えることができれ
ばよいソルダーレジスト層6′を印刷法または露光法に
より塗布形成するか、もしくはマスキングテープ6′を
貼り付け、第1図(E)の状態となる。次いで、第1図
(F)に示すように、露出している貫通孔3および導体
回路のみに化学銅めっき層4を所定の厚さに析出させ、
その後、面付けランド7上のソルダーレジスト層あるい
はマスキングテープ6′を除去し、完成状態の面付けラ
ンド7を有する面付け実装プリント板が製造される。こ
の方法で製造された面付け実装プリント板の面付けラン
ド7は、銅張り積層板1の銅箔2のみで形成されている
ため、面付けランド7の幅、面付けランド7どうしの間
隙寸法、並びに面付けランド7の厚さのバラツキが少な
いと共に、ランド7どうしの間隙が狭くなることもな
く、良好な面付け作業性と高品質を確保できる。First, as shown in FIG. 1 (A), a through hole 3 is provided at a predetermined position of a copper clad laminate 1 (or a multilayer printed board base material that has been laminated and pressed) on which a copper foil 2 is formed, and then, A catalyst layer 9 for depositing a chemical copper plating layer is formed on the entire surface of the copper-clad laminate 1 including the inner walls of the through holes 3. Next, an etching resist layer 5 is formed on a predetermined circuit portion using a photosensitive dry film, and the state shown in FIG. 1 (B) is obtained. Then
Using the resist layer 5 as a mask, unnecessary copper foil 2 other than the predetermined circuit portion is dissolved and removed by etching, and then the etching resist layer 5 is also removed to obtain the state of FIG. 1 (C). Next, a permanent solder resist layer 8 having a shape that exposes only a circuit portion requiring a copper plating layer and that can withstand chemical copper plating in a later step and can also withstand soldering in a later step is printed or printed. Application and formation is performed by the exposure method, and the state shown in FIG. Then, a solder resist layer 6'which is required to withstand only the chemical copper plating in the subsequent step is applied and formed only on the imposition land 7 by a printing method or an exposure method, or a masking tape 6'is attached. The state shown in FIG. 1 (E) is obtained. Then, as shown in FIG. 1 (F), a chemical copper plating layer 4 is deposited to a predetermined thickness only on the exposed through hole 3 and conductor circuit,
Then, the solder resist layer or the masking tape 6'on the imposition land 7 is removed, and the imposition mounting printed board having the imposition land 7 in a completed state is manufactured. Since the imposition land 7 of the imposition mounting printed board manufactured by this method is formed only by the copper foil 2 of the copper-clad laminate 1, the width of the imposition land 7 and the gap size between the imposition lands 7 In addition, the thickness of the imposition lands 7 varies little, and the gap between the lands 7 does not become narrow, so that good imposition workability and high quality can be secured.
以上説明したように、本発明の方法によれば、面付けラ
ンドの各部寸法のバラツキを抑制できるため、面付け部
品の面付け作業性が向上でき、あわせて面付け品質も向
上させることができる。As described above, according to the method of the present invention, it is possible to suppress the variation in the size of each part of the imposition land, and thus it is possible to improve the imposition workability of imposition parts and also improve the imposition quality. .
第1図(A)〜(F)は、本発明の面付け実装プリント
板の製造方法の一実施例を示す工程断面図、第2図〜第
5図は、従来の製造方法の一例の工程断面図を示す。第
6図〜第9図は、従来の製造方法の別の一例の工程断面
図、第10図〜第12図は、従来の製造方法のさらに別の一
例の工程断面図である。 1…銅張り積層板(プリント板基材) 2…銅張り積層板の銅箔 3…貫通孔 4…銅めっき層 5…エッチングレジスト層 6′…マスキングレジスト層あるいはマスキングテープ 7…面付けランド 8…永久レジスト層 9…触媒層 10…貫通孔導体1 (A) to 1 (F) are process cross-sectional views showing an embodiment of a method for manufacturing an imposition mounted printed board of the present invention, and FIGS. 2 to 5 are steps of an example of a conventional manufacturing method. A sectional view is shown. 6 to 9 are process cross-sectional views of another example of the conventional manufacturing method, and FIGS. 10 to 12 are process cross-sectional views of yet another example of the conventional manufacturing method. DESCRIPTION OF SYMBOLS 1 ... Copper-clad laminated board (print board base material) 2 ... Copper foil of a copper-clad laminated board 3 ... Through hole 4 ... Copper plating layer 5 ... Etching resist layer 6 '... Masking resist layer or masking tape 7 ... Imposition land 8 … Permanent resist layer 9… Catalyst layer 10… Through-hole conductor
Claims (2)
された貫通孔の内壁を含む該基板の表面にめっき層析出
用触媒層を形成する工程と、上記銅箔上の所定の部分に
エッチングレジスト層を形成する工程と、上記エッチン
グレジスト層をマスクとして上記銅箔をエッチング除去
する工程と、少なくとも上記銅箔上を銅めっき工程に耐
え得るマスク層で覆う工程と、少なくとも上記貫通孔の
内壁を含む所定の領域上にめっき層を所定の厚さに析出
させる工程と、少なくとも一部の上記銅箔上の上記マス
ク層を除去する工程とを含み、かつ、上記マスク層が、
上記貫通孔および表面に露出させる必要のある部分を除
く所定の領域上を覆う第1のマスク層と、上記貫通孔を
除き、少なくとも一部の上記銅箔上を覆う第2のマスク
層からなり、上記第2のマスク層は印刷法または露光法
により塗布形成するレジスト層からなり、かつ、上記マ
スク層を除去する工程において、上記第2のマスク層の
みを除去することを特徴とする面付け実装プリント板の
製造方法。1. A substrate having a copper foil on its surface, a step of forming a plating layer deposition catalyst layer on the surface of the substrate including the inner walls of through holes formed in the substrate, and a predetermined process on the copper foil. A step of forming an etching resist layer in a portion, a step of etching away the copper foil using the etching resist layer as a mask, a step of covering at least the copper foil with a mask layer capable of withstanding a copper plating step, at least the above A step of depositing a plating layer to a predetermined thickness on a predetermined region including the inner wall of the through hole, and a step of removing the mask layer on at least a part of the copper foil, and the mask layer is ,
It comprises a first mask layer covering a predetermined area excluding the through hole and a portion that needs to be exposed on the surface, and a second mask layer covering at least a part of the copper foil except the through hole. The second mask layer is composed of a resist layer applied and formed by a printing method or an exposure method, and in the step of removing the mask layer, only the second mask layer is removed. Manufacturing method of printed circuit board.
およびはんだ付け工程に耐え得る永久ソルダーレジスト
層であることを特徴とする特許請求の範囲第1項記載の
面付け実装プリント板の製造方法。2. The imposition mounted printed circuit board according to claim 1, wherein the first mask layer is a permanent solder resist layer that can withstand the subsequent copper plating step and soldering step. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62236186A JPH0732309B2 (en) | 1987-09-22 | 1987-09-22 | Method of manufacturing imposition mounted printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62236186A JPH0732309B2 (en) | 1987-09-22 | 1987-09-22 | Method of manufacturing imposition mounted printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6481299A JPS6481299A (en) | 1989-03-27 |
| JPH0732309B2 true JPH0732309B2 (en) | 1995-04-10 |
Family
ID=16997049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62236186A Expired - Lifetime JPH0732309B2 (en) | 1987-09-22 | 1987-09-22 | Method of manufacturing imposition mounted printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0732309B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0217697A (en) * | 1988-07-05 | 1990-01-22 | Mitsubishi Electric Corp | Manufacture of high-density printed circuit board |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5543274A (en) * | 1978-09-22 | 1980-03-27 | Ntn Toyo Bearing Co Ltd | Fuel injection device |
| JPS5575288A (en) * | 1978-12-01 | 1980-06-06 | Nippon Electric Co | Method of fabricating printed circuit board |
| JPS612386A (en) * | 1984-06-15 | 1986-01-08 | 株式会社日立製作所 | Method of producing printed circuit board |
| JPS61121391A (en) * | 1984-11-16 | 1986-06-09 | 松下電器産業株式会社 | Printed wiring board |
-
1987
- 1987-09-22 JP JP62236186A patent/JPH0732309B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6481299A (en) | 1989-03-27 |
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