JPH07327145A - Image display device - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide an image display device for a CRT receiver, which controls a difference in resolution between a central portion and a peripheral portion in a horizontal direction caused by flattening a display screen in a well-balanced manner. [Structure] Video output circuit 3 for providing video output to CRT 1
And D / which gives an analog video signal to the video output circuit 3.
An A converter 4, a line memory 5 for giving a digital video signal to the D / A converter 4, a deflection waveform generation circuit 6, and a read timing generation circuit 7 are provided, and the deflection output circuit 6 outputs a deflection output to the deflection yoke 2. And the read timing generation circuit 7 gives the read timing to the line memory 5, the difference in resolution between the central portion and the peripheral portion of the CRT 1 is controlled in a well-balanced manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device for displaying an image using a CRT, and is particularly effective for a display screen having a flat surface.

[0002]

2. Description of the Related Art A conventional image display device is disclosed, for example, in Japanese Patent Laid-Open No. 13176/1990. FIG. 13 is a block diagram showing a part of this conventional image display device. In FIG. 13, 101 is a horizontal deflection coil, 102 is a variable voltage source for the horizontal deflection coil 101, 103 is a damper diode, 104 is switching means using a transistor TR, and 105 is control means for controlling the variable voltage source 102. The control means 105 previously stores and holds digital control data corresponding to the shape of the display screen of the CRT 1 which is the scanning target by the horizontal deflection beam BM shown in FIG.
The voltage control signal Cv corresponding to the digital control data is sent to the variable voltage source 102.

The control means 105 has a generator 106 for transmitting a reference clock signal and a generator 10 for storing and holding digital control data (8 bits) in advance.
ROM 107 for sending digital control data based on the reference clock signal from D6, and D / A conversion of the digital control data from this ROM 107 to obtain the variable voltage source 10
2 to the D / A converter 108. Here, in the ROM 107, the horizontal deflection beam BM is previously stored.
14, digital control data corresponding to the shape of the display screen of the CRT 1 to be scanned, that is, as shown in FIG. 14, a horizontal deflection angle θ1 with respect to the end of the display screen, a scanning distance L1 with respect to the horizontal deflection angle θ1, and a display screen The digital control data necessary for horizontal scanning such as the horizontal deflection angle θ2 with respect to the central portion and the scanning distance L2 with respect to the horizontal deflection angle θ2 are stored and held.

In the conventional image display apparatus configured as described above, 8-bit digital control data is sent from the ROM 107 based on the reference clock signal from the generator 106 of the control means 105, and this digital control data is D The / A converter 108 converts the voltage control signal Cv, which is an analog signal, and supplies the voltage control signal Cv to the variable voltage source 102. As a result, the variable voltage source 102 outputs a minimum value to the horizontal deflection coil 101 in the waveform shown in FIG. 15A, that is, when the phase corresponds to the peripheral portion of the display screen of the CRT 1, the minimum value is obtained and the central portion of the display screen is scanned. The supply voltage VL whose value continuously changes so as to become the maximum value at the corresponding phase is supplied to the horizontal deflection coil 101, and the corrected horizontal deflection current as shown by the solid line in FIG. ILH flows. As a result, the values of the scanning distances L1 and L2 per unit time corresponding to the deflection angles θ1 and θ2 can be made equal, and the linearity in the horizontal direction is improved.

[0005]

In recent years, the flattening of the display screen of the CRT and the increase of the deflection angle for the purpose of shortening the overall length have been advanced, and the incident angle to the display screen has become large in the peripheral portion. Therefore, the conventional configuration as described above has a problem that significant deterioration in horizontal resolution and deterioration in luminance occur in the peripheral portion with respect to the central portion of the display screen. This will be described with reference to FIG.

FIG. 16 (a) shows a CRT1 when there are pulse inputs in the central portion and the peripheral portion of one horizontal scanning period.
The horizontal luminance distribution of the spot on the display screen is shown. Here, each width represented by two solid lines and two broken lines shows the size of the spot. Each pulse has a rising time and a falling time, and during the period from the rising to the falling, the spot is deflected from the solid line to the broken line at the central portion and the peripheral portion, respectively. At this time, due to the difference in the incident angle to the display screen, the beam density becomes small in the peripheral portion of the screen, and the luminance distribution becomes wider and lower than that in the central portion. That is, the horizontal spot diameter is large and the brightness is lowered. As a result, the horizontal resolution and the luminance are significantly deteriorated in the peripheral part with respect to the central part of the screen.

In view of the above points, an object of the present invention is to provide an image display device capable of balancing the resolution and brightness of the central portion and the peripheral portion of the display screen.

[0008]

In order to solve the above problems, the first invention of the present invention is to provide a video output circuit for providing a video output to a CRT, and a D / A for providing an analog video signal to the video output circuit. A converter, a line memory for giving a digital video signal to the D / A converter, a deflection waveform generating circuit for giving a deflection output to a deflection yoke, and a read timing generating circuit for giving a read timing to the line memory are provided. Is an image display device.

A second aspect of the present invention is a video output circuit for providing a video output to a CRT, a D / A converter for providing an analog video signal to the video output circuit, and the D / A.
A line memory that gives a digital video signal to the converter,
An auxiliary deflecting device for velocity-modulating an electron beam according to the horizontal deflection amount, an auxiliary deflecting waveform generating circuit for outputting an auxiliary deflecting waveform to the auxiliary deflecting device, and a read timing generating circuit for giving a read timing to the line memory are provided. An image display device characterized by the above.

According to a third aspect of the present invention, an auxiliary deflecting device for speed-modulating an electron beam, an auxiliary deflecting waveform amplifying circuit for outputting an auxiliary deflecting waveform to the auxiliary deflecting device, and an image for the auxiliary deflecting waveform amplifying circuit are provided. An image display device comprising a differentiating circuit for inputting a differential waveform of a signal.

A fourth aspect of the present invention is a video output circuit for giving a video output to a CRT, a D / A converter for giving an analog video signal to the video output circuit, and a digital signal for the D / A converter. Line memory for giving a video signal, a deflection waveform generating circuit for giving a deflection output to a deflection yoke, a read timing generating circuit for giving a read timing to the line memory, and the deflection based on the brightness / contrast information from the video output circuit. A deflection waveform control circuit for controlling the output waveform of the waveform generation circuit and a read timing control circuit for controlling the read timing of the read timing generation circuit based on the brightness / contrast information from the video output circuit are provided. It is an image display device.

Further, a fifth aspect of the present invention is a video output circuit for providing a video output to a CRT, a D / A converter for providing an analog video signal to the video output circuit, and the D / A.
A line memory that gives a digital video signal to the converter,
A deflection waveform generation circuit for giving a deflection output to a deflection yoke, a read timing generation circuit for giving a read timing to the line memory, a photoelectric conversion element provided at a predetermined position on a CRT display screen, and a display output by the photoelectric conversion element. A spot diameter detection circuit that detects the horizontal spot diameter based on the brightness distribution information of the spots on the screen, and an output waveform of the deflection waveform generation circuit based on the horizontal spot diameter information that is output by the spot diameter detection circuit. And a read timing control circuit that controls the read timing of the read timing generation circuit based on the horizontal spot diameter information on the display screen output from the spot diameter detection circuit. Is an image display device.

[0013]

According to the first aspect of the present invention, the deflection waveform generating circuit has a slow scanning speed in the peripheral portion of the screen and a high scanning speed in the central portion of the screen, and provides the timing for reading the video output in accordance with the above. The horizontal spot diameters in the central and peripheral areas of the screen are made close to each other to achieve a balanced horizontal resolution and brightness distribution in the central and peripheral areas of the screen.

According to the second aspect of the present invention, the auxiliary deflection waveform generating circuit having the above-mentioned structure generates velocity modulation in the direction opposite to the beam traveling direction at the peripheral portion of the screen and in the beam traveling direction at the central portion of the screen, and in response thereto. By giving the read timing of the video output, the horizontal spot diameters in the central part and the peripheral part of the screen are made close to each other, and the balanced horizontal resolution and brightness distribution are realized in the central part and the peripheral part of the screen.

According to a third aspect of the present invention, with the above-mentioned configuration, the auxiliary deflection waveform generating circuit generates a strong velocity modulation in the peripheral portion of the screen and a weak velocity modulation in the central portion of the screen at the abrupt change portion of the video signal, so that the central portion of the screen is changed. The horizontal spot diameters in the peripheral area are made close to each other to achieve a balanced horizontal resolution in the central area and the peripheral area of the screen.

According to a fourth aspect of the present invention, the deflection waveform control circuit controls the deflection waveform of the deflection waveform generation circuit according to the screen brightness, and the read timing control circuit controls the read timing of the read timing generation circuit. By doing so, even if the luminance changes, a well-balanced resolution and luminance are realized in the central portion and the peripheral portion of the screen.

According to a fifth aspect of the present invention, the photoelectric conversion element and the spot diameter detection circuit having the above-mentioned structure take in information on the horizontal spot diameter on the display screen, and based on this information, the deflection waveform control circuit causes the deflection waveform generation circuit. The deflection timing is controlled by the read timing control circuit, and the read timing control circuit controls the read timing of the read timing generation circuit to realize the correction of the temporal change in the balance of the brightness and resolution of the central portion and the peripheral portion of the screen.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an image display device in an embodiment of the first invention. In FIG. 1, 1 is a CRT, 2 is a deflection yoke, 3 is a video output circuit which gives a video output to the CRT 1, 4 is a D / A converter which gives an analog video signal to the video output circuit 3, and 5 is a D / A conversion. A line memory for giving a digital video signal to the device 4, a deflection waveform generation circuit 6 for giving a deflection output to the deflection yoke 2, and a read timing generation circuit 7 for giving a read timing to the line memory 5.

The operation of the image display device of this embodiment having the above-described structure will be described below. FIG. 6 shows changes in the video signal before and after passing through the line memory 5. First, a digital video signal having the same sampling width as the signal 1 is input to the line memory 5 and temporarily stored therein.
The input signal 1 is given a read timing by the read timing generation circuit 7, and is output as a digital video signal whose projection period changes according to each data like the signal 2. Here, the read timing will be described. Let V0 be the scanning speed on the display screen when horizontally scanning at a constant speed on the display screen, and V (t) be the scanning speed at each time when the scanning speed is changed according to the scanning position in this embodiment. To do. Here, t is the elapsed time from the beginning of scanning. In order to obtain the same output at the same position on the display screen in the case of constant velocity scanning and the case of velocity modulation scanning,
The read timing generation circuit 7 outputs the original signal at time t (K).
The timing T at which the video signal of time satisfies the formula (1)
Read with (K).

[0020]

[Equation 1]

As shown in FIG. 16B, the deflection waveform generating circuit 6 outputs deflection so that the arbitrary two points on the same horizontal line on the display screen, point A and point B, have the same horizontal spot diameter during scanning. Is supplied to the deflection yoke 2. Here, a method of determining the deflection output waveform will be described. On the display screen, the stationary spot diameter at point A is φA, the read timing is T (A), T
Assuming that the read timing next to (A) is T (A + 1), the spot diameter ΦA at the time of scanning at point A is expressed by equation (2).

[0022]

[Equation 2]

When the stationary spot diameter at the point B on the display screen is φB, the read timing is T (B), and the read timing next to T (B) is T (B + 1), the scan at the point B is performed. The spot diameter ΦB is expressed by equation (3).

[0024]

[Equation 3]

In order for the horizontal spot diameters at the points A and B to be the same when scanning, the equation (4) must be satisfied. ΦA = ΦB (4) The scanning speed V is set so as to satisfy the expressions (1) and (4).
(T) and read timings T (1), T (2),
..., T (N) is determined. The scanning speed V (t) determined by the deflection waveform generation circuit 6 and the read timing generation circuit 7.
And read timings T (1), T (2), ..., T
The deflection waveform and the read timing are generated so as to satisfy (N).

Here, the generation of the deflection waveform will be described. The operation of the deflection waveform generation circuit that satisfies the determined scanning speed V (t) will be described with reference to FIGS. FIG. 7 is a circuit configuration diagram of the deflection waveform generation circuit 6. Q1 is an output transistor, D is a damper diode, C is a resonance capacitor, L is a horizontal deflection coil, E is a power supply, CS is an S-shaped correction capacitor, and FBT is a fly. It is a back transformer. Figure 8
Is a diagram showing the deflection current waveform, and the solid line shows
Deflection current waveform when scanning one horizontal scanning period on the display screen at the same speed, and the dotted line shows the deflection current that realizes the scanning speed V (t) determined by the equations (1) and (4). It is a waveform. Increasing the inclination of the waveform at the center of the screen can be realized by increasing the voltage of the power source E of the deflection waveform generating circuit 6. Delaying the rise of the waveform in the peripheral portion of the screen can be realized by adjusting the capacitance of the S-shaped correction capacitor CS of the deflection waveform generation circuit 6. That is, a desired deflection current waveform can be obtained by the voltage of the power source E and the capacity of the S-shaped correction capacitor CS.

Generation of read timing will be described with reference to FIG. In FIG. 9, the read timing generation circuit 7 includes a phase comparator 16, a low pass filter 17, a voltage controlled oscillator 18, a frequency divider 19 according to the number of digital samplings in the horizontal period, and a low pass filter 17. It is composed of an adder 20 for adding the output signal from the frequency correction signal and the frequency correction signal, and a frequency correction signal generator 21 for generating the frequency correction signal.

The phase comparator 16 and the low pass filter 17
The voltage-controlled oscillator 18 and the frequency divider 19 constitute a PLL synthesizer. That is, when there is no input from the frequency correction signal generator 21, if a signal of the horizontal deflection period is input to the phase comparator 16, the frequency multiplied according to the frequency division ratio previously input to the frequency divider 19 is obtained. It is output from the voltage controlled oscillator 19. For example, a signal having a reference frequency of a horizontal frequency of 33.75 kHz is output by the phase comparator 16
When the frequency division ratio 2200 is input to the frequency divider 19, the signal having a frequency of 33.75 kHz × 2200 = 74.25 MHz is output.

When the output frequency of the voltage controlled oscillator 18 is fo (t), the relationship with the control voltage Vco of the voltage controlled oscillator 18 is given by the following equation (6). fo (t) = Kv · Vco (t) (6) where Kv is a control function of the voltage controlled oscillator 18 and is a constant.

The control voltage when there is no output from the frequency correction signal generator 21 and a stable output is obtained is Vs,
When the output from the frequency correction signal generator 21 is Vc (t), the output frequency f when the frequency correction signal is input
o (t) is expressed by the following equation (7).

Fo (f) = Kv · {Vs + Vc (t)} (7) When a horizontal rate parabolic input is input to this Vc (t), the control voltage is high at the beginning and end of scanning, that is, the frequency is high. , The control voltage is low in the center of the scan,
That is, a low frequency signal is generated. This Vc
A desired read timing can be obtained by adjusting the amplitude or positive / negative of the parabola input of (t).

By adjusting the deflection waveform and the read timing of the video signal in this way, as shown in FIG. 16B, a horizontal spot diameter balanced in the central portion and the peripheral portion and deflection with good deflection linearity can be obtained. Will be realized. Further, at this time, since the horizontal spot diameters are the same in the central portion and the peripheral portion, the current densities with respect to the spots are also equal, and the luminance in the central portion and the peripheral portion approaches a well-balanced value.

FIG. 2 is a block diagram showing an image display device according to an embodiment of the second invention. In FIG. 2, 1 is CR
T, 2 is a deflection yoke, 3 is a video output circuit for providing a video output to the CRT 1, 4 is a D / A converter for providing an analog video signal to the video output circuit 3, and 5 is a digital video for the D / A converter 4. A line memory for giving a signal, 7 a read timing generating circuit for giving a read timing to the line memory 5, 8 an auxiliary deflecting device for velocity-modulating an electron beam,
An auxiliary deflection waveform generation circuit 9 outputs an auxiliary deflection waveform to the auxiliary deflection device 8.

The operation of the image display device of this embodiment having the above-described structure will be described below. FIG. 6 shows changes in the video signal before and after passing through the line memory 5. First, a digital video signal having the same sampling width as the signal 1 is input to the line memory 5 and temporarily stored therein.
The input signal 1 is given a read timing by the read timing generation circuit 7 and is output as a digital video signal whose projection period is changed by each data like the signal 2. Here, the read timing will be described. Let V0 be the scanning speed on the display screen when horizontally scanning at a constant speed on the display screen, and V (t) be the scanning speed at each time when the scanning speed is changed according to the scanning position in this embodiment. To do. Here, t is the elapsed time from the beginning of scanning. In order to obtain the same output at the same position on the display screen in the case of current speed scanning and the case of speed modulation scanning,
The read timing generation circuit 7 outputs the original signal at time t (K).
The video signal at that time is read at the timing T (K) that satisfies the equation (1) as in the first embodiment.

As shown in FIG. 16 (b), the auxiliary deflection waveform generating circuit 9 causes the arbitrary two points A and A on the same horizontal line on the display screen.
The auxiliary deflection output is supplied to the auxiliary deflecting device 8 so that the horizontal spot diameters at the time of scanning become equal at point B. Here, a method of determining the auxiliary deflection output waveform will be described. If the stationary spot diameter at point A is φ (A), the read timing is T (A), and the read timing next to T (A) is T (A + 1) on the display screen, the spot at the time of scanning at point A Diameter Φ
A is represented by the equation (2) as in the first embodiment. Also, on the display screen, set the stationary spot diameter at point B to φ
B, the read timing is T (B), and the read timing next to T (B) is T (B + 1), the spot diameter ΦB at the time of scanning at the point B is the same as in the first embodiment expressed by equation (3).
Will be represented by. In order to make the horizontal spot diameters at the points A and B equal to each other at the time of scanning, it is necessary to satisfy the equation (4) as in the first embodiment.

To satisfy the equations (1) and (4),
Scanning speed V (t) and read timings T (1), T
(2), ..., T (N) are determined. The scanning speed V (t) determined by the auxiliary deflection waveform generation circuit 9 and the read timing generation circuit 7 and the read timing T (1), T
(2), ..., The auxiliary deflection waveform and the read timing are generated so as to satisfy T (N).

Here, the generation of the auxiliary deflection waveform will be described. FIG. 10A shows a scanning speed V0 at the time of horizontal uniform scanning.
And the scanning speed V (t) determined by the equations (1) and (4)
Indicates. In order to realize V (t) on the display screen, the auxiliary deflection waveform generation circuit 9 decelerates the beam in the peripheral portion and accelerates the beam in the central portion in accordance with the speed difference shown in FIG. 10 (b). The auxiliary deflection waveform is input to the auxiliary deflection device 8. This can be realized by inputting an auxiliary deflection current having a parabolic waveform as shown in FIG.

Generation of read timing will be described with reference to FIG. In FIG. 9, the read timing generation circuit 7 includes a phase comparator 16, a low pass filter 17, a voltage controlled oscillator 18, a frequency divider 19 according to the number of digital samplings in the horizontal period, and a low pass filter 17. It is composed of an adder 20 for adding the output signal from the frequency correction signal and the frequency correction signal, and a frequency correction signal generator 21 for generating the frequency correction signal.

The phase comparator 16 and the low pass filter 17
The voltage controlled oscillator 18 and the frequency divider 19 constitute a PLL synthesizer. That is, when there is no input from the frequency correction signal generator 21, the phase comparator 16
When a signal of the horizontal deflection period is input to, the voltage controlled oscillator 19 outputs a frequency multiplied according to the frequency division ratio previously input to the frequency divider 19. For example, a signal having a reference frequency of a horizontal frequency of 33.75 kHz is detected by the phase comparator 1
6 and the frequency division ratio 2200 is input to the frequency divider 19, a signal having a frequency of 33.75 kHz × 2200 = 74.25 MHz is output.

When the output frequency of the voltage controlled oscillator 18 is fo (t), the relationship with the control voltage Vco of the voltage controlled oscillator 18 is given by the equation (6) as in the first embodiment. However, Kv is a control function of the voltage controlled oscillator 18 and is a constant.

When there is no output from the frequency correction signal generator 21 and a stable output is obtained, the control voltage is Vs,
When the output from the frequency correction signal generator 21 is Vc (t), the output frequency f when the frequency correction signal is input
o (t) is expressed by equation (7) as in the first embodiment.

When a horizontal-rate parabolic input is applied to Vc (t), the control voltage is high at the beginning and the end of the scan, that is, the frequency is high, and the control voltage is low at the center of the scan, that is, the signal is low. Is generated. A desired read timing can be obtained by adjusting the amplitude or the positive / negative of the parabolic input of Vc (t).

By adjusting the auxiliary deflection waveform and the read timing of the video signal in this way, it is possible to achieve deflection with a horizontal spot diameter and deflection linearity that are well balanced in the central portion and the peripheral portion. Further, at this time, since the horizontal spot diameters are the same in the central portion and the peripheral portion, the current densities with respect to the spots are also equal, and the luminance in the central portion and the peripheral portion approaches a well-balanced value.

FIG. 3 is a block diagram showing an image display device according to an embodiment of the third invention. In FIG. 3, 1 is CR
T, 2 is a deflection yoke, 8 is an auxiliary deflection device for velocity-modulating an electron beam, 10 is an auxiliary deflection waveform amplifier circuit for amplifying an input signal according to a horizontal scanning position, 11 is a video signal, and an image contour is obtained. It is a differentiating circuit that generates a signal in the section. The operation of the image display device of this embodiment configured as described above will be described below.

First, the video signal is input to the differentiating circuit 11. The differentiating circuit 11 differentiates the video signal, and outputs a positive output when the signal suddenly increases and a negative output when the signal suddenly decreases. This is shown in FIG. When this output is applied to the auxiliary deflecting device 8 without passing through the auxiliary deflecting waveform amplifier circuit 10, the auxiliary deflecting device 8 accelerates the electron beam when a positive input is made, and when the negative input is made, Slow down the electron beam. That is, FIG.
As shown in FIG. 1 (b), the beam spot diameter is reduced by the auxiliary deflection as shown by the solid line to the dotted line. The auxiliary deflection waveform amplifying circuit 10 amplifies the output of the differentiating circuit 11 when scanning the peripheral portion of the screen and small when scanning the central portion of the screen. This state is shown in FIG. 12A is a video signal for generating spots in the central portion and the peripheral portion of one horizontal scanning period, and FIG. 12B is a video signal shown in FIG. 12 and FIG.
It is a figure which shows the output which the output of the differentiating circuit 11 shown by (b) is amplified by the auxiliary | assistant deflection waveform amplifier circuit 10, and is large in a peripheral part small. The output shown in FIG. 12C is given to the auxiliary deflecting device 8, and as a result, the horizontal reduction ratio of the spot is large in the peripheral portion of the screen, the reduction ratio is small in the central portion, and the spot diameters in the central portion and the peripheral portion of the screen are reduced. Approaching the same size. In this way, by performing velocity modulation of the electron beam according to the difference in spot diameter between the central portion and the peripheral portion, a horizontal spot diameter balanced between the central portion and the peripheral portion and deflection with good deflection linearity are realized. To be done.

FIG. 4 is a block diagram showing an image display device according to the fourth embodiment of the invention. In FIG. 4, 1 is CR
T, 2 is a deflection yoke, 3 is a video output circuit for providing a video output to the CRT 1, 4 is a D / A converter for providing an analog video signal to the video output circuit 3, and 5 is a digital video for the D / A converter 4. A line memory for giving a signal, 6 is a deflection yoke 2
, 7 is a read timing generation circuit for giving a read timing to the line memory 5, and 12 is a deflection waveform generation circuit for controlling the deflection waveform of the deflection waveform generation circuit 6 based on the brightness / contrast adjustment volume information of the video output circuit 3. A deflection waveform control circuit 13 is a read timing control circuit that controls the read timing of the read timing 7 based on the brightness / contrast adjustment volume information of the video output circuit 3.

The operation of the image display device of this embodiment having the above-described structure will be described below. First, information on the optimum scanning speed corresponding to the brightness / contrast adjustment volume of the video output circuit 3 is input to the deflection waveform control circuit 12. Further, control information corresponding to the brightness / contrast adjustment volume of the video output circuit 3 is input to the read timing control circuit 13.

The deflection waveform control circuit 12 includes a video output circuit 3
The deflection waveform generation circuit 6 shown in FIG. 7 is controlled based on the information of the brightness / contrast adjustment volume of. Here, generation of the deflection waveform will be described. Brightness of video output circuit 3
The scanning speed V (t) is determined from the contrast adjustment volume information and the information of the optimum scanning speed input in advance. The deflection waveform generation circuit 6 generates a deflection waveform that satisfies the determined scanning speed V (t). The operation of the deflection waveform generation circuit 6 will be described with reference to FIGS. FIG. 7 is a circuit configuration diagram of the deflection waveform generation circuit 6, where Q1 is an output transistor,
D is a damper diode, C is a resonance capacitor, L is a horizontal deflection coil, E is a power supply, CS is an S-shaped correction capacitor,
FBT is a flyback transformer. FIG. 8 is a diagram showing a deflection current waveform. A solid line shows a deflection current waveform when one horizontal scanning period is scanned on the display screen at the same speed, and a dotted line shows the first embodiment. Is a deflection current waveform that realizes the scanning speed V (t) determined by the equations (1) and (4). Increasing the inclination of the waveform at the center of the screen can be realized by increasing the voltage of the power source E of the deflection waveform generating circuit 6. Delaying the rise of the waveform in the peripheral portion of the screen can be realized by adjusting the capacitance of the S-shaped correction capacitor CS of the deflection waveform generation circuit 6. That is, a desired deflection current waveform can be obtained by the voltage of the power source E and the capacity of the S-shaped correction capacitor CS.

Further, the read timing control circuit 13
Controls the read timing generation circuit 7 by determining the read timing such that the horizontal spot diameter is balanced in the central portion and the peripheral portion based on the information of the brightness / contrast adjustment volume of the video output circuit 3. Here, the control of the read timing will be described with reference to FIG. In FIG. 9, the read timing generation circuit 7 is
A phase comparator 16, a low pass filter 17, a voltage controlled oscillator 18, a frequency divider 19 corresponding to the number of digital samplings in the horizontal period, an output signal from the low pass filter 17 and a frequency correction signal are added. It comprises an adder 20 and a frequency correction signal generator 21 for generating a frequency correction signal.

The phase comparator 16 and the low pass filter 17
The voltage controlled oscillator 18 and the frequency divider 19 constitute a PLL synthesizer. That is, when there is no input from the frequency correction signal generator 21, the phase comparator 16
When a signal of the horizontal deflection period is input to, the voltage controlled oscillator 19 outputs a frequency multiplied according to the frequency division ratio previously input to the frequency divider 19. For example, a signal having a reference frequency of a horizontal frequency of 33.75 kHz is detected by the phase comparator 1
6 and the frequency division ratio 2200 is input to the frequency divider 19, a signal having a frequency of 33.75 kHz × 2200 = 74.25 MHz is output.

When the output frequency of the voltage controlled oscillator 18 is fo (t), the relationship with the control voltage Vco of the voltage controlled oscillator 18 is given by the equation (6) as in the first embodiment. However, Kv is a control function of the voltage controlled oscillator 18 and is a constant.

The control voltage when there is no output from the frequency correction signal generator 21 and a stable output is obtained is Vs,
When the output from the frequency correction signal generator 21 is Vc (t), the output frequency f when the frequency correction signal is input
o (t) is expressed by equation (7) as in the first embodiment.

When a horizontal-rate parabolic input is applied to this Vc (t), the control voltage is high at the beginning and end of the scan, that is, the frequency is high, and the control voltage is low at the center of the scan, that is, the signal is low. Is generated. A desired read timing can be obtained by controlling the amplitude or positive / negative of the parabolic input of Vc (t) by the read timing control circuit 13 based on the brightness / contrast information of the video output circuit 3. In this way, even if the horizontal spot diameter balance between the central portion and the peripheral portion is deteriorated due to the change in the brightness of the display screen, the deflection waveform generating circuit 6 and the read timing 7 can be controlled to make accurate correction. It is possible.

FIG. 5 is a block diagram showing an image display device according to an embodiment of the fifth invention. In FIG. 5, 1 is CR
T, 2 is a deflection yoke, 3 is a video output circuit for providing a video output to the CRT 1, 4 is a D / A converter for providing an analog video signal to the video output circuit 3, and 5 is a digital video for the D / A converter 4. A line memory for giving a signal, 6 is a deflection yoke 2
A deflection waveform generation circuit for giving a deflection output to the line memory, a read timing generation circuit for giving a read timing to the line memory 5, a photoelectric conversion element 14 provided at a predetermined position of the CRT image display device, and a photoelectric conversion element 14 for an output A spot diameter detection circuit for obtaining a horizontal spot diameter based on the brightness distribution on the display screen
5, a deflection waveform control circuit for controlling the deflection waveform of the deflection waveform generation circuit 6 based on the horizontal spot diameter information of 5, and a read timing control 13 for controlling the read timing of the read timing 7 based on the horizontal spot diameter information of the spot diameter detection circuit 15. Circuit.

The operation of the image display device of this embodiment having the above-described structure will be described below. First, C
The test signal is displayed on the display screen of RT1. As the test signal, one that can measure the horizontal spot diameter during horizontal scanning, such as a crosshatch signal, is used. Photoelectric conversion element 1
Reference numeral 4 captures the brightness distribution information of at least two spots on the same horizontal line on the display screen, and outputs the brightness distribution information and the screen position information to the spot diameter detection circuit 15. The spot diameter detection circuit 15 detects the horizontal stationary spot diameter based on the output of the photoelectric conversion element 14 from the horizontal spot diameter at the time of scanning based on the luminance distribution and the scanning distance based on the screen display position.

Optimal scanning speed information corresponding to the screen position and spot diameter is input to the deflection waveform control circuit 12 in advance. In addition, control information corresponding to the screen position and the spot diameter is input to the read timing control circuit 13 in advance.

The deflection waveform control circuit 12 controls the deflection waveform generation circuit 6 shown in FIG. 7 based on the screen position and the spot diameter information from the spot diameter detection circuit 15. Here, generation of the deflection waveform will be described. Spot diameter detection circuit 15
The scanning speed V (t) is determined from the information on the screen position and the spot diameter and the information on the optimum scanning speed input in advance. The deflection waveform generation circuit 6 generates a deflection waveform that satisfies the determined scanning speed V (t). The operation of the deflection waveform generation circuit 6 will be described with reference to FIGS. FIG. 7 is a circuit configuration diagram of the deflection waveform generation circuit 6, where Q1 is an output transistor, D is a damper diode, C is a resonance capacitor, and L
Is a horizontal deflection coil, E is a power supply, CS is an S-shaped correction capacitor, and FBT is a flyback transformer. FIG. 8 is a diagram showing a deflection current waveform. A solid line shows a deflection current waveform when one horizontal scanning period is scanned on the display screen at the same speed, and a dotted line shows the first embodiment. Is a deflection current waveform that realizes the scanning speed V (t) determined by the equations (1) and (4). Increasing the inclination of the waveform at the center of the screen can be realized by increasing the voltage of the power source E of the deflection waveform generating circuit 6. Delaying the rise of the waveform in the peripheral portion of the screen can be realized by adjusting the capacitance of the S-shaped correction capacitor CS of the deflection waveform generation circuit 6. That is,
A desired deflection current waveform can be obtained by the voltage of the power source E and the capacity of the S-shaped correction capacitor CS.

Further, the read timing control circuit 13
Controls the read timing generation circuit 7 by determining the read timing such that the horizontal spot diameter is balanced in the central portion and the peripheral portion based on the information on the screen position and the spot diameter from the spot diameter detection circuit 15. Here, the control of the read timing will be described with reference to FIG. In FIG. 9, the read timing generation circuit 7 is
A phase comparator 16, a low pass filter 17, a voltage controlled oscillator 18, a frequency divider 19 corresponding to the number of digital samplings in the horizontal period, an output signal from the low pass filter 17 and a frequency correction signal are added. It comprises an adder 20 and a frequency correction signal generator 21 for generating a frequency correction signal.

The phase comparator 16 and the low pass filter 17
The voltage controlled oscillator 18 and the frequency divider 19 constitute a PLL synthesizer. That is, when there is no input from the frequency correction signal generator 21, the phase comparator 16
When a signal of the horizontal deflection period is input to, the voltage controlled oscillator 19 outputs a frequency multiplied according to the frequency division ratio previously input to the frequency divider 19. For example, a signal having a reference frequency of a horizontal frequency of 33.75 kHz is detected by the phase comparator 1
6 and the frequency division ratio 2200 is input to the frequency divider 19, a signal having a frequency of 33.75 kHz × 2200 = 74.25 MHz is output.

When the output frequency of the voltage controlled oscillator 18 is fo (t), the relationship with the control voltage Vco of the voltage controlled oscillator 18 is given by the equation (6) as in the first embodiment. However, Kv is a control function of the voltage controlled oscillator 18 and is a constant.

The control voltage when there is no output from the frequency correction signal generator 21 and a stable output is obtained is Vs,
When the output from the frequency correction signal generator 21 is Vc (t), the output frequency f when the frequency correction signal is input
o (t) is expressed by equation (7) as in the first embodiment.

When a horizontal rate parabolic input is applied to this Vc (t), a control voltage is high at the beginning and the end of scanning, that is, the frequency is high, and a control voltage is low at the center of the scanning, that is, a signal having a low frequency. Is generated. A desired read timing can be obtained by the read timing control circuit 13 controlling the amplitude or positive / negative of the parabolic input of Vc (t) based on the screen position of the spot diameter detection circuit 15 and the spot diameter information. In this way, even if the balance of the horizontal spot diameters in the central portion and the peripheral portion is deteriorated due to the aging of the CRT 1, it is possible to perform accurate correction by controlling the deflection waveform generation circuit 6 and the read timing generation circuit 7. It is possible.

Although the output of the frequency correction signal generator 21 is described as a parabolic wave, it goes without saying that a waveform including other components such as a fourth power component may be generated. Also, the third
Although the embodiment has been described by using the scanning velocity modulation, the contour correction of the video signal can be realized by weakening the central portion and strengthening the peripheral portion.

[0064]

As described above, according to the first aspect of the present invention, the scanning speed on the display screen and the read-out timing of the video signal are adjusted so that the horizontal spot diameters at the central portion and the peripheral portion become closer. As a result, even if the CRT display screen is close to a flat surface, balanced horizontal resolution and brightness can be realized in the central portion and the peripheral portion, and its practical effect is great.

According to the second aspect of the present invention, the velocity modulation waveform of the electron beam input to the auxiliary deflecting device and the read timing of the video signal are adjusted so that the horizontal spot diameters at the central portion and the peripheral portion are adjusted. By bringing them close to each other, even if the CRT display screen is close to a flat surface, it is possible to realize a horizontal resolution and brightness that are well balanced in the central portion and the peripheral portion, and the practical effect thereof is great.

Further, according to the third aspect of the present invention, the amount of velocity modulation of the electron beam generated at the rise and fall of the video signal is controlled according to the horizontal deflection amount, and the central portion and the peripheral portion are controlled. By approaching the horizontal spot diameter, C
Even if the RT display screen is close to a flat surface, a balanced horizontal resolution can be realized in the central portion and the peripheral portion, and its practical effect is great.

Further, according to the fourth aspect of the present invention, the deflection waveform control circuit controls the deflection waveform and the read timing control circuit controls the read timing in accordance with the luminance / contrast of the video signal. Even if there is a change in contrast, the horizontal spot diameters in the central part and the peripheral part are brought close to each other, so that even if the CRT display screen is close to a flat surface, the horizontal resolution is well balanced in the central part and the peripheral part.・ Brightness can be realized and its practical effect is great. According to the fifth aspect of the present invention, the photoelectric conversion element and the spot diameter detection circuit detect the spot diameter on the display screen, and the deflection waveform control circuit determines the deflection waveform according to the spot diameter and the read timing. By controlling the read timing by the control circuit, even when the CRT changes over time, the horizontal spot diameters at the central portion and the peripheral portion are made close to each other, so that even if the CRT display screen is close to a flat surface, A well-balanced horizontal resolution and brightness can be realized in the central part and the peripheral part, and its practical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image display device in an embodiment of the first invention of the present invention.

FIG. 2 is a configuration diagram of an image display device in an embodiment of the second invention of the present invention.

FIG. 3 is a configuration diagram of an image display device in an embodiment of the third invention of the present invention.

FIG. 4 is a configuration diagram of an image display device in a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of an image display device in an embodiment of the fifth invention of the present invention.

FIG. 6 is a diagram showing changes in a video signal before and after passing through a line memory according to an embodiment of the present invention.

FIG. 7 is a configuration diagram of a deflection waveform generation circuit according to an embodiment of the present invention.

FIG. 8 is a diagram showing a deflection waveform in the example of the present invention.

FIG. 9 is a configuration diagram of a read timing generation circuit according to an embodiment of the present invention.

FIG. 10 is a diagram showing the relationship between the scanning speed and the auxiliary deflection current in the embodiment of the second invention.

FIG. 11 is a diagram showing the action of the differentiating circuit and the change of the spot due to the auxiliary deflection in the embodiment of the third invention.

FIG. 12 is a diagram showing a process of generating a velocity modulation waveform in the embodiment of the third invention.

FIG. 13 is a configuration diagram of a horizontal deflection circuit of a conventional example.

FIG. 14 is a diagram showing a scanning state of a conventional example.

FIG. 15 is a diagram showing a signal waveform of a conventional example.

FIG. 16 is a diagram showing a difference between spots according to deflection angles in the conventional example and the present invention.

[Explanation of symbols]

 1 CRT 2 deflection yoke 3 image output circuit 4 D / A converter 5 line memory 6 deflection waveform generation circuit 7 read timing generation circuit 8 auxiliary deflection device 9 auxiliary deflection waveform generation circuit 10 auxiliary deflection waveform amplification circuit 11 differentiating circuit 12 deflection waveform Control circuit 13 Read timing control circuit 14 Photoelectric conversion element 15 Spot diameter detection circuit 21 Frequency correction signal generator BM Electron beam C Resonance capacitor CS S-shaped correction capacitor

Claims (5)

[Claims] 1. A video output circuit for providing a video output to a CRT, and a D for providing an analog video signal to the video output circuit.
A / A converter, a line memory for giving a digital video signal to the D / A converter, a deflection waveform generating circuit for giving a deflection output to a deflection yoke, and a read timing generating circuit for giving a read timing to the line memory. An image display device characterized by the above. 2. A video output circuit for giving a video output to a CRT, and a D for giving an analog video signal to the video output circuit.
/ A converter, a line memory for giving a digital video signal to the D / A converter, an auxiliary deflecting device for speed-modulating an electron beam according to a horizontal deflection amount, and an auxiliary deflecting waveform output to the auxiliary deflecting device. An image display device, comprising: an auxiliary deflection waveform generating circuit for performing the above; and a read timing generating circuit for giving a read timing to the line memory. 3. An auxiliary deflection device for velocity-modulating an electron beam, an auxiliary deflection waveform amplification circuit for outputting an auxiliary deflection waveform to the auxiliary deflection device, and a differentiation for inputting a differential waveform of a video signal to the auxiliary deflection waveform amplification circuit. An image display device comprising a circuit. 4. A video output circuit for giving a video output to a CRT, and a D for giving an analog video signal to the video output circuit.
/ A converter, a line memory for giving a digital video signal to the D / A converter, a deflection waveform generating circuit for giving a deflection output to a deflection yoke, and a read timing generating circuit for giving a read timing to the line memory, A deflection waveform control circuit that controls the output waveform of the deflection waveform generation circuit based on the brightness / contrast information from the video output circuit, and a read timing of the read timing generation circuit based on the brightness / contrast information from the video output circuit. An image display device comprising a read timing control circuit for controlling. 5. A video output circuit for giving a video output to a CRT, and a D for giving an analog video signal to the video output circuit.
/ A converter, a line memory for giving a digital video signal to the D / A converter, a deflection waveform generating circuit for giving a deflection output to a deflection yoke, and a read timing generating circuit for giving a read timing to the line memory, CR
A photoelectric conversion element provided at a predetermined position on the T display screen, a spot diameter detection circuit for detecting a horizontal spot diameter on the basis of brightness distribution information of spots on the display screen output by the photoelectric conversion element, and the spot diameter detection circuit. The deflection waveform control circuit for controlling the output waveform of the deflection waveform generation circuit based on the information of the horizontal spot diameter on the display screen output by the, and the information of the horizontal spot diameter on the display screen output by the spot diameter detection circuit. An image display device comprising a read timing control circuit for controlling the read timing of the read timing generation circuit based on the above.