JPH0733022U - Bias circuit for power amplifier - Google Patents

Abstract

(57) [Abstract] [Purpose] In the bias circuit of class AB power amplifier,
Provided is a bias circuit of a power amplifier which covers a delay of an appropriate bias current due to a large thermal time constant of an output transistor and can stably flow an appropriate bias current. According to the discrimination output of a discrimination circuit 19 for discriminating between a class A operation and a class B operation of a class AB power amplifier, a sample and hold circuit 20 outputs A of output transistors 1 and 2
The current of the output transistor is sampled during class operation and B
The control circuit 29 controls the bias circuit 8 of the output transistors 1 and 2 by a hold voltage that holds the voltage during class operation.
Control to optimize the bias current and stabilize it.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an improvement of a bias circuit suitable for a bias circuit of a class AB push-pull power amplifier.

[0002]

[Prior art]

 Conventionally, as a bias circuit of a push-pull power amplifier, as shown in FIG. 4, a complementary symmetrical NPN transistor 1 and a PNP transistor 2 are connected in parallel to a load (actually a speaker) 3 and are connected to the power supplies + B and -B. On the other hand, a bias circuit 8 consisting of resistors 4, 5 and 6 is applied to the bases of the output transistors 1 and 2 which are connected in series so as to be in series with each other through a constant current source 4.

That is, the resistors 5, 6 and 7 are connected in series to the other end of the constant current source 4 connected to the positive voltage source + B, and the other end of the resistor 7 connected in series is connected to the negative power source −B. , The bases of the output transistors 1 and 2 are connected between the resistors 5 and 6 as well as between the resistors 6 and 7, and a bleeder current I _B that is sufficiently larger than the base current is supplied to the output transistors 1 and 2 so that the resistor 6 is connected. the resistance value When R _6, the voltage across the not make as that Do and _{I B R 6 ≒ V BE1 +} V BE2.

Actually, as shown in FIG. 5, two diodes, for example, varistors 9 and 10 are connected in series between the bases of the two output transistors 1 and 2 and a variable resistor 11 for fine adjustment is connected in series. A bias circuit 8 for passing a class AB bias current. 5, the parts corresponding to those in FIG. 4 are denoted by the same reference numerals and duplicate description is omitted, but the diodes 9 and 10 and the variable resistor 11 are used for temperature compensation and voltage reduction compensation. The NPN transistor 12 is a transistor for excitation, the input signal In is supplied to the base, the collector is integrally connected to the variable resistor 11 of the bias circuit 8, and the emitter is connected to the negative voltage source -B. The resistors 13 and 14 connected between the emitters of the output transistors 1 and 2 use the diodes 9 and 10 in the bias circuit 8 so that the forward voltage drop V _{F of} these diodes and the base-emitter of the output transistors 1 and 2 are connected. It is an emitter resistor for absorbing the voltage difference between the voltages V _BE1 and V _BE2 and controlling the collector current during idling.

[0005]

[Problems to be solved by the device]

According to the bias circuit 8 of the power amplifier shown in FIG. 5 described above, when a large current flows through the output transistors 1 and 2 and the temperature rises, the bias currents of the output transistors 1 and 2 change. Therefore, the temperature rise of the output transistors 1 and 2 is detected by the temperature compensating diodes 9 and 10 (V _BE1 and V _BE2 of the transistors 1 and 2 have a negative temperature coefficient that becomes smaller as the temperature rises). Therefore, V _BE1 and V _BE2 are detected.) By correcting the change in the bias current of the output transistors 1 and 2, (V _F > V _BE1 or V _BE2 ), the bias current becomes constant and the operation is stabilized. I am trying.

However, in such a temperature compensation system, a radiator for heat radiation is attached to the output transistors 1 and 2, but the thermal time constant of this radiator is extremely large, from several minutes to several tens of minutes. Therefore, there is a delay in heat transfer time, and it takes a long time for the output transistors 1 and 2 to stabilize and to flow a predetermined bias current.

Further, although complementary symmetrical NPN and PNP transistors are used as the output transistors 1 and 2, it is difficult to perfectly match the temperature characteristics of the output transistors 1 and 2 with each other. There is also a problem that accurate temperature compensation becomes difficult due to the difference in temperature characteristics between 1 and 2.

Further, even if the output transistors 1 and 2 are thermally stabilized, if the output changes greatly, the bias current changes greatly due to the time delay due to the large thermal time constant described above, and the bias current is corrected. There was a problem that excess and deficiency occurred and a stabilized bias current could not be flown in response to an instantaneous output change.

The present invention is intended to provide a bias circuit for a power amplifier that solves the above problems, and its object is to detect the bias current by the bias current detection circuit of the output transistors 1 and 2. Then, the bias currents of the output transistors 1 and 2 are made constant at a high response speed, and an appropriate bias current is supplied to the output transistors 1 and 2, thereby stabilizing the power amplifier.

[0010]

[Means for Solving the Problems]

 As shown in FIG. 1, the bias circuit of the power amplifier according to the present invention includes output transistors 1 and 2 in a bias circuit 8 of a class AB power amplifier in which two output transistors 1 and 2 are push-pull connected. Detection circuit 15 that outputs a detection signal corresponding to the bias current flowing in each emitter of the, a discrimination circuit 19 that discriminates between the class A operation and the class B operation based on the detection signal from this detection circuit 15, and this discrimination circuit A sample-and-hold circuit 20 that outputs currents from the output transistors 1 and 2 during class A operation and holds during class B operation according to the identification output signal from 19 and the sample-and-hold output of the sample-and-hold circuit 20. A control circuit 29 for controlling the bias currents of the output transistors 1 and 2 which are push-pull connected by comparing the signal with a predetermined voltage. Those consisting comprises a.

[0011]

[Action]

 The bias circuit of the power amplifier of the present invention detects the bias current during class A operation and / or class B operation in the class AB push-pull power amplifier, and detects the detection current of the output transistors 1 and 2 during class A operation. Since it is sampled and held during class B operation, it is possible to obtain a bias circuit of a power amplifier that can be quickly controlled to a predetermined bias current without being affected by a large thermal time constant.

[0012]

【Example】

 Hereinafter, the bias circuit of the power amplifier of the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of a bias circuit of a class AB push-pull power amplifier, in which an NPN transistor 12 constitutes an excitation stage, and a base is an emitter connected to an input terminal to which an input signal In is supplied. Is connected to the negative power source -B, and the collector is connected to the base of the PNP type output transistor 2 and the connection point D to the emitter of the light receiving element 28 of the photocoupler 26 that constitutes the bias circuit 8.

The photocoupler 26 is composed of a phototransistor as a light emitting element 27 and a light receiving element 28. The photocoupler 26 electrically cuts off the light emitting element 27 side and the light receiving element 28 side and changes the internal impedance to function as the bias circuit 8. . The base of the phototransistor as the light receiving element 28 is reverse-biased so that a collector current proportional to the amount of light supplied from the light emitting element 27 is made to flow, and the collector is constructed in compensation symmetry with the PNP type output transistor 2. It is connected to a connection point C between the base of the NPN output transistor 1 and one end of the current source 4, and the other end of the current source 4 is connected to the positive power source + B.

The compensation-symmetrical push-pull NPN output transistor 1 and PNP output transistor 2 are connected in series with each other, their collectors are connected to a positive power supply + B and a negative power supply −B, and their emitters are connected in series. Connected via the emitter resistors 13 and 14 connected to the output terminal from which the output signal OUT is taken out from the connection point J between the emitter resistors 13 and 14, and the load 3 such as a speaker is connected between this output terminal and the ground. The output transistors 1 and 2 are connected in parallel to the load 3 in series with the positive and negative power supplies + B and -B to form a SEPP circuit for performing push-pull operation. The emitter resistors 13 and 14 form a bias current detection circuit 15, which will be described later.

The connection point A between the emitter of the output transistor 1 and the emitter resistor 13 and the connection point B between the emitter of the output transistor 2 and the emitter resistor 14 are the first and second comparators 16 each including a differential amplifier or the like. And 17 are connected to the non-inverting input terminal and the inverting input terminal, and the connection point J of the emitter resistors 13 and 14 is connected to the output terminal. The output signal OUT from the output terminal is connected to the first and second comparators 16 and 16. And 17 inverting and non-inverting input terminals. The outputs of the first and second comparators 16 and 17 are connected to the input terminals of the AND gate circuit 18 to discriminate whether the output transistors 1 and 2 are in class A operation or class B operation. A discrimination circuit 19 is formed.

The identification signal of the identification circuit 19 is supplied to the sample and hold circuit 20 to be sampled and held. The non-inverting and inverting input terminals of the differential amplifier 21 of the sample-and-hold circuit 20 are connected to points A and B.

As will be described later, the sample-and-hold circuit 20 can be easily configured by incorporating an analog switch and a holding capacitor between two buffer amplifiers. However, if the acquisition time is a little long, it may be one IC. It is commercially available.

The output of the sample hold circuit 20 is supplied to the non-inverting input terminal of the third comparator 23, which is a differential amplifier. The inverting input terminal has one end grounded and the other end connected to the reference voltage source 22 connected to the reference voltage terminal E.

The output terminal of the comparator 23 is connected to the anode of the light emitting diode which is the light emitting element 27 of the photocoupler 26 via the resistor 24, and the cathode of the light emitting diode is grounded. A capacitor 25 is connected between the connection point of the resistor 24 and the anode of the light emitting diode 27 and the ground. The resistor 24 and the capacitor 25 form an integrating circuit 30.

The operation of the bias circuit 8 of the power amplifier in the above configuration will be described below. Initially, the bias currents (idling currents) of the output transistors 1 and 2 are such that the class AB operation is performed. Generally, in class AB amplification, the idling current is biased so as to flow only half or less of the maximum output current, but the collector loss when there is no signal is such that the maximum value of the output current Ipeak is Ipeak ≤ Iid ‥‥‥‥‥‥‥‥ (1) If Ipeak ≧ Iid ‥‥‥‥‥‥‥‥ (2), if the formula (1) operates in class A, and in formula (2) the idling current is 1/10 or less of class A, It is considered to be the same as the loss of class B operation.

That is, both output transistors 1 and 2 are in the “on” state during class A operation, and either one of the output transistors 1 or 2 is in the “off” state during class B operation.

The idling current as described above, that is, the bias current flows through the emitter resistors 13 and 14, and a voltage drop corresponding to the bias current occurs between both ends A and J of the emitter resistor 13 and both ends J and B of the emitter resistor 14. Then, the emitter resistors 13 and 14 form a bias current detection circuit 15 that detects a current according to the emitter bias current of the output transistors 1 and 2. The bias current detection circuit 15 can easily take out a detection signal corresponding to the bias current by using a differential amplifier or the like when there is no signal that only supplies the bias current. For example, the bias current I of the output transistors 1 and 2 can be extracted. _{When the} AC output signal is superimposed on ₁ and I ₂ , detection becomes difficult.

Then, the voltage drop corresponding to the bias currents I ₁ and I _{2 between the first} and _second drops of AJ and JB between the respective ends of the emitter resistors 13 and 14 constituting the bias current detection circuit 15 is made. It is supplied to the second comparators 16 and 17. The first and second comparators 16 and 17 have emitter resistors 13 and 14 because both output transistors 1 and 2 are "on" when the class AB power amplifier output transistors 1 and 2 are operating in class A. The voltage between both ends is supplied to the first and second comparators 16 and 17, and the voltage between both ends is compared.

On the other hand, when the class B operation is being performed, one of the output transistors 1 and 2 is “off”, so that either one of the first and second comparators 16 or 17 has an emitter resistor 13 or The voltage across 14 is supplied.

Now, assuming that the output current supplied to the speaker of the load 3 is on the vertical axis and the horizontal axis is the time axis t, and the output current is considered to have a waveform as shown in FIG. 2A, the bias of the output transistors 1 and 2 is biased. The currents I ₁ and I ₂ have waveforms as shown in FIG. 2B. The output waveform at the point F of the first operational amplifier 16 at the time of class A operation when the bias currents I ₁ and I ₂ having such timing waveforms flow over one cycle of the output current as shown in FIG. 2C. H pulse is output, and the output waveform of point G of the second comparator 17 outputs L pulse in the positive half cycle as shown in FIG. 2D.

If the outputs of the first and second comparators 16 and 17 are supplied to the AND gate circuit 18, as shown in FIGS. 2C and 2D, the output of the AND gate circuit 18 is output to the output of the AND gate circuit 18 only during the H pulse. Similarly, the H pulse is output. That is, when the output transistors 1 and 2 are performing class A operation, the H pulse is detected by the first and second comparators 16 and 17 as well as the AND gate circuit 18, and the H pulse is detected by the sample and hold circuit 20 described later. Supplied. That is, the first and second comparators 16 and 17 and the AND gate circuit 18 constitute the discrimination circuit 19 capable of discriminating whether the output transistors 1 and 2 are performing class A operation or class B operation. Will be done.

The H pulse from the AND gate circuit 18 is given to the sample and hold circuit (hereinafter referred to as S & H circuit) 20 as a sample pulse. FIG. 3A shows a principle configuration of the S & H circuit 20. As the differential amplifier 21, a buffer amplifier 21a and an FET input operational amplifier 21b having an infinite input impedance are used, and a switching means 30 is provided between the amplifiers 21a and 21b. The holding capacitor 31 is interposed, and the switching means 30 is turned “on” and “off” by the H pulse, that is, the sample pulse from the AND gate circuit 18, and the voltage across the emitter resistors 13 and 14 A and B is held by the holding capacitor 31. It holds during class B operation and supplies the hold voltage at the output end of the operational amplifier 21b to the third comparator 23 of the control circuit 29. FIG. 3B shows a circuit of the S & H circuit (LF398H) 20 composed of one IC described above.

That is, by using the S & H circuit 20 as described above, it is possible to sample during class A operation and hold during class B operation as shown in FIG. 2E. And this held voltage corresponds to the bias current.

Next, the third comparator 23 will be described. The sample-hold voltage is supplied to the non-inverting input terminal of the third comparator 23, and the inverting input terminal is supplied with the reference voltage level supplied from the reference voltage source 22 at the terminal E. And the output voltage of the sample S & H circuit 20 are compared.

If the hold signal voltage of the S & H circuit is higher than the reference voltage level of the third comparator 23, an H level signal is output, and if the hold signal voltage is low, an L level signal is output. This comparison output signal is integrated by an integrating circuit 30 composed of a resistor 24 and a capacitor 25, and also drives a light emitting element 27 of the photocoupler 26 to emit light. The third comparator 23, the integrating circuit 30, and the light emitting element 27 of the photocoupler 26 are included in the control circuit 29. The light emission of the light emitting element 27 of the photo coupler 26 changes the impedance of the light receiving element 28, and the voltage drop between C and D of the bias circuit 8 constituted by the current source 4 and the light receiving element 28 in the photo coupler 26 changes. As a result, the bias currents of the output transistors 1 and 2 are controlled.

That is, when the outputs of the output transistors 1 and 2 increase and the temperature rises, the bias current also increases, but the hold signal of the S & H circuit 20 also increases. Here, in this example, the discrimination circuit 19 discriminates whether the class A operation is the class B operation, controls the S & H circuit 20 to be sampled during the class A operation, and held during the class B operation. When the hold voltage of the S & H circuit 20 increases and the hold voltage exceeds the reference level, the H level is output, and the control circuit 29 reduces the impedance of the bias circuit 8 to reduce the voltage drop between C and D. Reduce the bias current.

Conversely, when the bias currents of the output transistors 1 and 2 decrease, the bias current flowing through the output transistors 1 and 2 is increased by the operation opposite to the above description. In this example, the reference voltage level of the reference voltage source 22 is selected to operate in class AB. However, if this reference voltage level is operated in class A or class B, it is possible to set the operating states of various classes. You can do it.

Although the discrimination circuit 19 detects the state in which the output transistors 1 and 2 are in the class A operation in the above-described embodiment, for example, the state in which the output transistors 1 and 2 are in the class B operation may be detected.

As described above, the present invention directly detects the variation in bias current of the class AB power amplification output transistors 1 and 2, and the detected voltage is sampled by the S & H circuit 20 during class A operation to class B. Since it is held during operation, it is possible to obtain a bias circuit for a power amplifier that can quickly stabilize the bias current.

[0035]

[Effect of device]

 According to the bias circuit of the power amplifier of the present invention, the bias current of the output transistor is stabilized at a fast response speed even in the class AB operation in which the input signal is supplied, and the delay of heat transfer time and the temperature characteristic of the output transistor are suppressed. Even if there is a difference, it is possible to obtain a device that can stably pass the optimum bias current.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a bias circuit of a power amplifier showing an embodiment of the present invention.

FIG. 2 is a waveform diagram of the bias circuit of the power amplifier of the present invention.

FIG. 3 is a block diagram of a sample-and-hold circuit used in the bias circuit of the voltage amplifier of the present invention.

FIG. 4 is an explanatory diagram of a bias circuit of a conventional power amplifier.

FIG. 5 is an actual circuit diagram of a bias circuit of a conventional power amplifier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 NPN type output transistor 2 PNP type output transistor 8 Bias circuit 15 Bias current detection circuit 19 Identification circuit 20 Sample and hold circuit 29 Control circuit 30 Integration circuit

Claims (2)

[Scope of utility model registration request] 1. A bias circuit of a class AB power amplifier in which two output transistors are push-pull connected, and a detection circuit for outputting a detection signal according to a bias current flowing through each emitter of the output transistor; A discrimination circuit for discriminating between the class A operation and the class B operation based on the detection signal of A, and a discrimination output signal from the discrimination circuit for sampling the output transistor current during the class A operation and holding it during the class B operation And a hold circuit and a control circuit for comparing the sample and hold output signal of the sample and hold circuit with a predetermined voltage to control the bias current of the push-pull output transistor. Bias circuit of amplifier. 2. The bias circuit for a power amplifier according to claim 1, wherein the identification circuit is composed of a comparator and an AND gate circuit.