JPH07334376A - Microprocessor and multitask management method - Google Patents

Abstract

(57) [Summary] [Purpose] To provide a technology that can easily check whether a problem due to stack operation occurs during program development. [Structure] The value stored in the SP register 9, that is, the current value of the stack pointer is sent to the SP via the signal line 19.
The value stored in the P register 15 is given to the SP comparison circuit 17 via the signal line 20. In the SP comparison circuit 17, the value stored in the SP register 9 is SPP.
If the value is smaller than the value stored in the register 15, the signal line 21 is set to "H", otherwise, the signal line 2 is set.
Set 1 to "L". Signal line 21 is "L" to "H"
Then, the value stored in the SP register 9 is given to the SPP register 15. [Effect] The minimum value of the stack pointer is always stored in the SPP register 15.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor capable of developing a program in consideration of the stack size and a multitask management method for the microprocessor.

[0002]

2. Description of the Related Art Generally, in a program executed by a microprocessor, a concept of "stack" for temporarily stacking data in a storage area is introduced. The stack is usually allocated in a predetermined area of the main storage device.

For example, when a subroutine is called, a return address indicating a place to return to after the execution of the subroutine is completed is stored in the stack. Alternatively, it is used to temporarily store the value of the internal register of the microprocessor when an interrupt occurs. It is also used as a variable storage area for temporary variables.

FIG. 8 is a conceptual diagram of addresses showing how the stack is allocated to the storage area 500. In FIG. 8, the upper side corresponds to the high address side of the storage area 500, and the lower side corresponds to the low address side. Normally, in the storage area 500, a program area 100 for storing instructions and data of programs and a stack area 200 to which a stack is allocated are set. The stack area 200 is an area sandwiched between the stack uppermost address 200u and the stack lowermost address 200d, and the uppermost address of the program area 100 here matches the stack lowermost address 200d.

When the data is stacked in the stack area 200, the data is sequentially stacked from the high address side to the low address side. In the figure, the outline arrow indicates the stacking direction.

Stacking new data on the top (low address) of the stack is called stack push.
The address at which the most recently pushed data is on the stack is called the stack pointer. In the figure, the stack pointer is indicated by reference sign SP. Each time the stack is pushed, the stack pointer SP indicates a small (low) address.

On the other hand, taking out the data from the top of the data stacked in the stack is called stack pop, and the stack pointer SP indicates a large (high) address each time the stack is popped.

It is necessary to secure at least the stack area 200 by the size of the stack used by the program to be executed (stack size).

The stack itself is a software concept, and in order to efficiently allocate and operate the stack, the microprocessor is provided with various instructions for stack operation. In addition, various hardware is also provided to implement these instructions for stack manipulation.

FIG. 9 is a block diagram showing the outline of the configuration of a microprocessor provided with such software and hardware. The instruction fetch unit 4 receives data via the data bus 3.
An instruction is read from a main memory device (not shown). The read instruction is analyzed by the instruction decoding unit 5, and the result is given to the instruction executing unit 6. The instruction execution unit 6 performs various processes based on this instruction. The above-mentioned "provided with various instructions for stack operation" means that even if the data itself corresponding to the instruction exists in the external main storage device, the function to decode and analyze it, Refers to having the function of executing instructions.

The instruction execution unit 6 controls the program counter 7, general-purpose register 8, stack pointer register (SP
Register 9 is controlled. The program counter 7 stores the address of the instruction to be executed. A stack pointer is stored in the SP register 9.

FIG. 10 is a flow chart showing the processing when a stack push instruction is executed. When the stack push instruction is executed, the value of the SP register 9 is decreased by the size of the data to be stacked (step S
11). Then, in the main storage device, the address (stack pointer) indicated by the updated value of the SP register 9
On the other hand, the data to be accumulated is stored (step S12). Of course, the microprocessor also has a stack pop instruction.

Further, examples of other instructions using the stack include a subroutine call instruction and a return subroutine instruction. The subroutine call instruction is an instruction to move the execution to the subroutine after stack-pushing the address of the "instruction to be executed next after the execution of the subroutine". The return subroutine instruction is
This is an instruction to return to the original address that called the subroutine by stack-popping the return address from the stack and moving execution to that address.

In addition, a plurality of general-purpose registers 8 are provided inside the microprocessor, and there are instructions for saving and restoring on the stack with one instruction. By providing the microprocessor with hardware and instructions for manipulating the stack in this way, stack manipulation becomes faster and easier.

Further, the microprocessor usually further includes an interrupt stack pointer register (SPI register) 1
It has 0. The SPI register 10 stores the stack pointer during execution of the interrupt routine. As described above, in recent microprocessors, the stack area to be used is automatically changed during the execution of the interrupt routine and when it is not, and the registers for storing the respective stack pointers are usually provided separately.

[0016]

However, if the size of the stack area 200 used by the program to be executed is erroneously estimated, the stack becomes the stack area 200.
There is a risk that the program will run out of control. In general, a stack overflow is a problem that often occurs because a program developer determines by calculation which size and size of the stack area 200 is set in which area of the main storage device.

FIG. 11 is a conceptual diagram of addresses showing how the stack overflows. The stack is stacked over the stack area 200, and the stack pointer SP has an address lower than the stack lowest address 200d. Therefore, the stack is stacked even in the area 100a on the high address side of the program area 100, and the data stored in advance in the area 100a is destroyed. In such a case, there is a problem that when the program is executed for the destroyed area 100a, the normal operation is no longer performed.

It is difficult to identify the cause of such a problem due to the setting error of the stack area. This is because the program does not run out of control immediately when the stack overflows, but a malfunction occurs only when the program is executed in the area 100a destroyed by the stack. At this time, the stack pointer has already been set to the stack area 20 that was initially set.
Since it has returned to 0, it is not possible to immediately determine whether the data in the area 100a has been destroyed by the stack.

On the other hand, if the stack is used incorrectly, there is a problem that a stack underflow occurs which causes a stack pop to a higher address side than the stack uppermost address 200u.

In order to prevent such problems caused by stack operations, it is necessary to accurately grasp the stack size of the stack used by the program. If the stack size can be accurately grasped, the stack area 200 to be secured can be minimized, so that the storage area of the main storage device can be saved.

However, although it is possible to calculate the stack size used by the program, the calculation may be troublesome when the program is already described in a high-level language. In addition, if the beginner programmers program without knowing the concept of stack, the calculation is impossible.

Therefore, a method of actually executing a program to check the stack size has been considered. Conventionally, the size required in the stack has been obtained by checking the value of the stack pointer at an appropriate timing. However, the stack pointer does not always take the peak value at that timing, and the problem of destruction of the program area 100 cannot be completely eliminated.

The present invention has been made to solve the above problems, and provides a microprocessor capable of accurately knowing the stack size used by a program, and problems caused by stack operation during program development. It is an object of the present invention to provide a technique capable of easily checking whether or not a problem occurs.

[0024]

[Means for Solving the Problems] Claim 1 of the present invention
Is a microprocessor that performs stack operations, and includes (a) a stack pointer register that stores the current stack pointer of the stack, (b) a stack pointer peak register, and (c) (c-1). A first input end to which the data stored in the stack pointer register is given, and (c-2) a second input end to which the data stored in the stack pointer peak register is given,
(C-3) The data given to the first input end is compared with the data given to the second input end, and the data stored in the stack pointer peak register is updated based on a predetermined magnitude relation. A comparator having an output terminal for
(D) A microprocessor including an instruction analysis unit that analyzes an instruction that stores a predetermined value in the stack pointer peak register.

According to claim 2 of the present invention,
2. The microprocessor according to claim 1, wherein the predetermined magnitude relationship is the stack pointer peak when the data given to the first input end is smaller than the data given to the second input end. It indicates that the value of the register is updated to the data given to the first input terminal.

According to claim 3 of the present invention,
2. The microprocessor according to claim 1, wherein the predetermined magnitude relationship is the stack pointer peak when the data given to the first input end is larger than the data given to the second input end. It indicates that the value of the register is updated to the data given to the first input terminal.

According to claim 4 of the present invention,
A microprocessor for controlling a plurality of stack modes, comprising: (a) a plurality of stack pointer registers provided corresponding to each of the plurality of stack modes, each storing a current stack pointer of each stack mode; (B) a stack pointer peak register provided corresponding to the plurality of stack pointer registers; and (c) provided corresponding to the plurality of stack pointer registers, each of which corresponds to (c-1). A first input end to which the data stored in the stack pointer register is given, (c-2) a second input end to which the corresponding data stored in the stack pointer peak register is given, and (c-3) the first input The data given to the end and the data given to the second input end are compared, and based on a predetermined magnitude relationship. There comprises a plurality of comparators and an output end for updating the data stored in said stack pointer peak register.

According to claim 5 of the present invention,
2. A multi-task management method for executing a plurality of tasks in a time-division manner in a microprocessor according to claim 1, wherein (e) one of the tasks is suspended, and the values of the stack pointer peak register and the stack pointer register are Saving as a context of one task; (f) starting and suspending the other task; (g) restoring the context of the one task; and (h) the one task. , Starting based on the context of the one task.

[0029]

In the microprocessor according to the first aspect of the present invention, the peak value of the stack pointer which changes when the program is executed is stored in the stack pointer peak register.

In the microprocessor according to the second aspect of the present invention, the minimum peak value of the stack pointer acquired during program execution is stored in the stack pointer peak register.

In the microprocessor according to claim 3 of the present invention, the maximum peak value of the stack pointer acquired during the execution of the program is stored in the stack pointer peak register.

In the microprocessor according to the fourth aspect of the present invention, the peak value of the stack pointer is stored in the stack pointer peak register for each of a plurality of stacks.

In the multitask management method according to claim 5 of the present invention, the value of the stack pointer register and the value of the stack pointer peak register are saved and restored as the context of the task when the task is suspended / resumed.

[0034]

【Example】

First Embodiment: FIG. 1 is a block diagram showing the structure of a microprocessor 11 according to a first embodiment of the present invention. The microprocessor 11 includes an instruction fetch unit 4, an instruction decode unit 5, an instruction execution unit 6, a program counter 7, a general-purpose register 8 and an SP register 9, like the conventional microprocessor 1 shown in FIG. . However, a stack pointer comparison circuit (SP comparison circuit) is additionally added.
17, a stack pointer peak register (SPP register) 15 is provided.

Like the SP register 9, the SPP register 15 can be set by the instruction executing section 6 via the signal line 14 based on a software instruction.

The value stored in the SP register 9, that is, the current value of the stack pointer is S through the signal line 19.
The values stored in the PP register 15 are given to the SP comparison circuits 17 via the signal lines 20, respectively. The SP comparison circuit 17 is composed of a commonly used size comparator, and S
The value stored in the P register 9 is changed to the SPP register 1
If it is smaller than the value stored in 5, the signal line 21
Is set to "H", otherwise, the signal line 21 is set to "L".
Set to.

The SPP register 15 is composed of a kind of latch circuit, and the value stored in the SP register 9 is given through the signal line 22. And the signal line 21
Goes from "L" to "H", the SPP register 1
The value stored in the SP register 9 is given to 5. That is, the SPP register 15 is updated using the current stack pointer value. By such operation, SP
The minimum value of the stack pointer is always stored in the P register 15.

FIG. 2 is a flow chart showing the procedure for executing the stack push instruction in this embodiment. Compared with the case of executing the conventional stack push instruction shown in FIG. 10, steps S11 and S1 are performed.
Steps S13 and S14 are interposed between the two. In step S13, it is determined whether or not the value stored in the SP register 9 is smaller than the value stored in the SPP register 15. If "Y", the value is stored in the SP register 9 in step S14. The existing value is given to the SPP register 15.

Since the microprocessor according to the first embodiment operates in this way, the minimum value of the address reached by the stack pointer is the SPP register 15 even if temporarily.
It is stored in. Therefore, when developing a program (especially when debugging), how much stack area was used,
It is possible to reliably know whether or not a stack overflow has occurred.

FIG. 3 is a flow chart showing how this is grasped. In step S15, the stack top address 200u is set in the SP register 9 and the SPP register 15, respectively, prior to execution of the program to be debugged.
Is given as an initial value. The reason why such an initial value is given is that the stack pointer always moves to the low address side when stack push is executed and stacks are stacked.

In step S16, the program to be debugged is executed. This execution moves the stack pointer variously, but the smallest address is the SPP.
It is stored in the register 15. Therefore, in step S17, by reading the value stored in the SPP register 15, it is possible to check where the stack pointer has moved, even temporarily during the program execution.

Of course, not only the stack top address 200u is set as the initial value in the SPP register 15, but any other value can be set as long as it is on the side of a higher address than the stack top address 200u. . In this case, the stack pointer value at that time is automatically copied to the SPP register 15.

On the other hand, the SP comparison circuit 17 sets the signal line 21 to "H" when the value stored in the SP register 9 is larger than the value stored in the SPP register 15, and otherwise. If the one that operates so as to set the signal line 21 to "L" is used, the maximum value of the stack pointer is always stored in the SPP register 15. Therefore, the stack underflow can be detected in the same manner as the above operation.

Of course, the SP comparison circuit 17 can be made to have a plurality of operation modes, and either stack overflow or stack underflow can be selected and detected as required.

The monitor program may be executed prior to the execution of the program to be debugged.
However, according to the present invention, the instruction for storing a predetermined value in the stack pointer peak register in advance can be executed. Therefore, even if the monitor program is executed in advance at the time of program development and some value is already stored in the stack pointer peak register. , The value of the stack pointer peak register can be newly initialized. Therefore, the detection of the area required by the stack will not be mistaken by the execution of the monitor program.

Second Embodiment: FIG. 4 is a block diagram showing the arrangement of a microprocessor 11a according to the second embodiment.

SP comparison circuits 17a and 17b are provided corresponding to the SP comparison circuit 17 in the first embodiment, and SPP registers 15a and 15b are provided corresponding to the SPP register 15. SP register 9, SP comparison circuit 1
7a and the SPP register 15a and the SP register 9, the SP comparison circuit 17b, and the SPP register 15b are connected by the SP register 9, the SP comparison circuit 17, and the SPP register 15 shown in the first embodiment. It is similar to the connection relationship.

The value stored in the SP register 9 is S
If the value is smaller than the value stored in the PP register 15, the SP comparison circuit 17a causes the SPP register 15a to store the value stored in the SP register 9.

On the other hand, when the value stored in the SP register 9 is larger than the value stored in the SPP register 15, the SP comparison circuit 17b causes the SPP register 15 to operate.
The value stored in the SP register 9 is stored by executing b.

Since the second embodiment is constructed and functions as described above, it is possible to check the maximum value and the minimum value of the stack pointer, and it is possible to detect both stack overflow and stack underflow.

Third Embodiment: FIG. 5 is a block diagram showing the configuration of the microprocessor 11b according to the second embodiment.

The microprocessor 11b is added to the microprocessor 11 shown in the first embodiment to add SPI.
Register 10, interrupt stack pointer comparison circuit (S
A PI comparator circuit 18 and an interrupt stack pointer peak register (SPIP register) 16 are provided.

The stack is used even when the interrupt routine is executed, and a microprocessor having a plurality of stack modes has a stack pointer register for each stack mode. Therefore, the third embodiment applies the present invention in such a case.

SPI register 10, SPI comparison circuit 1
8. The connection relationship of the SPIP register 16 is the same as the connection relationship of the SP register 9, the SP comparison circuit 17, and the SPP register 15 shown in the first embodiment. Therefore, the peak value which is the maximum value or the minimum value of the stack pointer can be checked also in the interrupt routine.

Fourth Embodiment: In a microprocessor, a multitask operation system (multitask OS) for executing a plurality of tasks may be operated. The multi-task OS is software that causes a plurality of programs (tasks) to operate at the same time.
Although "simultaneously", multiple tasks are performed in a time-sharing manner, as a typical microprocessor can only do one operation at a time.

FIG. 6 is a flow chart showing the procedure of such task switching. For simplicity, the case of switching two tasks will be described, but the same applies to the case of switching more tasks. For convenience, description will be given with reference to the conventional microprocessor 1 shown in FIG.

The first task is being executed and is interrupted (step S20). When switching tasks in a time-sharing manner, the value of the internal register of the microprocessor is saved in the main storage device as the context of the first task (information indicating the state of the task) that was executed immediately before (steps S21 and S22). , S23). Then, the execution of the second task is started (step S25). On this occasion,
The value of the internal register, which will be described later, is also restored for the second task (step S24).

After this, after the execution of the second task is completed, the same saving as in steps S21, S22, and S23 is performed for the second task (step S2).
6). Next, the value of the internal register saved in the main memory for the first task is restored (step S2
7, S28, S29), and the first task is continued again (step S30). The restoration in step S24 corresponds to steps S27, S28, and S29.

The data of the internal register that is saved and restored in this way corresponds to the context in each task, and even if the task is switched and interrupted or restarted, continuous processing can be performed for the same task. .

When the present invention is applied to a multitask OS, the stack pointer is also saved and restored as the context.

FIG. 7 is a flow chart showing the procedure when the present invention is applied to a multitasking OS. In the flowchart shown in FIG. 6, step S31 is added between step S22 and step S23, step S34 is added between step S27 and step S28, step S24 is added to step S32, and step S2 is added.
6 has been replaced by step S33.

In step S31, the value of the SPP register 15 for the first task is saved as one of the contexts, like the value of the program counter 7, the value of the general register 8 and the value of the SP register 9. Further, in step S34, the first task S
The value of the PP register 15 is restored as one of the contexts.

In step S32, the restoration related to the second task is performed.
It corresponds to S34, S28, and S29. In addition, in step S33, a save related to the second task is performed, which is performed in steps S21, S22, S31, S2.
It corresponds to 3.

As described above, in the fourth embodiment, the maximum value and the minimum value of the stack area can be obtained for each task even if the tasks are executed in a time division manner. Of course, even if they are discontinuous in time due to being interrupted / resumed, as long as the stack takes a maximum / minimum value even if it is the same task, that value will be SP until the end.
It is stored in the P register 15. Therefore, stack overflow and stack underflow can be easily detected for each task.

[0065]

In the microprocessor according to claim 1 of the present invention, since the peak value of the stack pointer is stored in the stack pointer peak register, the area used as a stack, even temporarily during the program, is used. The maximum size of can be detected. Therefore, it becomes easy to consider the stack size in setting the stack area when developing the program.

Moreover, since the instruction for storing a predetermined value in the stack pointer peak register in advance can be executed, the monitor program is executed in advance at the time of program development, and some value is already stored in the stack pointer peak register. Also, the value of the stack pointer peak register can be newly initialized. Therefore, the detection of the area required by the stack will not be mistaken by the execution of the monitor program.

In the microprocessor according to the second aspect of the present invention, it becomes easy to develop a program so that stack overflow does not occur.

In the microprocessor according to the third aspect of the present invention, it becomes easy to develop the program so that the stack underflow does not occur.

In the microprocessor according to the fourth aspect of the present invention, the area required by the stack can be detected for each of the plurality of stacks.

In the multitask management method according to claim 5 of the present invention, while executing multitask,
The peak value of the stack pointer can be detected.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a flowchart showing the operation of the first embodiment of the present invention.

FIG. 3 is a flowchart showing the operation of the first embodiment of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a flowchart showing the premise of the fourth embodiment of the present invention.

FIG. 7 is a flowchart showing the operation of the fourth embodiment of the present invention.

FIG. 8 is a conceptual diagram of an address showing a conventional technique.

FIG. 9 is a block diagram showing a conventional technique.

FIG. 10 is a flowchart showing a conventional technique.

FIG. 11 is a conceptual diagram of an address showing a problem of Jira technology.

[Explanation of symbols]

5 instruction decode section, 6 instruction execution section, 9 SP register, 10 SPI register, 15, 15a, 15b S
PP register, 16 SPIP register, 17, 17
a, 17b SP comparison circuit, 18 SPI comparison circuit.

Claims (5)

[Claims] 1. A microprocessor for performing stack operations, comprising: (a) a stack pointer register for storing a current stack pointer of a stack; (b) a stack pointer peak register; and (c) (c-1), A first input end to which the data stored in the stack pointer register is given; (c-2) a second input end to which the data stored in the stack pointer peak register is given; and (c-3) to the first input end. A comparator having an output end for comparing the given data with the data given to the second input end and updating the data stored in the stack pointer peak register based on a predetermined magnitude relationship; d) A microprocessor including an instruction analysis unit that analyzes an instruction for storing a predetermined value in the stack pointer peak register. Support. 2. The predetermined magnitude relation means that when the data given to the first input end is smaller than the data given to the second input end, the value of the stack pointer peak register is 2. The microprocessor according to claim 1, which indicates to update to the data given to the first input terminal. 3. The predetermined magnitude relationship means that when the data given to the first input end is larger than the data given to the second input end, the value of the stack pointer peak register is 2. The microprocessor according to claim 1, which indicates to update to the data given to the first input terminal. 4. A microprocessor for controlling a plurality of stack modes, comprising: (a) a plurality of microprocessors provided corresponding to each of the plurality of stack modes, each storing a current stack pointer of each stack mode. A stack pointer register, (b) a stack pointer peak register provided corresponding to the plurality of stack pointer registers, and (c) provided corresponding to the plurality of stack pointer registers, each of which is (c- 1) The first to which the data stored in the corresponding stack pointer register is given
An input end, (c-2) a second input end to which the data stored in the corresponding stack pointer peak register is given, and (c-3) data given to the first input end,
A plurality of comparators each having an output end for comparing the data supplied to the second input end and updating the data stored in the stack pointer peak register based on a predetermined magnitude relation. 5. A multi-task management method for causing a plurality of tasks to be executed in a time-division manner in a microprocessor according to claim 1, wherein (e) one of the tasks is suspended, the stack pointer peak register and the stack pointer. Saving the value of the register as the context of the one task; (f) starting and suspending the other task; (g) restoring the context of the one task; (h) Starting the one task based on the context of the one task.