JPH07334657A - Picture processing circuit - Google Patents

Abstract

PURPOSE:To provide a small-sized and low-cost picture processing circuit which performs emphasis of the outline or the like as well as removal of the background noise. CONSTITUTION:This picture processing circuit is operated in the outline emphasis mode as well as the background noise removal mode and is provided with a picture signal storage circuit 9 which outputs a stored picture signal at a timing after the storage timing in the outline emphasis mode and outputs the picture signal of the state of only the background noise in the background noise removal mode, a look up table circuit 10 which subjects the original picture signal and the output signal of the picture signal storage circuit 9 to the operation including subtraction in the outline emphasis mode and subjects the original picture signal ana the output signal of the picture signal storage circuit 9 to the operation including division in the background noise removal mode, and a mode switching circuit 13 for switching between the outline emphasis mode and the background noise removal mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit used when measuring a biological sample or the like using a microscope.

[0002]

2. Description of the Related Art When measuring the shape of a biological sample using a microscope, most of the sample is composed of water and there is no difference in the light transmittance, which makes it difficult to obtain contrast and observes it with the naked eye. May not be easy. Therefore, it is necessary to emphasize the contour and the like.

On the other hand, in order to obtain a good observation image, uneven illumination, optical system, shading (shading) of the camera,
That is, it is necessary to correct the background noise.

Conventionally, in order to meet these needs, in order to emphasize the contour and the like, for example, a signal difference between pixels described in Japanese Patent Laid-Open No. 5-159048 is arithmetically processed, and its output and a video signal are processed. Was done by the method of synthesizing.

Further, in order to correct the unevenness of illumination, for example, the method of subtracting noise from the original image signal described in JP-A-4-6962 has been used.

[0006]

In the prior art, therefore, separate circuits had to be provided in order to meet the above two needs. Therefore, the number of parts has increased, leading to a larger circuit and higher cost.

Therefore, an object of the present invention is to provide a small-sized and low-cost image processing circuit which can both enhance a contour and remove background noise by sharing circuit components. To do.

[0008]

In order to achieve the above object, the invention according to claim 1 provides an edge enhancement mode for enhancing the edge of an object to be observed, and a background noise from an image including the object to be observed. Is an image processing circuit that operates in a background noise removal mode for removing the
An image signal storage circuit having a capacity for storing image signals for frames, and outputs the stored image signal at a timing later than the stored timing in the edge enhancement mode, and in the background noise removal mode. , An image signal storage circuit that stores an image signal in a state of only background noise that does not include an observation object, and outputs this image signal at a timing corresponding to an original image signal in a state in which the observation object exists, and an original image An image in which the contour of the observation target is emphasized by inputting the signal and the output signal of the image signal storage circuit and performing an operation including subtraction on the original image signal and the output signal of the image signal storage circuit in the contour enhancement mode. In addition to outputting the signal, in the background noise removal mode, the original image signal and the image signal storage A contour table enhancement mode by issuing a command to a look-up table circuit that outputs an image signal from which background noise is removed by performing an operation including division on the output signal of And a mode switching circuit for switching the background noise removal mode.

[0009]

According to the present invention, the setting of the image signal storage circuit and the look-up table circuit is switched depending on whether the mode is the edge enhancement mode or the background noise removal mode, and the object to be observed has a common circuit configuration. Enables both edge enhancement and background noise removal. Therefore, the number of parts is reduced, and the image processing circuit can be downsized and the cost can be reduced.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Note that the same reference numerals are used for the same or corresponding parts in the drawings.

FIG. 1 is a block diagram showing the configuration of an image processing circuit constructed according to the present invention. In FIG.
An observation object (not shown) such as a biological sample is placed on the sample table 2 of the microscope 1. A video camera 3 is connected to the eyepiece of the microscope 1. The output signal Via of the video camera 3 is connected to the input terminal of the A / D converter 4, and the A / D converter 4 converts Via (analog signal) into a digital signal Vi. The output terminal of the A / D converter 4 is connected to the input terminal of the image processing circuit 5 of the present invention, and the digital signal Vi is input to the image processing circuit 5. Hereinafter, the digital signal Vi will be referred to as an original image signal. Further, the output terminal of the image processing circuit 5 is connected to the D / A converter 6, and the output signal Vo (digital signal) of the image processing circuit 5 is converted into an analog signal Voa and input to the video monitor 7. Then, the image of the biological sample or the like subjected to the contour enhancement processing can be observed by the video monitor 7.

Next, the image processing circuit 5 of the present invention will be described. FIG. 2 is a block diagram showing the configuration of the image processing circuit 5. In FIG. 2, the original image signal Vi, which is the output signal of the A / D converter 4, is input to the input terminal 8.
The input terminal 8 is connected to the image signal storage circuit 9, the look-up table circuit 10 and the periodic signal generation circuit 11, and the original image signal Vi is input to these circuits 9-11. The output terminal of the image signal storage circuit 9 is connected to another input terminal of the look-up table circuit 10, and the output signal Vs of the image signal storage circuit 9 is the look-up table circuit 10.
Entered in. Then, the lookup table circuit 10
The output signal Vo is output from the output terminal 12 and input to the D / A converter 6 (see FIG. 1). The synchronizing signal generation circuit 11 recognizes the horizontal synchronizing signal and the vertical synchronizing signal from the original image signal Vi, and resets the memory address according to the mode designated by the mode switching circuit 13 (the contour emphasis mode and the background noise removing mode described later). Signal (Rst), write enable signal (We
), Read enable signal (Re) and clock signal (Cl)
generate k). These generated signals are input to the image signal storage circuit 9 to control it. Further, a look-up table switching signal (Sel) is given from the mode switching circuit 13 to the look-up table circuit 10, and this signal selects one of a plurality of memory arrays existing in the look-up table circuit 10. It

FIG. 3 is a diagram showing an example of the image signal storage circuit 9, and the image signal storage circuit 9 comprises a sequential access memory 14. In the sequential access memory 14, the input signal Si from the input terminal 15 matches the original image signal Vi, and the signal So output to the output terminal 16 becomes an input signal to the look-up table circuit 10. Write enable signal W from input terminal 17
An input signal is written to the sequential access memory 14 when e is ON, and writing to the sequential access memory 14 is not performed when this signal is OFF. Read enable signal Re from input terminal 18 is ON
The contents are read from the sequential access memory 14 only in this state, and the reading is not performed when this signal is OFF. In synchronization with the pixel clock signal Clk input from the input terminal 19, the input signal Si is written and the storage data is output as the output signal Si. When the memory address reset signal Rst is applied from the input terminal 20 to the sequential access memory 14, the next writing and reading are performed from the head of the sequential access memory 14. Sequential access memory 14
Has a capacity equivalent to one frame of an image on the video camera 3 or the video monitor 7, the input signal Si is sequentially written only when the write permission signal We is ON, and the read permission signal Re is ON. Only in the order, data is sequentially read in the order in which the data was written.

FIG. 4 is a time chart explaining the operation of the synchronizing signal generating circuit 11. Sync signal generation circuit 1
The original image signal Vi input to 1 is a general video signal as shown in FIG. The falling portion 21 is a horizontal synchronizing signal and indicates the horizontal start of the scanning line. A portion in the range indicated by reference numeral 22 is a vertical synchronizing signal and indicates the start of the scanning line in the vertical direction. Although interlaced scanning is generally performed, interlaced scanning is not considered here for the sake of simplicity of description.

The memory address reset signal Rst shown in FIG. 4 is converted into the original image signal Vi by the synchronizing signal generating circuit 11.
It is generated at the timing of the vertical synchronization signal 22. Similarly, the write enable signal We and the read enable signal Re
Is generated at the timing of the horizontal synchronizing signal 21 of the original image signal Vi by the synchronizing signal generating circuit 11. The synchronization signal generation circuit 11 generates the write enable signal We and the read enable signal Re by shifting the timing.

It is assumed that the signal Si shown in FIG. 5 is input to the image signal storage circuit 9 thus constituted by the sequential access memory 14. As shown in FIG. 5, the input signal Si is a portion of the original image signal Vi other than the horizontal synchronizing signal and the vertical synchronizing signal, that is, the portion corresponding to the image data. Also, We, Re, So, Clk,
Rst is a signal similar to that shown in FIG.

The read permission signal Re is delayed from the write permission signal We, and the signal So is delayed from the signal Si by the delay time. Further, the write permission signal We is turned on only for one frame of the image, and then only the write permission signal We is turned on.
The image can be stored by holding the FF state. In this way, the image signal storage circuit 9 can be used as an image shift unit and an image storage unit.

Next, the operation of the look-up table circuit 10 will be described. FIG. 6 is a diagram showing a configuration example of the lookup table circuit 10. In this example, each of the two input terminals 30 and 32 has a 2-bit information amount. Further, four memory arrays 34 _{0 to} 34 ₃ are provided, and they can be switched and used.
A signal input to one of the input terminals 30 selects a row of the memory arrays 34 _{0 to} 34 ₃ via the row decoder 36. The signal input to the other input terminal 32 is used to select the columns of the memory arrays 34 _{0 to} 34 ₃ via the column decoder 38.

The look-up table switching signal input from the input terminal 40 is a 4-bit selectable 2-bit signal and selects each of the memory arrays 34 _{0 to} 34 ₃ via the memory plane decoder 42. . Then, of the memory arrays selected by the memory plane decoder 42, the row decoder 36 and the column decoder 38.
The content of one memory cell selected by is output from the output terminal 12 (see FIG. 2).

FIG. 7 shows a setting example of the memory arrays 34 _{0 to} 34 ₃ in which one input value (the value of the row decoder 36) is subtracted from the other input value (the value of the column decoder 38) and "3" is added. It is a thing. For example, when the input value of the input terminal 30 is “2” and the input value of the input terminal 32 is “3”, the value of the row decoder 36 is “2” and the value of the column decoder 38 is “3”. Become. Therefore, the first memory cell from the top and the third memory cell from the left in FIG. 7 are selected. A value of 2-3 + 3, that is, "2" is stored in this memory cell, and "2" is output from the output terminal 12.

In the case of this embodiment, two input terminals 30,
Since each of 32 has 2 bits, a memory array of 4 rows and 4 columns is used.
When each 2 has 8 bits, a memory array of 256 rows and 256 columns may be used.

Next, the operation of the image processing circuit configured as described above will be described. First, the operation in the contour emphasis mode will be described.

It is assumed that the original image signal Vi input to the input terminal 8 is as shown in FIG. 8 (b). That is,
It is assumed that the image of one frame by the original image signal Vi is as shown in FIG. 8 (b). The horizontal scanning signal at this time is shown in FIG.
a). In the edge enhancement mode, the image signal storage circuit 9 is set to be used as the above-mentioned image shift means. For example, it is set to shift one pixel in the horizontal direction. At this time, the original image signal Vi is a signal Vs horizontally shifted through the image signal storage circuit 9 (FIG. 8 (c)).
Refer to). If the look-up table circuit 10 is set to perform an operation of adding an offset value for eliminating a negative value after subtracting Vo from Vi,
The output Vo of the look-up table circuit 10 is shown in FIG.
As shown in. The image corresponding to this signal Vo is an image obtained by extracting the vertical contour of the image by the original image signal Vi, as shown in FIG. 8 (f).

Further, various contour enhancement can be performed by changing the setting of the look-up table circuit 10. For example, when the setting is such that a value obtained by subtracting Vs from Vi is multiplied by an arbitrary coefficient, for example, 1.5 or 0.5, and then Vi is added, an image in which the vertical contour of the original image is emphasized is output. It can be obtained from the terminal 12, and the degree of emphasis can be arbitrarily selected by changing the coefficient.

Next, the operation of the image processing circuit in the background noise removal mode will be described.

First, the image signal storage circuit 9 stores an image in which the observation object does not exist on the sample table 2 of the microscope 1. This image corresponds to uneven illumination, shading (shading) of the optical system and camera, and is background noise to be corrected. This background noise is caused by turning on the write permission signal We for one frame in the image signal storage circuit 9 and then holding the write permission signal We in the off state.
It can be stored in the image signal storage circuit 9 as image data for one frame of image.

Next, an image of the observation object placed on the sample table 2 of the microscope 1 is input as the original image signal Vi through the video camera 3 or the like. If the look-up table circuit 10 is set to divide the original image signal Vi by the background noise Vs, background noise such as uneven illumination can be removed from the image of the observation object.

The processing procedure in this case is shown below.

1) Prepare a sample to be observed on the sample table 2 of the microscope 1.

2) The image of the background noise including blur of the microscope 1 and uneven illumination is input terminal 8
Enter from.

3) The write enable signal We of the image signal storage circuit 9 is turned on for one frame to store the image due to background noise in the image signal storage circuit 9.

4) The look-up table circuit 10 is set to divide the original image signal Vi by the output Vs of the image signal storage circuit 9.

5) After focusing the microscope 1, the read permission signal Re of the image signal storage circuit 9 is continuously turned on.

6) An image signal with background noise corrected is output from the output terminal.

In this mode, although the original image signal Vi is set to be divided by the background noise Vs, the background noise Vs is changed from the original image signal Vi.
May be set to be subtracted.

Further, according to the configuration of FIG. 2, the original image signal V
Although i appears to be the output signal Vo after passing through the look-up table circuit 10, in reality, the original image signal Vi
The horizontal synchronizing signal, the vertical synchronizing signal, and the like among the signals included in (3) are output without passing through the look-up table circuit 10.

[0037]

As described above, according to the present invention, the settings of the image signal storage circuit and the look-up table circuit are switched according to whether the mode is the edge enhancement mode or the background noise removal mode, The common circuit configuration enables both the edge enhancement of the observation target and the background noise removal, and the same circuit configuration enhances the contours and removes the background noise. Thus, a low-cost image processing circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a system to which an image processing circuit configured according to the present invention is applied.

FIG. 2 is a block diagram showing an internal configuration of an image processing circuit.

FIG. 3 is a diagram showing an image signal storage circuit composed of a sequential access memory.

FIG. 4 is a time chart showing the operation of the synchronization signal generation circuit.

FIG. 5 is a time chart showing the operation of the image signal storage circuit.

FIG. 6 is a diagram showing a configuration of a lookup table circuit.

FIG. 7 is a diagram showing a setting example of a lookup table circuit.

FIG. 8 is a diagram showing a state where a vertical contour is emphasized in a contour emphasis mode.

[Explanation of symbols]

5 ... Image processing circuit, 9 ... Image signal storage circuit, 10 ... Look-up table circuit, 13 ... Mode switching circuit.

Claims (1)

[Claims] 1. An image processing circuit which operates in a contour enhancement mode for enhancing the contour of an observation target object and a background noise removal mode for removing background noise from an image including the observation target object, An image signal storage circuit having a capacity for receiving an original image signal including an observation object and storing an image signal for one frame, and in the contour enhancement mode, is delayed from the stored timing of the stored image signal. In addition to outputting at the same timing, in the background noise removal mode, the image signal in the state of only background noise not including the observation object is stored, and this image signal is the original image signal in the state in which the observation object is present. An image signal storage circuit for outputting at a timing corresponding to, and the original image signal and the image signal storage An image signal in which the contour of the observation object is emphasized by performing a calculation including subtraction on the original image signal and the output signal of the image signal storage circuit in the contour enhancement mode. A lookup table that outputs the image signal from which the background noise is removed by performing an operation including division on the original image signal and the output signal of the image signal storage circuit in the background noise removal mode An image processing circuit comprising: a circuit; and a mode switching circuit that switches the contour enhancement mode and the background noise removal mode by issuing a command to the image signal storage circuit and the lookup table circuit.