JPH07334986A - Memory control method - Google Patents

Abstract

(57) [Summary] [Object] To provide a memory control method capable of reducing the memory access overhead due to refresh. In a system having a memory composed of a memory controller and a plurality of memory modules 3a / 3b that need refreshing, for each memory module, a refresh counter 4 for monitoring a specified time for refreshing the module, and the refresh counter A flag 6a / 6b for storing the end of the operation is provided, and for example, the module 3
While a is performing access, it performs a refresh operation on another module 3b / 3c or the like whose refresh operation end flag is off, and turns on the refresh operation end flag 6b / 6c or the like when the operation is completed. When the refresh counter 4 finishes counting for a specified time, refresh is executed only for the module for which the refresh operation end flag is off, and the operation end flag is turned off to reduce the memory access overhead due to refresh. .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control method for a memory system including a memory device requiring refresh, and more particularly to a memory control method capable of efficiently refreshing the memory.

[0002]

2. Description of the Related Art Generally, a dynamic RAM constituting a memory used in a computer system needs to perform a refresh operation for rewriting the content within a fixed time. A conventional method of controlling a memory is, for example, as described in Japanese Patent Laid-Open No. 5-189963, when the memory is divided into two modules and one of the memory modules has a read or write access.
It has been proposed to reduce the memory access overhead (indirect processing) by forcibly refreshing the other memory module.

[0003]

The refresh operation of the memory control method according to the prior art described above is such that when a read or write access is made to a certain memory module, the memory access is always performed to refresh the other memory module. However, there is a problem in that the refresh operation is performed more than necessary and the power consumption is increased in the case of frequent occurrence.

Further, the conventional refresh operation is
By refreshing the memory module other than during memory access by writing and reading data,
Although it becomes possible to refresh more memory elements, if a memory module that could not be refreshed within the specified time occurs, a large number of other memory modules are used when the memory module is forcibly refreshed. Since the module does not operate at all, the operation rate of the memory becomes insufficient, and the memory access overhead (indirect processing) due to this refresh increases.

An object of the present invention is to eliminate the drawbacks of the prior art and to provide a memory control method for a memory system which can reduce the memory access overhead due to the refresh.

[0006]

In order to achieve the above object, the present invention provides a memory control method for writing and reading data to and from a plurality of memory modules that need to be refreshed. A refresh counter for monitoring time and a refresh operation end flag for storing the refresh status corresponding to the plurality of memory modules are provided, and when a certain memory module is reading or writing, the refresh operation and the other memory modules are performed. A memory module in which a refresh operation end flag is set, and when the refresh counter reaches a specified time, the memory module whose refresh operation end flag is off is forcibly refreshed and refreshing is not necessary. And permits the execution of the memory access.

[0007]

In the memory control method according to the above feature, before the refresh counter counts the specified time of the refresh cycle, the other memory module is refreshed while the access to the certain memory module is being executed, so that the refresh counter can perform the periodical operation. It is possible to reduce the frequency of performing the automatic refresh and reduce the overhead of the memory access by permitting the memory access to the memory module that does not need the refresh when the refresh counter regularly performs the refresh. .

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a computer system including a memory system to which the memory control method according to the present invention is applied, and FIG. 2 is a diagram for explaining an operation in the memory system. In FIG. 2, the refresh cycle is shown short for the sake of explanation. As shown in FIG. 1, the computer system according to the present embodiment has a central processing unit (CPU) 1 for controlling the whole and a memory module divided into a plurality of memory modules, for example, a memory module 3a /.
3b and the like, and a memory control device 2 that controls writing and reading of data to and from the memory modules 3a / 3b based on an instruction from the central processing unit 1.
Is a refresh counter 4 for monitoring a specified time required for refreshing the memory modules 3a / 3b and the like.
And the memory module 3 based on the instruction from the CPU 1.
A memory control circuit 5 for controlling writing / reading of data to / from a / 3b and the like, and a refresh operation end flag 6a / 6b corresponding to each memory module. The memory control circuit 5 sends a control signal 7a to each memory module. / 7b, etc., while controlling the address / data /
It is configured to exchange common control signals and the like.

The refresh counter 4 is a counter for monitoring the prescribed time required for refreshing the memory modules 3a / 3b and the like, and the refresh operation end flag 6a and the like are refresh operations within the refresh monitoring time corresponding to each memory module. Is a flag for storing the end / non-end of. In this processing system,
When performing read or write access to one memory module, the memory control circuit 5 performs memory access via the control signals 7a / 7b and the like corresponding to the target memory module 3a / 3b and the memory bus 8. Also, when refreshing,
The memory control circuit 5 executes the refresh operation via the control signals 7a / 7b and the like corresponding to the target memory modules 3a / 3b and the like.

Now, a memory control method in the computer system configured as described above will be described with reference to the timing chart of FIG. First, at timing A, when the CPU 1 is activated, the remote control circuit 5 starts counting by the refresh counter 4 and turns off the refresh operation end flags 6a / 6b and the like to the initial state. Next, at a timing B, the remote control circuit 5 performs a read operation to the memory module 3a by the read activation from the CPU 1, and the refresh operation end flags 6b / 6c and later corresponding to the memory modules 3b / 3c and later are turned off, so Module 3
The refresh operation is executed on and after b. By this refresh operation, the refresh operation end flags 6b and later corresponding to these memory modules 3b and later are simultaneously turned on. That is, the end of refreshing of the memory module 3b and thereafter is set. At the timing C, the memory module 3a is read as at the timing B, but the refresh operation end flag 6b and later corresponding to the other memory modules 3b and later are not refreshed. This reduces the frequency of refresh and reduces power consumption compared to the control method that unconditionally executes refresh processing for another memory module while accessing a certain memory as described in the related art. Means that you can do it.

At timing D, the remote control circuit 5 does not perform the refresh operation on any memory module because the memory access from the CPU 1 is not performed. At the timing E, the remote control circuit 5 performs the read operation to the memory module 3b by the read activation from the CPU 1, and the refresh counter 4 finishes the counting at the beginning of the timing E (reset).
Therefore, the memory module 3a whose refresh operation end flag is off is forcibly refreshed. At this time, if there is another memory module that has not been refreshed, the refreshing of the memory module is also performed by referring to the refresh operation end flag. Further, the remote control circuit 5 resets the refresh counter 4 to set all the refresh operation end flags 6a and after corresponding to all the memory modules 3a after the refresh operation is completed for all the above memory modules.
In the conventional technology, since the memory module 3b and subsequent memory cells are also refreshed at this timing E, there is a problem that the write operation is delayed until the next timing F. On the other hand, in this embodiment, this overhead can be eliminated.

At the next timing F, the same operation as that at timing B is performed, and the refresh operation end flag 6b and the subsequent corresponding to the refreshed memory module 3b and after are turned on. At the timing G, the remote control circuit 5 performs a read operation to the memory module 3b by the read activation from the CPU 1, and the memory module 3a
Since the refresh operation end flag 6a corresponding to is off / the other refresh operation end flags 6 are on, the refresh operation is performed only on the memory module 3a. As a result, in this embodiment, it is possible to avoid performing refresh operations more than necessary,
Power consumption can be suppressed. Further, here, by turning on the refresh operation end flag 6a corresponding to the memory module 3a, the refresh operation end flag 6a and later corresponding to all the memory modules 3a and later are set to on.

Timing H is a stage where memory access is not performed, and timing I next shows an example in which the refresh counter 4 finishes counting at the beginning of the timing. However, since the refresh operation end flags 6a and later corresponding to all the memory modules 3a and later are turned on at this point, the refresh operation is not performed and all the refresh operation end flags 6a and later are forcibly set to off. .

If there is a memory access request at this point,
Similarly to the timing B, read or write access is performed to that memory module, refresh is simultaneously performed to another memory module, and only the refresh operation end flag of the memory module that is read or written is turned off. The refresh operation end flags of other memory modules that have been refreshed are held on.

As described above, according to this embodiment, although the average time interval of refresh is the same as the conventional one, the memory access to the specific memory module and the remaining memory modules can be efficiently refreshed at the same time. Thus, the memory access overhead due to refresh can be reduced.

That is, the present invention is provided with a refresh counter 4 for monitoring a specified time for refreshing the memory module 3a and the like, and a refresh operation end flag 6a for storing the refresh status corresponding to the plurality of memory modules 3a and the like. When a certain memory module is reading or writing, the refresh operation and the refresh operation end flag are set to another memory module, and when the refresh counter reaches a specified time, the refresh operation end flag is off. The first feature is that the memory access overhead due to refresh is reduced by forcibly refreshing only a certain memory module.

Further, in the first feature, when one memory module is using the memory bus for reading or writing and the refresh operation is performed for another memory module, the refresh operation end flag is off. A second feature is that the power consumption is reduced by refreshing only a certain memory module. In the first feature, the refresh counter is not reset within a prescribed time and the refresh is forcibly performed. A third feature is that when a required memory module is refreshed, memory access is permitted to other memory modules. Further, in the first feature, when the refresh counter reaches a specified time, all memory modules are accessed. Refresh operation end flag corresponding to the memory module When the refresh is not performed because the switch is on, the refresh counter is cleared, the read or write access is permitted, and if the read or write access is not performed at this time, all refresh operation end flags are turned off. Alternatively, if a read or write access is performed at this time, the other memory modules are refreshed at the same time, and only the refresh operation end flag of the memory module to which the read or write access is performed is turned off, and the other memory module is refreshed. A fourth feature is that the refresh operation end flag remains on.

[0018]

As described above, according to the present invention, a refresh counter for monitoring a specified time for refreshing a memory module and a refresh operation end flag for storing a refresh status of the memory module are provided, and a certain memory module reads data. Alternatively, during writing, the refresh operation and the refresh operation end flag are set to another memory module, and when the refresh counter reaches a specified time, only the memory module whose refresh operation end flag is off is set. By performing the forced refresh, it is possible to reduce the memory access overhead due to the refresh and further reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a computer system including a memory system to which a memory control method according to the present invention is applied.

FIG. 2 is a diagram for explaining an operation in the present memory system.

[Explanation of symbols]

1: Central processing unit (CPU), 2: Memory control device, 3
a / 3b / 3c: memory module, 4: refresh counter, 5: memory control circuit, 6a / 6b /
6c: Refresh operation end flag, 7a / 7b: control signal, 8: memory bus.

Claims (1)

[Claims] 1. A memory control method for writing and reading data to and from a plurality of memory modules requiring refreshing, comprising: a refresh counter for monitoring a specified time for refreshing the memory modules; and the plurality of memories. A refresh operation end flag for storing the refresh status corresponding to the module is provided, and when a certain memory module is being read or written, the refresh operation and the refresh operation end flag are set to another memory module and the refresh operation is performed. When the counter reaches a specified time, the memory module whose refresh operation end flag is off is forcibly refreshed, and the memory access is permitted to the memory module that does not need refresh. Memory control method.