JPH0734499B2 - Hybrid integrated circuit board - Google Patents
Hybrid integrated circuit boardInfo
- Publication number
- JPH0734499B2 JPH0734499B2 JP2117446A JP11744690A JPH0734499B2 JP H0734499 B2 JPH0734499 B2 JP H0734499B2 JP 2117446 A JP2117446 A JP 2117446A JP 11744690 A JP11744690 A JP 11744690A JP H0734499 B2 JPH0734499 B2 JP H0734499B2
- Authority
- JP
- Japan
- Prior art keywords
- thick film
- integrated circuit
- circuit board
- hybrid integrated
- film element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、導体パターンを形成した絶縁基板上に厚膜素
子と薄膜素子とを形成する混成集積回路基板に関するも
のである。The present invention relates to a hybrid integrated circuit board in which a thick film element and a thin film element are formed on an insulating substrate having a conductor pattern formed thereon.
〈従来の技術〉 従来、絶縁基板上に厚膜素子と薄膜素子とを形成する場
合には、例えば第４図に示すように、絶縁基板としての
セラミック基板１の一方の面（図では上面）に回路パタ
ーンとなる導体パターン４を形成し、この上にチップ抵
抗９やチップコンデンサ15等の表面実装部品をはんだ付
け等により固定すると共に、他方の面（図では下面）に
は、両側に薄膜電極11を有する薄膜抵抗８を形成する。
そして絶縁基板11に設けたスルーホール10を介して上面
側と下面側とを電気的に接続する構成が採られている。<Prior Art> Conventionally, when a thick film element and a thin film element are formed on an insulating substrate, for example, as shown in FIG. 4, one surface (upper surface in the drawing) of a ceramic substrate 1 as an insulating substrate is used. A conductor pattern 4 serving as a circuit pattern is formed on the surface, and surface mounting components such as a chip resistor 9 and a chip capacitor 15 are fixed on the conductor pattern 4 by soldering, and the other surface (lower surface in the figure) has thin films on both sides. A thin film resistor 8 having an electrode 11 is formed.
Then, a configuration is adopted in which the upper surface side and the lower surface side are electrically connected via a through hole 10 provided in the insulating substrate 11.
また、他の例として、第５図に示すように、絶縁基板１
の片面に前例と同様、導体パターン４、厚膜抵抗９′及
び上部電極７を有する誘電体厚膜６等を形成し、この上
に絶縁層12を形成し、さらにこの絶縁層12の上面側に薄
膜電極11を有する薄膜抵抗８を形成する。そして、これ
らの電気的接続は、絶縁層12に設けたスルーホール10を
介して行うものである。In addition, as another example, as shown in FIG.
As in the previous example, a dielectric thick film 6 having a conductor pattern 4, a thick film resistor 9 ', and an upper electrode 7 is formed on one surface of the above, an insulating layer 12 is formed on the dielectric thick film 6, and the upper surface side of the insulating layer 12 is further formed. Then, a thin film resistor 8 having a thin film electrode 11 is formed. Then, these electrical connections are made through the through holes 10 provided in the insulating layer 12.
〈発明が解決しようとする課題〉 上述したように、絶縁基板上に厚膜素子と薄膜素子とを
配する場合、１枚の絶縁基板の表面側に厚膜素子、裏面
側に薄膜素子というように分けて配するか、絶縁層を介
して上層部と下層部とに分けて配す構成等が従来から採
用されており、両素子を同一面上に配することは行なわ
れていないのが現状である。この理由として （ａ）厚膜素子の焼成温度が850℃程度、薄膜素子の形
成時の温度が150〜200℃程度と大きく相違すること。<Problems to be Solved by the Invention> As described above, when the thick film element and the thin film element are arranged on the insulating substrate, the thick film element is on the front surface side and the thin film element is on the back surface side of one insulating substrate. It has been conventionally adopted to dispose them separately or to dispose them in an upper layer and a lower layer via an insulating layer, and it has not been done to arrange both elements on the same surface. The current situation. The reason for this is that (a) the firing temperature of the thick film element is about 850 ° C., and the temperature at the time of forming the thin film element is about 150 to 200 ° C.
（ｂ）厚膜素子はAg/Pd電極、薄膜素子はCu/Cr電極と両
素子の電極材料が相違すること。(B) The electrode materials of the thick film element and Ag / Pd electrode are different, and that of the thin film element is Cu / Cr electrode, which are different from each other.
等の問題点があった。前記（ａ）は、まず厚膜素子を焼
成し、次に薄膜素子を形成するなど工程上解決すること
は可能であるが、前記（ｂ）、即ち適用される素子の電
極材料が相違する点は解決できなかった。There were problems such as. In (a), it is possible to solve the process such as first firing a thick film element and then forming a thin film element, but (b), that is, the point that the electrode material of the applied element is different. Could not be resolved.
また、電子回路基板の高密度実装化を進める上で、前述
のように絶縁基板の表裏面をスルーホールを介して電気
的に接続する場合、前記スルーホール及びその周辺に形
成するランドによって実装面が減少し、導体パターンの
収容性を阻害することになっていた。Further, in order to increase the mounting density of electronic circuit boards, when the front and back surfaces of the insulating substrate are electrically connected through the through holes as described above, the mounting surface is formed by the through holes and the lands formed around them. Was reduced, which hindered the accommodation of the conductor pattern.
さらにまた、各素子をはんだ付けによって導体パターン
上に固定しているが、工程不良の大半がはんだ付け不良
（短絡と断線）にあるのが現状であり、今後、回路素子
及び導体パターンの狭小化が更に進行した場合、はんだ
付け不良（特に短絡）の発生は不可避であり、はんだ付
けに代る新しい接続技術の開発が望まれていた。Furthermore, each element is fixed on the conductor pattern by soldering, but most of the process defects are soldering defects (short circuit and disconnection), and in the future, circuit elements and conductor patterns will become narrower. In case of further progress, defective soldering (especially short circuit) is unavoidable, and development of new connection technology instead of soldering has been desired.
本発明は前記欠点を解決すべくなされたものであり、そ
の目的は、スルーホールを介せずかつはんだ付手法を用
いることなしに、絶縁基板の同一面上に厚膜素子と薄膜
素子とが混在した混成集積回路基板を提供することにあ
る。The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is to provide a thick film element and a thin film element on the same surface of an insulating substrate without using a through hole and using a soldering method. It is to provide a mixed integrated circuit board.
〈課題を解決するための手段〉 本発明は上記目的に鑑みてなされたものであり、その要
旨は、金属有機物ペーストを用いて形成した複数の素子
電極上に厚膜素子及び薄膜素子を各々設け、前記各素子
間を導体パターンで接続することにより、絶縁基板の同
一面上に前記厚膜素子と薄膜素子とを混在させて実装す
る混成集積回路基板にある。<Means for Solving the Problems> The present invention has been made in view of the above objects, and its gist is to provide a thick film element and a thin film element on a plurality of element electrodes formed using a metal organic paste, respectively. In the hybrid integrated circuit board, the thick film element and the thin film element are mixedly mounted on the same surface of the insulating substrate by connecting the elements with a conductor pattern.
また、前記導体パターンは、金属有機物ペーストを用い
て焼成するか、又は厚膜ペーストを600〜900℃で焼成し
て形成することも可能である。Further, the conductor pattern can be formed by firing using a metal organic paste or by firing a thick film paste at 600 to 900 ° C.
なお、前記金属有機物ペーストとしては、Au,Ag,Pd,Pt
又はこれらを組み合せた合金の有機化合物をペースト状
にしたものが好ましい。As the metal organic paste, Au, Ag, Pd, Pt
Alternatively, it is preferable to use an organic compound of an alloy obtained by combining these as a paste.
また、前記厚膜素子とは導体、抵抗体、誘電体等の回路
素子をスクリーン印刷法などによって800〜850℃程度で
印刷焼成し形成する素子をいい、前記薄膜素子とは真空
装置内で蒸着、スパッタリング又は気相反応法、陽極反
応法などによって、導体、抵抗体、誘電体等の回路素子
を薄膜に形成する素子をいう。なお、薄膜素子の形成時
の温度は150〜200℃程度である。Further, the thick film element refers to an element formed by printing and firing a circuit element such as a conductor, a resistor or a dielectric at a temperature of about 800 to 850 ° C. by a screen printing method, and the thin film element is vapor-deposited in a vacuum apparatus. , An element in which a circuit element such as a conductor, a resistor or a dielectric is formed into a thin film by sputtering, a vapor phase reaction method, an anode reaction method or the like. The temperature at the time of forming the thin film element is about 150 to 200 ° C.
〈作用〉 ペースト状の前記金属有機物材料を印刷・焼成して、素
子電極を形成する。金属有機物材料を用いて形成した素
子電極は、厚膜及び薄膜の両方の素子に対してマッチン
グも良好であり、安定した電気的諸特性を発揮する。<Operation> The paste-like metal organic material is printed and baked to form a device electrode. The device electrode formed by using the metal organic material has good matching with both the thick film device and the thin film device, and exhibits stable electrical characteristics.
〈実施例〉 本発明に係る混成集積回路基板Ａを添付図面に基づいて
説明する。<Example> A hybrid integrated circuit board A according to the present invention will be described with reference to the accompanying drawings.
まず、絶縁基板としてのセラミック基板１上の片面に素
子電極部4aと各素子間を電気的に接続する導体部4b（第
２図参照）とからなる回路パターンとしての導体パター
ン４を形成する。この形成に際しては金属有機物材料と
しての金を含有した金レジネートペーストをスクリーン
印刷法或いはフォトエッチング法により、パターン化
し、850℃程度の高温で焼成し、形成する。First, a conductor pattern 4 as a circuit pattern including an element electrode portion 4a and a conductor portion 4b (see FIG. 2) for electrically connecting the elements is formed on one surface of a ceramic substrate 1 as an insulating substrate. In this formation, a gold resinate paste containing gold as a metal organic material is patterned by a screen printing method or a photo-etching method and baked at a high temperature of about 850 ° C. to be formed.
次に導体パターン４に、両端部が重なるように所定位置
に厚膜素子を形成する。形成する素子が抵抗体である場
合には、RuO2系、Pb2Ru2O6.5系等の抵抗ペーストを用い
て、また、コンデンサである場合には、ペロブスカイト
構造をもつBaTiO3系の誘電ペーストを用いて、スクリー
ン印刷法によりパターン印刷し、850℃程度で焼成す
る。なお、コンデンサの場合は、この焼成により形成し
た誘電体厚膜６上に上部電極７を形成する。更にこれら
厚膜素子の上を覆うようにガラスコート５を施して厚膜
抵抗体13、厚膜コンデンサ14等の厚膜素子形成工程は終
了する。Next, a thick film element is formed on the conductor pattern 4 at a predetermined position so that both ends thereof overlap. When the element to be formed is a resistor, a resistance paste such as RuO 2 system or Pb 2 Ru 2 O 6.5 system is used, and when the device is a capacitor, BaTiO 3 system dielectric paste having a perovskite structure is used. Is used to perform pattern printing by a screen printing method and is baked at about 850 ° C. In the case of a capacitor, the upper electrode 7 is formed on the dielectric thick film 6 formed by this firing. Further, the glass coat 5 is applied so as to cover the thick film elements, and the step of forming the thick film elements such as the thick film resistor 13 and the thick film capacitor 14 is completed.
次に導体パターン４上にその両端部が重なるように薄膜
素子を形成する。薄膜は真空蒸着法等の従来の方法によ
り形成し、フォトエッチング法によりパターン化して、
薄膜抵抗８を形成する。Next, a thin film element is formed on the conductor pattern 4 so that both ends thereof overlap. The thin film is formed by a conventional method such as a vacuum vapor deposition method and patterned by a photo etching method,
The thin film resistor 8 is formed.
以上の工程により、セラミックス基板１の同一面上に厚
膜素子と薄膜素子とが混在した混成集積回路基板Ａを得
ることができる。Through the above steps, it is possible to obtain the hybrid integrated circuit board A in which the thick film element and the thin film element are mixed on the same surface of the ceramic substrate 1.
これ以降の工程は、従来の製法と同様であり、レーザ・
トリミングにより各素子の抵抗値、容量値を所望の値に
調整し、樹脂コートを施し、リードフレームを取付け、
モールドすればハイブリッドICが完成する。The subsequent steps are the same as those in the conventional manufacturing method.
Adjust the resistance and capacitance of each element to the desired values by trimming, apply resin coating, attach the lead frame,
A hybrid IC is completed by molding.
前記実施例では、金属有機物材料で形成する導体パター
ン４によって、素子電極部4aと導体部4bとを同時に形成
したが、素子電極部4aのみを前記金属有機物材料によっ
て形成することも可能である（第２図）。この場合の形
成工程は、まず、素子電極部4aを850℃で焼成して形成
し、次に導体部4bをAg,Ag-Pd,Cu系等の厚膜導電ペース
トを用いてスクリーン印刷法によりパターン印刷し、60
0〜900℃程度で焼成し形成するものである（第３図）。
これ以降の工程は前記実施例と同様であるので、重複し
て説明するのを避ける。In the above-described embodiment, the element electrode portion 4a and the conductor portion 4b are formed at the same time by the conductor pattern 4 formed of the metal organic material, but it is also possible to form only the element electrode portion 4a by the metal organic material ( (Fig. 2). In this case, the forming step is performed by first baking the element electrode portion 4a at 850 ° C., and then forming the conductor portion 4b by a screen printing method using a thick film conductive paste such as Ag, Ag-Pd, or Cu. Pattern printed, 60
It is formed by firing at about 0 to 900 ° C (Fig. 3).
Since the subsequent steps are the same as those in the above-mentioned embodiment, the description will not be repeated.
なお、厚膜導電ペーストとは、貴金属、酸化物、ガラス
のパウダーと液状の有機バインダを混合して作られたも
のであり、従来から厚膜導体として広く使用されている
ものである。The thick film conductive paste is prepared by mixing powders of noble metal, oxide, glass and liquid organic binder, and has been widely used as a thick film conductor from the past.
〈効果〉 本発明に係る混成集積回路基板は、各素子電極を金属有
機物ペーストを用いて形成したので、絶縁基板の同一面
上に厚膜素子と薄膜素子とを混在させることができる。
従って、スルーホールを設ける必要がないため、表面実
装率を向上させることができると共に、はんだ付けによ
らず各素子を固定できるため、はんだ付け不良による部
品の不良発生率が改善され、また、より一層の高密度集
積化にも十分貢献することができる等、多くの効果が期
待できる。<Effect> In the hybrid integrated circuit board according to the present invention, since each element electrode is formed by using the metal organic paste, the thick film element and the thin film element can be mixed on the same surface of the insulating substrate.
Therefore, since it is not necessary to provide through holes, the surface mounting rate can be improved, and since each element can be fixed without soldering, the failure rate of parts due to soldering failure is improved, and moreover, Many effects can be expected, such as being able to sufficiently contribute to higher density integration.
第１図は本発明に係る混成集積回路基板を示す断面図、
第２図は素子電極部及び導体部を拡大して示す部分斜視
図、第３図は他の実施例の製造工程を示すフローチャー
ト、第４図及び第５図は従来の混成集積回路基板を示す
断面図である。 １……セラミック基板、４……導体パターン、4a……素
子電極部、4b……導体部、Ａ……混成集積回路基板。FIG. 1 is a sectional view showing a hybrid integrated circuit substrate according to the present invention,
FIG. 2 is an enlarged partial perspective view showing an element electrode portion and a conductor portion, FIG. 3 is a flow chart showing a manufacturing process of another embodiment, and FIGS. 4 and 5 show a conventional hybrid integrated circuit board. FIG. 1 ... Ceramic substrate, 4 ... Conductor pattern, 4a ... Element electrode part, 4b ... Conductor part, A ... Hybrid integrated circuit board.
Claims (3)
の素子電極上に厚膜素子及び薄膜素子を各々設け、前記
各素子間を導体パターンで接続することにより、絶縁基
板の同一面上に前記厚膜素子と薄膜素子とを混在させて
形成することを特徴とする混成集積回路基板。1. A thick film element and a thin film element are respectively provided on a plurality of element electrodes formed by using a metal organic paste, and the elements are connected by a conductor pattern so that the same surface of an insulating substrate is formed. A hybrid integrated circuit board, wherein a thick film element and a thin film element are formed in a mixed manner.
を用いて形成することを特徴とする請求項１記載の混成
集積回路基板。2. The hybrid integrated circuit board according to claim 1, wherein the conductor pattern is formed using a metal organic paste.
〜900℃で焼成し形成することを特徴とする請求項１記
載の混成集積回路基板。3. The conductor pattern comprises a thick film paste 600
The hybrid integrated circuit board according to claim 1, wherein the hybrid integrated circuit board is formed by firing at about 900 ° C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2117446A JPH0734499B2 (en) | 1990-05-09 | 1990-05-09 | Hybrid integrated circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2117446A JPH0734499B2 (en) | 1990-05-09 | 1990-05-09 | Hybrid integrated circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0414890A JPH0414890A (en) | 1992-01-20 |
| JPH0734499B2 true JPH0734499B2 (en) | 1995-04-12 |
Family
ID=14711857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2117446A Expired - Lifetime JPH0734499B2 (en) | 1990-05-09 | 1990-05-09 | Hybrid integrated circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0734499B2 (en) |
-
1990
- 1990-05-09 JP JP2117446A patent/JPH0734499B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0414890A (en) | 1992-01-20 |
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