JPH0735824A - Scan path circuit - Google Patents

Abstract

PURPOSE:To enable the building of a scan path with no consideration given to clock skew. CONSTITUTION:A selector 10 of a flipflop 1 selects one of a data from a data input terminal D and a scan data from a scan data input terminal SD according to a scan mode signal from a scan mode terminal M1 to be outputted to a D flipflop 12. An exclusive OR circuit 11 performs an exclusive ORing computation between a scan clock signal from a clock terminal C and a logic value set previously from a scan mode terminal M2 and outputs the results of the computation to the D flipflop 12 as scan clock signal. The D flipflop 12 is operated by a scan clock signal from the exclusive OR circuit 11 to hold data from the selector 10 and the contents held are outputted to an output terminal Q.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanpath circuit, and more particularly to supplying a scan clock to the scanpath circuit.

[0002]

2. Description of the Related Art Conventionally, in a scan path circuit, a one-phase clock is used as a scan clock when all flip-flops that determine the states in a sequential circuit operate as one shift register in the scan mode. Any value can be freely set from the external terminal to all flip-flops.

As a result, the internal state of the sequential circuit can be freely set. It is also possible to read the internal state of the sequential circuit by using the flip-flop that operates as one shift register described above.

That is, as shown in FIG. 4, flip-flops (hereinafter referred to as F / F) 20-1 to 20-4 are vertically connected to each other, and a scan clock (CLK) from a clock input terminal 23 and a scan mode. The scan operation is performed by the scan mode signal from the switching terminal 24. Reference numeral 21 in FIG. 4 is a scan data input terminal (SDIN), 22 is a scan data output terminal (SDOUT), and 25 to 27 are load adjustment buffers.

In the F / F 20-1, the scan mode terminal M
When a scan mode signal from the scan mode switching terminal 24 is input to the selector 28-, as shown in FIG.
The input / output data of the sequential circuit (not shown) input to the data terminal D at 1 and the scan data from the scan data input terminal 21 input to the scan data terminal SD are switched.

The D flip-flop (DFF) 29-1 is operated by the scan clock from the clock input terminal 23, holds the data from the selector 28-1 and holds F / F.
Output to the output terminal Q of F20-1.

Although not shown, F / Fs 20-2 to 20
-4 also has the same configuration as F / F 20-1,
The same operation as F20-1 is performed. As a result, the scan data from the scan data input terminal 21 becomes F / F2.
0-1 to 20-4 are sequentially shifted and output from the scan data output terminal 22.

During the scanning operation of these F / Fs 20-1 to 20-4, as shown in FIG.
When output to the output terminal Q of the / F20-2, in normal operation, as shown by the solid line, F is delayed by one clock.
It is output to the output terminal Q of / F20-3.

Now, due to the delay difference of the clock distribution circuit, F
In the case of a circuit in which the input of the scan clock to the clock terminal C of the / F20-3 is delayed, the output terminal Q of the F / F20-2 and the output terminal Q of the F / F20-3 have the same value, which is indicated by the broken line. As described above, data omission occurs.

That is, the F / Fs 20-1 to 20-4 having a shift register structure by a one-phase clock signal.
Is set, a malfunction occurs due to the skew of the clock distribution of each F / F 20-1 to 20-4.

In order to prevent the malfunction due to the skew of the clock distribution, the phase of the clock supplied to the flip-flops in the even-numbered blocks and the phase of the clock supplied to the flip-flops in the odd-numbered blocks are set. Techniques for making them different from each other have been proposed. This technique is described in detail in JP-A-3-46821.

[0012]

In the conventional scan path circuit described above, the phase of the clock supplied to the flip-flops in the even-numbered blocks and the phase of the clock supplied to the flip-flops in the odd-numbered blocks are To be different from each other to prevent malfunction due to skew of clock distribution.

However, when the block is composed of a plurality of flip-flops, the skew of clock distribution to the flip-flops in the block still exists, and the malfunction in the block cannot be prevented. Further, it is necessary to supply a clock having a different phase to the flip-flops in the even-numbered blocks and the flip-flops in the odd-numbered blocks, or to provide a circuit for reversing the clock phases in the blocks. Become.

Therefore, an object of the present invention is to solve the above-mentioned problems and to provide a scan path circuit capable of forming a scan path without considering clock skew at all.

[0015]

A scanpath circuit according to the present invention is constructed by vertically connecting a plurality of flip-flop circuits, and shift operations of adjacent flip-flop circuits are performed with clock signals having mutually opposite phases. A scan path circuit for switching between normal operation data and scan operation data in accordance with a scan mode signal; and a logical operation for performing a logical operation between the clock signal and a preset logical value. Means and holding means for holding and outputting the output of the switching means according to the output of the logical operation means are provided in each of the plurality of flip-flop circuits.

[0016]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a flip-flop (hereinafter F
/ F) 1 selector 10 selects either the data from the data input terminal D or the scan data from the scan data input terminal SD according to the scan mode signal from the scan mode terminal M1 to select the D flip-flop. Output to the DFF 12.

The exclusive OR circuit 11 performs an exclusive OR operation of the scan clock signal from the clock terminal C and a preset logical value from the scan mode terminal M2, and the operation result is used as the scan clock signal D. Output to the flip-flop 12.

The D flip-flop 12 operates according to the scan clock signal from the exclusive OR circuit 11, holds the data from the selector 10, and outputs the held content to the output terminal Q.

In this F / F1, the logical values from the scan mode terminal M2 to the exclusive OR circuit 11 are set so as to be mutually opposite values between the adjacent F / Fs. For example, if the adjacent F / Fs are operating in the opposite phase of the scan clock signal, the logical value from the scan mode terminal M2 is the opposite value to the adjacent F / Fs.
/ F1 operates in the positive phase of the scan clock signal.

FIG. 2 is a block diagram showing a scan path configuration according to an embodiment of the present invention. In the figure, a scan path circuit according to an embodiment of the present invention is composed of F / Fs 1-1 to 1-4 connected in cascade. Where F /
Each of F1-1 to 1-4 has the same configuration as that of F / F1 shown in FIG. 1 and performs the same operation as that of F / F1.

A scan clock signal (CLK) is supplied from the clock input terminal 4 to the clock terminal C of each of the F / F 1-1 to 1-4, and the scan mode terminal M1 of each of the F / F 1-1 to 1-4. A scan mode signal is supplied from the scan mode switching terminal 5. In addition, 2 in FIG.
Is a scan data input terminal (SDIN), 3 is a scan data output terminal (SDOUT), and 6 to 8 are load adjustment buffers.

On the other hand, the scan mode terminals M2 of each of the F / Fs 1-1 to 1-4 are supplied with reverse logic values by the circuits adjacent to each other. That is, since the scan mode signal is directly supplied from the scan mode switching terminal 5 to the scan mode terminals M2 of the odd-numbered F / Fs 1-1 and 1-3, the scan mode signal is High in the scan mode.
is set to h.

Since the scan mode terminals M2 of the even-numbered F / Fs 1-2 and 1-4 are grounded, they are set to Low in the scan mode. Therefore, in scan mode, odd-numbered F / F1-1, 1
-3 and even-numbered F / Fs 1-2 and 1-4 have logical values opposite to each other.

In this case, odd-numbered F / Fs 1-1, 1-
3 becomes a falling latch because the scan mode terminal M2 is set to High in the scan mode, and the even-numbered F / Fs 1-2 and 1-4 each have the scan mode terminal M2 set to Low in the scan mode. It becomes a rising latch.

FIG. 3 is a time chart showing the operation of one embodiment of the present invention. The operation of the scan path circuit according to the embodiment of the present invention will be described with reference to FIGS.
The scan path circuit according to the embodiment of the present invention is in the scan mode when the scan mode signal is High.

When the scan operation is performed by the scan path circuit, the scan mode terminal M1 of each F / F1-1 to 1-4 is used.
A scan mode signal is supplied from the scan mode switching terminal 5.

As a result, the selector 10 of each of the F / Fs 1-1 to 1-4 has input / output data of a sequential circuit (not shown) input to the data terminal D and scan data input to the scan data terminal SD. The scan data from the input terminal 2 is switched.

In this case, odd-numbered F / Fs 1-1, 1-
Since each of the 3 sets the scan mode terminal M2 to High, the scan data from the scan data input terminal 2 is held at the trailing edge of the scan clock signal.

On the other hand, since even-numbered F / Fs 1-2 and 1-4 are set to the scan mode terminal M2 at Low, the scan data from the scan data input terminal 2 is held at the rising edge of the scan clock signal. To do.

Therefore, in any of the F / F1-1 to 1-4, the data skew due to the clock skew does not occur, and a malfunction occurs due to the clock distribution skew of each F / F1-1 to 1-4. There is nothing to do.

In this way, the F / Fs that are connected in cascade are mutually connected.
By supplying opposite logic values to the scan mode terminals M1 to 1-4 of the circuits adjacent to each other, the odd-numbered F / F1-1 and 1-3 are used as falling latches in the scan mode. , And even-numbered F / F1-2, 1-4
By using each as a rising latch, the scan path can be incorporated without any consideration of clock skew. Therefore, the scan path can be applied to a semiconductor integrated circuit that cannot be modified after fabrication.

Since the above method operates safely even when an asynchronous circuit is included, it is effective when the asynchronous circuit is included or when the clock skew cannot be adjusted in a large-scale circuit.

Therefore, the above F / F1-1 to 1-4
Even when each is divided into blocks and clocks of different phases are supplied, malfunctions within the blocks due to clock skew can be prevented. In this case, it is not necessary to supply clocks with different phases to the flip-flops in the even-numbered blocks and the flip-flops in the odd-numbered blocks, and a circuit for reversing the clock phases in the blocks There is no need to arrange.

[0035]

As described above, according to the present invention, a plurality of flip-flop circuits are vertically connected to each other, and the shift operations of adjacent flip-flop circuits are performed by clock signals having mutually opposite phases. In the scan path circuit, a plurality of flip-flop circuits are provided with means for switching between data during normal operation and data during scan operation according to a scan mode signal, and a logical operation of a clock signal and a preset logical value. By providing the means for holding and outputting the data switched according to the result, there is an effect that the scan path can be configured without considering the clock skew at all.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a scan path configuration according to an embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing a scan path configuration according to a conventional example.

FIG. 5 is a block diagram showing a configuration of a conventional example.

FIG. 6 is a time chart showing an operation of a conventional example.

[Explanation of symbols]

 1, 1-1 to 1-4 Flip-flop 2 Scan data input terminal 3 Scan data output terminal 4 Clock input terminal 5 Scan mode switching terminal 10 Selector 11 Exclusive OR circuit 12 D flip-flop

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 11/22 360 P 7165-5B G06F 1/04 330 Z

Claims (3)

[Claims] 1. A scan path circuit configured by vertically connecting a plurality of flip-flop circuits, wherein each adjacent flip-flop circuit performs a shift operation with clock signals having opposite phases to each other. Switching means for switching between data and data during a scan operation according to a scan mode signal, logical operation means for performing a logical operation between the clock signal and a preset logical value, and the output of the switching means for the logical operation. A scan path circuit, wherein each of the plurality of flip-flop circuits includes holding means for holding and outputting according to the output of the means. 2. The adjacent flip-flop circuits are logically operated by a logical operation between a logical value set to have a value opposite to a logical value of the adjacent flip-flop circuits and the clock signal. 2. The scanpath circuit according to claim 1, wherein the scanpath circuit is configured to generate a clock signal having a phase opposite to that of the clock signal of. 3. The scan path circuit according to claim 1, wherein the logical operation means is an exclusive OR circuit.