JPH0736736A - Microprocessor - Google Patents

Abstract

PURPOSE:To confirm an operation even when a branching instruction is present by specifying one of (n) instructions simultaneously fetched by a code input means. CONSTITUTION:By HWJMP signals 109 for indicating branching to a half word boundary, a tracing device 103 can specify which instruction between the two instruction included in a fetched word the branching is performed to. Thus, in the case of tracing the instruction execution of this microprocessor 101 for fetching the plural instructions in one bus cycle, since the HWJMP signals 109 are outputted along with bus cycle information, the tracing device 103 for confirming the operation and whether or not all the fetched instructions are to be executed can accurately trace the branching instruction and highly accurate operation confirmation can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device, and more particularly to a microprocessor whose operation is monitored by a trace device.

[0002]

2. Description of the Related Art When debugging a program of an information processing device such as a microprocessor, a device for tracing the execution of the program is sometimes used in order to improve the debugging efficiency. This utilizes the fact that whenever a microprocessor executes an instruction, it fetches the instruction from the main memory (instruction fetch), and monitors the address signal to the main memory and the status signal of the instruction fetch to dynamically execute the instruction. It outputs the order of execution (however, if the system uses a cache memory, the instruction address may not be output to the main memory, so consider a system that does not use a cache memory here).

Further, there is a method of improving the performance of the microprocessor by fetching a plurality of instructions at once in order to increase the efficiency of fetching from the main memory. For example, if the data bus is a 32-bit microprocessor, if one instruction length is 32 bits, only one instruction can be fetched by one instruction fetch, but if the instruction length is 16 bits, one instruction fetch is performed. Two instructions can be fetched by this instruction fetch, and the efficiency of instruction fetch is improved.

However, a problem arises when the trace device using the above-mentioned instruction fetch is applied to such a processor that fetches a plurality of instructions at once.

This problem will be described below using a conventional example.

FIG. 4 is a diagram showing an example in which a trace device is connected to a conventional microprocessor. In the figure, 401 is a microprocessor (hereinafter referred to as MPU), 402 is a main hidden device (hereinafter referred to as memory), 403 is a trace device,
404 is a 30-bit wide address bus, 405 is a 32-bit wide data bus, 406 is a BUSCY signal indicating that the MPU 401 is issuing a bus cycle, 407.
Is a BUSST signal indicating the type of bus cycle output by the MPU 401, and 408 is an R / W signal indicating whether the bus cycle output by the MPU 401 is read or write.

In order for the MPU 401 to read or write an instruction or data stored in the memory 402, a target address is put on the address bus 404, and the read data put on the data bus 405 by the memory 402 is fetched to the MPU 401, or Putting data to be written in the memory 402 on the data bus 405 is called issuing a bus cycle.

In the conventional system, the BUSCY signal 4
The bus cycle is valid while 06 outputs 1.

A BUSST signal 407 that changes in synchronization with the BUSCY signal 406 is used to distinguish whether the bus cycle being issued is for instruction fetch or for data access. BUSST signal 40
When 7 is 0, the bus cycle is for data access, and when 1 is 1, it is for instruction fetch.

Further, in order to distinguish whether the bus cycle is a data access or a read, the MPU4
01 outputs the R / W signal 408. R / W signal 408
When is 0, it indicates writing, and when it is 1, it indicates reading.

The system of this conventional example is byte addressing in which an address is assigned for each byte.
It has an address space of 4 GB by a bit address. However, since the data bus 405 has a width of 32 bits, data of 4 bytes is accessed at one time. Therefore, since the lower 2 bits of the 32-bit address do not need to be designated to the memory 402, the address bus 404 has a width of 30 bits. Hereinafter, a group of 4-byte data will be referred to as word data.
In addition, [0000 0004H], [1234 5678H], [FFFF FFFC
Addresses that are multiples of 4 such as [H] are called word boundary addresses, and addresses that are multiples of 4 and +2, such as [9876 5432H] and [0000 ABCEH], are called halfword boundary addresses.

The instruction output by the MPU 401 has a fixed length of 16 bits. On the other hand, since the data bus 405 has a width of 32 bits, two instructions can be simultaneously fetched into the MPU 401 by one instruction fetch.

The trace device 403 has an address bus 404 output by the MPU 401, a BUSCY signal 406, and a BU.
It is an additional device that monitors the SST signal 407 and detects the order in which the instructions are executed by the MPU 401 from the presence or absence of an instruction fetch bus cycle.

FIG. 6 shows the operation when such a microprocessor system executes the program shown in FIG.
And shown in FIG.

First, the program shown in FIG. 5 will be described.

This program is an example of a multi-way branch that branches to a plurality of branch destinations according to the contents of the register.

Depending on the value from 0 to 3 stored in the register r1 in advance, the addresses [0000 0000H], [0000 000
2H], [0000 0004H], or [0000 0006H].

First, [mov # 2, r2] at the address [0000 0100H]
The instruction substitutes the constant 2 in the register r2. Subsequently, the [mul r1, r2] instruction at the address [0000 0102H] multiplies the registers r1 and r2 and stores the result in the register r2. Here, the register r2 is a constant 2
Therefore, the content of the register r1 is doubled and then stored in the register r2.

By this multiplication, the branch destination address is calculated, and the [jmp [r2]] instruction at the address [0000 0104H] branches to the address indicated by the register r2. If the content of the register r1 is 0, the address is [0000 0000H], and if the content is 1, the address is [0000 0002H].

When this program is executed by the apparatus shown in FIG. 4, one instruction fetch includes two instructions. Therefore, when a branch occurs, only the instruction of the bus cycle from the outside determines which instruction as the branch destination. There is a problem that it is not possible to determine whether or not was executed. This problem will be described below with reference to FIGS. 6 and 7.

FIG. 6 and FIG. 7 show the instruction fetch bus cycle that can be observed from the outside and the internal instruction execution arranged side by side in chronological order.

First, the operation when the value of the register r1 is 0 is shown in FIG.

[0000 0 in the program shown in FIG.
In order to execute the [mov # 2, r2] instruction of the address [100H], the MPU 401 first moves from the address [0000 0100H] to [0000 0103].
An instruction fetch bus cycle is issued to fetch 4 bytes up to the address H] from the memory 402 (501). Since the length of one instruction is 16 bits, this 4 bytes contains two instructions. Therefore, inside the MPU401, the [mov # 2, r2] instruction at the address [0000 0100H] and [000
[0102H] The [mul r1, r2] instruction at the address is continuously executed (502, 503). Since the initial value of the register r1 shown in FIG. 6 is 0, the value of the register r2 after multiplication is also 0.

Next, since the MPU 401 executes the [jmp [r2]] instruction at the address [0000 0104H], it fetches 4 bytes from the address [0000 0104H] to the address [0000 0107H] (504). Although these 4 bytes also include two instructions, the first instruction is an unconditional branch instruction, so the second nop instruction is not executed and is discarded.

Since register r2 is 0, [jmp [r
2]] Execution of the command causes the execution of the program to be [0000 0000
H] Branch to the address (505). MPU401 is [0000
[Instruction A] at address [0000H] is executed, so [0000
Four bytes from the address [0000H] to the address [0000 0003H] are fetched (506). After [instruction A] and [instruction B] are continuously executed (507, 508), two operations are fetched again by instruction fetch and continuously executed, which is repeated.

Next, the operation when the content of the register r1 is 1 is shown in FIG.

The procedure up to the point where the [jmp [r2]] instruction at the address [0000 0104H] is executed is the same as in FIG.
Since the initial value of is 1, the multiplication result of register r2
Is 2, and the branch destination of the [jmp [r2]] instruction is the address [0000 0002H].

Since the MPU 401 executes the [instruction B] at the address [0000 0002H], it tries to fetch the address in which the [instruction B] is stored. However, MPU4
01 is a 32-bit bus that fetches two instructions at the same time,
[Instruction B] is fetched together with [Instruction A] by instruction fetch for 4 bytes from [0000 0000H] to [0000 0003H], and [Instruction A] is discarded (516).

After this instruction fetch, the [instruction B] is executed (518), and thereafter, the operation of fetching two instructions by the instruction fetch and continuously executing the same is repeated as in FIG.

Here, a problem occurs in the instruction execution trace by the trace unit 403. As can be seen from FIGS. 6 and 7, the instruction fetch bus cycles are issued in the same manner in these two examples, although the internal operations are different. Since the trace unit 403 determines the order of the execution instructions based on the instruction fetch bus cycle, it is not possible to judge whether the [instruction A] at the address [0000 0000H] has been executed only by the bus cycle sequence of FIG. 6 or 7. .

[0031]

When a trace device which outputs an instruction execution order by externally monitoring an instruction fetch bus cycle is used in a microprocessor which fetches a plurality of instructions in one bus cycle, the trace device is fetched. Since it is not possible to determine whether all or some of the instructions that have been executed are executed only by the bus cycle, it becomes impossible to accurately trace the branch instruction, and the trace device accurately monitors the operation of the microprocessor. There is a problem that can not be done.

The present invention has been made in view of the problems of the above-mentioned conventional technique, and realizes a microprocessor capable of confirming the operation even when there is a branch instruction. With the goal.

[0033]

The microprocessor of the present invention has address specifying means for outputting an address of an instruction code and a width of n × m bits, and is capable of simultaneously fetching n m-bit length instructions. It has an instruction code input means and a branch destination instruction notification means for specifying one of the n instructions fetched simultaneously by the code input means.

[0034]

Since a signal for notifying which instruction of the plurality of instructions read by the instruction fetch has branched is output from the microprocessor to the trace device, the plurality of instructions can be executed in one bus cycle. Enables instruction trace of the capturing microprocessor.

[0035]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a diagram showing an example in which a trace device is connected to a microprocessor according to an embodiment of the present invention.

In the figure, 101 is a microprocessor (hereinafter referred to as MPU), 102 is a main memory (hereinafter referred to as memory), 103 is a trace device, 104 is a 30-bit wide address bus, and 105 is 32-bit wide data. Bus, 1
Reference numeral 06 denotes a BUSCY signal indicating that the MPU 401 issues a bus cycle, 107 indicates a BUSST signal indicating the type of bus cycle issued by the MPU 401, 10
Reference numeral 8 is an R / W signal indicating whether the bus cycle issued by the MPU 401 is read or write, 109
Is a HWJMP signal that notifies the trace device that a branch has occurred at a halfword boundary.

The memory 102, the address bus 104, the data bus 105, the BUSCY signal 106, the BUSSST signal 107, and the R / W signal 108 are the components of the memory 402, the address bus 404, and the data bus in the conventional example shown in FIG. 405, BUSCY signal 40
6, the same as the BUSSST signal 407 and the R / W signal 408, and thus the description thereof is omitted.

The HWJMP signal 109 output by the MPU 101 in this embodiment differs depending on the branch destination when an instruction fetch occurs due to a branch. When the branch destination is a word boundary, it is 0, and the branch destination is half. If it is on a word boundary, 1 is output, and its output timing is output at the same timing as the BUSCY signal 106.

2 and 3 show the operation when such a microprocessor system executes the program shown in FIG. 5 as in the case of the conventional example.

The program shown in FIG. 5 is the same as that cited in the conventional example, and since it has been described in the section of the conventional example, the description thereof is omitted here.

When this program is executed by the apparatus shown in FIG. 1, HWJMP indicating a branch to a halfword boundary
The signal 109 allows the trace unit 103 to specify which of the two instructions contained in the fetched word the branch has taken.

FIGS. 2 and 3 show the instruction fetch bus cycle that can be observed from the outside and the internal instruction execution when the values of the register r1 are 0 and 1, respectively, arranged in chronological order.

First, the operation when the value of the register r1 is 0 will be described with reference to FIG.

[0000 0100H] in the program of FIG.
To execute the [mov # 2, r2] instruction at the address, first the MPU
101 issues an instruction fetch bus cycle to fetch 4 bytes from the address [0000 0100H] to the address [0000 0103H] from the memory 102 (301). Since the length of one instruction is 16 bits, this 4 bytes contains two instructions. Therefore, [00
[Mov # 2, r2] instruction at address 00 0100H] and [0000 0102H]
The [mul r1, r2] instruction at the address is continuously executed (30
2, 303). In the example shown in FIG. 2, since the initial value of the register r2 is 0, the value of the register r2 after multiplication is also 0.

Next, since the MPU 101 executes the [jmp [r2]] instruction at the address [0000 0104H], it fetches 4 bytes from the address [0000 0104H] to the address [0000 0107H] (304). Two instructions are also included in these 4 bytes, but since the first instruction is an unconditional branch instruction,
The second nop instruction is discarded without being executed.

After this, since the register r2 is 0,
Executing the [jmp [r2]] instruction causes the program to be executed by [00
00 0000H] is branched to (305). Since the MPU 101 executes the [instruction A] at the address [00000000H],
Four bytes from the address [0000 0000H] to the address [00000003H] are fetched (306).

Here, since the branch destination of the [jmp [r2]] instruction is not a halfword boundary but a word boundary, H
WJMP signal 109 is BUSCY signal 106, BUSS
0 is output at the same timing as the T signal 107 (30
9). This output is input to the trace unit 103 together with the fetch address on the address bus 104, and the trace unit 103 recognizes that all the instructions fetched by the instruction fetch are executed.

[Instruction A] and [Instruction B] in the MPU 101
Are continuously executed (307, 308), two instructions are fetched again by instruction fetch, and the operations are continuously executed.

Next, the operation when the content of the register r is 1 will be described with reference to FIG.

Up to the point where the [jmp [r2]] instruction at the address [0000 0104H] is executed, it is the same as the case shown in FIG. 2, but since the initial value of the register r2 is 1, the multiplication result register The value of the crossover is 2, and the branch destination of the [jmp [r2]] instruction is the address [0000 0002H].

Since the MPU 101 executes the [instruction B] at the address [0000 0002H], it tries to fetch the address where the [instruction B] is stored. However, MPU
Since 101 uses a 32-bit bus to fetch two instructions at the same time, [Instruction B] is fetched by instruction fetch for 4 bytes from [0000 0000H] to [0000 0003H] with [Instruction A], and [Instruction A] is It will be discarded (316).

Here, since the branch destination by the [jmp [r2]] instruction is the halfword boundary, the HWJMP signal 109 outputs 1 at the same timing as the BUSCY signal 106 and the BUSST signal 107 (319). This output is input to the trace unit 103 together with the fetch address on the address bus 104, and the trace unit 103 selects [0000 0000] from among the instructions fetched by the instruction fetch.
It is recognized that the [instruction A] at the address H] is not executed by the MPU 101.

After the above-mentioned instruction fetch, [instruction B] is executed (318), and thereafter, the same operation as in FIG. 2 is repeated by fetching two instructions by instruction fetch and continuously executing them.

As described above, by adding the HWJMP signal 109, the trace device 103 can distinguish a branch to a word boundary and a branch to a halfword boundary, which have exactly the same movement in only a bus cycle,
Accurate instruction trace is possible.

In the above embodiment, the address is set to 3
Since the instruction is 2 bits and the instruction has a fixed length of 16 bits, the output content required for the HWJMP signal 109 has two types, that is, a branch destination is a word boundary area or a half word boundary area. The number of signal lines to be increased is one.

Even if the address is of 64 bits and the instruction has a fixed length of 16 bits, the HW
The number of signal lines that are increased to output the JMP signal 109 is two, and the burden imposed on the device when implementing the present invention is extremely low.

[0058]

Since the present invention is constructed as described above, it has the following effects.

When tracing the instruction execution of the microprocessor which fetches a plurality of instructions in one bus cycle, the HWJMP signal is output together with the bus cycle information as to whether all or some of the fetched instructions are executed. Therefore, the tracing device that confirms the operation can accurately trace the branch instruction, and thus the operation can be confirmed with high accuracy.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention to which a trace device is connected.

FIG. 2 is a diagram showing an operation of the embodiment shown in FIG.

FIG. 3 is a diagram showing an operation of the embodiment shown in FIG.

FIG. 4 is a diagram showing a configuration of a conventional example to which a trace device is connected.

5 is a diagram showing an example of a program executed by the device shown in FIG.

FIG. 6 is a diagram showing an operation of a conventional example.

FIG. 7 is a diagram showing an operation of a conventional example.

[Explanation of symbols]

 101 MPU 102 Memory 103 Trace Device 104 Address Bus 105 Data Bus 106 BUSCY Signal 107 BUSST Signal 108 R / W Signal 109 HWJMP Signal

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[Procedure amendment]

[Submission date] November 10, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

Claims (1)

[Claims] 1. An instruction designating means for outputting an instruction code address; an instruction code inputting means having a width of n × m bits and capable of simultaneously capturing n m-bit length instructions; Has a branch-destination instruction notifying means for specifying one of the n instructions fetched at the same time, and when the branch-destination instruction of the program being executed is fetched, the branch-destination instruction address is designated by the address designating means. And a branch destination instruction notifying unit for notifying to the outside.