JPH0737892A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a highly reliable semiconductor device by making it possible to sufficiently remove contamination substance even with a high- temperature short time or low-temperature short time heat-treatment. CONSTITUTION:A groove 22 is provided consisting of an element isolation insulating film 4 formed on the surface of a semiconductor substrate and an element region surrounded by this element isolation insulating film 4, is formed so as to pass through the element isolation insulating film 4 and to reach the semiconductor substrate, and is filled with a substance 23 having higher efficiency of collecting impurities within the substrate inside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a structure for efficiently removing contaminants such as heavy metals and light metals from element formation regions.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit devices are becoming highly integrated, and in order to improve their reliability, impurities such as heavy metals and light metals taken into the inside of electronic devices are removed to improve electrical characteristics. Need to raise.

That is, heavy metal contamination introduced into the silicon substrate during the manufacturing process of a semiconductor device forms a trap center for free electrons (holes) or causes leakage of a pn junction, which may affect the electrical characteristics of the semiconductor element. Deteriorate. For example, when heavy metals such as Fe, Cu, Ni, and Au are introduced into the silicon substrate, the MOS lifetime is reduced and D
RAM holding time is shortened. Further, it is reported that the metal contaminant introduced into the gate oxide film causes deterioration of electrical characteristics such as withstand voltage and leak current of the oxide film and increase of defect density.

As described above, heavy metal pollution causes deterioration of its electrical characteristics, and especially in the production of ULSI, even a small amount of pollution deteriorates or fluctuates the element characteristics, which is a major cause of lowering the production yield. ing.

Two countermeasures have conventionally been taken against such pollutants.

One of the methods is to reduce the contamination of the wafer as much as possible by cleaning the production environment. A technology for reducing dust and pollution in a clean room is being developed as ultra clean technology. However, it is difficult to achieve complete cleaning of these production environments due to various factors such as time and cost.

The other is to remove contaminants such as heavy metal contamination from the device forming region. There are a method of removing contaminants by wet or dry etching and a method of removing by gettering.

The impurity removal method by wet or dry etching can remove impurities on the surface of the semiconductor substrate without etching the substrate, but impurities in the semiconductor substrate include contaminants from the surface of the semiconductor substrate. In this method, the impurity substance is simultaneously removed by etching the semiconductor substrate up to the region. The method for etching the semiconductor substrate is, for example, acid etching with HF + HNO ₃ or NH.
Alkaline etching with ₄ OH, CF ₄ , NF ₃
Such as gas etching. Although these methods can remove the contaminants on the semiconductor substrate surface and the substrate relatively easily, the semiconductor substrate surface needs to be shaved every time a process in which the contamination occurs is performed. Due to the pattern configuration in which the distance between the elements is short, it is a great cause of reliability deterioration that the wafer is repeatedly ground during the formation process.

On the other hand, the method of removing impurities by gettering that does not require etching of the substrate is roughly divided into two methods, namely intrinsic gettering (IG) and extrinsic gettering (EG).

In the intrinsic gettering, the wafer itself is subjected to a low temperature heat treatment at 650 to 750 ° C. to form oxygen precipitate nuclei, and then a high temperature heat treatment at 1000 ° C. or higher to form an oxygen precipitate, and the surrounding area. This is a method of depositing contaminants on strains or defects. In addition, prior to this two-step heat treatment, a high temperature heat treatment of about 1200 ° C. is often performed to prevent oxygen precipitation in the element active region near the surface. This gettering method requires oxygen as an impurity inside the wafer, and the heat treatment for forming oxygen precipitates is important. In other words, in order to create the optimum precipitation state, it is necessary to control the thermal history of the wafer in all thermal processes from low temperature to high temperature, and advanced technology is required in consideration of the dislocation strength of the wafer. Further, the IG effect can be expected in the CZ crystal, but the effect cannot be expected in the FZ crystal containing few oxygen impurities.

On the other hand, the extrinsic gettering includes ring gettering for gettering impurities on the back surface of the wafer, wafer back surface damage gettering, and wafer back surface polysilicon gettering.

In ring gettering, phosphorus is diffused from the back surface of the wafer in the final step of the process, and contaminating metal is deposited in the phosphorus diffusion region to remove heavy metals from the active region of the device. In order to perform the ring gettering, for example, POCl ₃ is used as a source gas of phosphorus, and the wafer is heated to 80% to form a high concentration phosphorus diffusion layer.
It is necessary to expose it to a high temperature of 0 ° C or higher.

In the wafer backside damage gettering, mechanical strain is intentionally formed on the backside of the wafer. As a result, oxygen-induced stacking faults are generated in the first oxidation step in the ULSI manufacturing process using the mechanical strain as a nucleus, and metal impurities are deposited there. The mechanical strain can be formed, for example, by spraying silicon oxide fine powder on the back surface of the wafer. Wafer back surface polysilicon gettering is a method in which a polysilicon film is deposited on the back surface of the wafer and metal impurities are deposited at the grain boundaries of the polysilicon. In these gettering methods, the gettering site is located on the back surface of the wafer, which will be a serious problem for future gettering technology. In other words, from the perspective of the degree of integration in the future semiconductor industry, the degree of integration will increase, and due to the relationship between cost and yield, the diameter of silicon wafers will inevitably increase, resulting in problems such as wafer warpage and strength. The thickness of the wafer increases. In addition, a shallow impurity diffusion layer is required for high integration, and as a result, the allowable time for high temperature heat treatment is shortened. Alternatively, either low temperature heat treatment or long treatment time must be taken. Therefore, it is very difficult to diffuse the metal impurities near the wafer surface to the gettering site on the back surface and sufficiently remove the contaminants from the element forming layer.

Due to these problems, it is necessary to form gettering sites on the surface of the wafer. As a result, by implanting high-energy ions into the surface of the wafer, the gettering sites are formed several μm deep from the element forming layer. Inspiring front side gettering was invented. In these methods, ion implantation damage is caused within a range of several μm from the wafer surface, and metal impurities are deposited in the defects. However, this method requires high-energy ion implantation, and as a result, metal impurities in the ion chamber are simultaneously implanted into deep sites. Further, there is a problem that crystal defects may be given to the shallow element formation region.

In order to increase the wafer thickness with the increase in the diameter of the wafer to obtain high productivity and to lower the temperature of the process for the development of the ultrafine element, the current gettering method uses a metal. There is a problem that contaminants of impurities cannot be removed sufficiently.

[0016]

As described above, even if the ultra clean technology aiming at the complete normalization of the whole process progresses, even if a small amount of pollution deteriorates the device characteristics due to the ultra-miniaturization of the device, gettering The removal of pollutants by means of the process becomes an indispensable step in ULSI manufacturing. Therefore, further advanced thermal history management is performed and the IG
It is necessary to establish technology as a technology with a higher degree of perfection. However, against the problems of increasing the wafer thickness due to the larger diameter of the wafer and lowering the process temperature for the development of ultra-fine elements, which is expected in the future, metal impurities near the wafer surface are gettered on the back surface. It cannot be said that the conventional EG technique of diffusing to the site and removing the pollutant from the device forming layer has been sufficiently addressed.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a highly reliable semiconductor device by which contaminants can be sufficiently removed by heat treatment at high temperature for a short time and at low temperature for a short time. And

[0018]

Therefore, in the present invention, an element isolation insulating film formed on the surface of a semiconductor substrate and an element region surrounded by the element isolation insulating film are provided, and the element isolation insulating film is penetrated. Then, a groove is formed so as to reach the semiconductor substrate, and the inside thereof is filled with a metal impurity collecting substance.

According to a second aspect of the present invention, a wiring layer formed on the surface of a semiconductor substrate, an insulating film provided on the semiconductor substrate with a groove reaching the semiconductor substrate, and the groove being filled, And a pseudo wiring layer made of a metal impurity collecting material formed so as to be in direct contact with the semiconductor substrate.

According to a third aspect of the present invention, the device isolation region is formed of a groove formed on the surface of the semiconductor substrate, and the device region surrounded by the device isolation region is formed. It is characterized in that it is configured by being filled with a metal impurity collecting substance through a sidewall insulating film, and that this substance is in direct contact with the substrate in at least a part of the groove.

According to a fourth aspect of the present invention, it comprises an element isolation region formed on the surface of a semiconductor substrate and an element region surrounded by the element isolation region, and a metal is provided in the element region in an unpleasant portion rather than an element portion. It is characterized in that it comprises a groove that is filled with an impurity collecting substance and that is configured such that at least a part of this substance is in direct contact with the substrate.

Materials having a high efficiency of collecting impurities in the substrate include amorphous silicon, polysilicon, amorphous silicon or polysilicon in which one of phosphorus and boron is added, phosphorus-doped silicate glass (PSG), boron-doped silicate. Glass (BS
G), or silicate glass containing phosphorus and boron (BP)
SG), Ti, W, Ta, or any other metal silicide, or a composite thereof. Further, in order to enhance the gettering effect, it is desirable that the concentration of B and P in the film is 10 ²⁰ atoms / cm ³ or more.

[0023]

According to the present invention, the gettering site formed inside the groove or hole of the trench structure exists on the surface of the semiconductor substrate, so that the thermal diffusion time of the metal impurities required for removing the metal impurities is short. The metal impurities can be sufficiently incorporated into the gettering site even by the low temperature heat treatment. Further, the effect can be sufficiently obtained even when the temperature is lowered as compared with the conventional one without causing the temperature rise in the manufacturing process. Further, as compared with the conventional method of forming the gettering site on the back surface, the gettering site can be formed in a region close to the element region, so that the gettering effect is significantly improved and the reliability is improved.

Further, as compared with front side gettering by high-energy ion implantation in which a gettering layer is formed on the surface of a semiconductor substrate, a gettering of a groove or a hole of a trench structure is performed by reactive ion etching or wet etching having a lower acceleration voltage. Since it is formed as a ring site, there is no damage such as contamination and crystal defects.
Further, in the front side gettering by high energy ion implantation, since the defects due to ion implantation act as gettering sites, the defects are recovered by once performing high temperature heat treatment, and the gettering effect is reduced. On the other hand, in the method of the present invention, a substance having a gettering effect is embedded in the surface of the substrate, so that the gettering effect is not essentially lowered no matter how many times the heat treatment is repeated unless the substance itself disappears. Therefore, it is extremely effective from the viewpoint of the sustainability of the gettering effect. For example, a DR including a transistor and a capacitor
Since a gettering layer can be formed under the capacitor electrode in AM, it is possible to prevent a decrease in MOS lifetime, a decrease in memory holding time, and the like.

According to the first aspect of the present invention, in addition to the above operation, a groove is formed so as to penetrate the element isolation insulating film and reach the semiconductor substrate, and a substance having a high impurity collection efficiency in the substrate is filled in the groove. Therefore, the unnecessary portion of the substrate is used, and thus the element area is not increased.

In the second aspect of the present invention, at least a part of the pseudo wiring layer provided for flattening in order to reduce the surface step difference with the wiring layer formed on the surface of the semiconductor substrate reaches the semiconductor substrate. Since the formed substrate is made of a substance having a high impurity collection efficiency, the unnecessary portion of the substrate is utilized in addition to the above-mentioned action, and thus the element area is not increased.

In a third aspect of the present invention, in an element isolation structure using a trench, the element isolation region is formed by filling the trench with a substance having a high impurity collection efficiency in the substrate through a sidewall insulating film, and at least the above Since this material is in direct contact with the substrate in a part of the groove, it can be easily formed without increasing the man-hours, and the stress in the thermal process is smaller than in the case where the trench is filled with only an insulator, and cracks can be prevented. There is no such problem.

According to a fourth aspect of the present invention, a groove having a structure in which a substance having a high efficiency of collecting impurities in the substrate is filled in a deeper portion than the element portion in the element region and at least a part of the substance is in direct contact with the substrate. The gettering substance can be arranged closer to the element, and the gettering efficiency is further improved.

For example, when polysilicon is used as the gettering site, the metal impurities are quickly gettered to the crystal grain boundaries of polysilicon to remove device contamination.

[0030]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor device according to the first embodiment of the present invention. In this semiconductor device, a gettering layer 3 made of phosphorus-doped polysilicon is filled inside a trench T formed on the surface of a silicon substrate via a sidewall insulating film 8 made of a silicon oxide film, and acts as a gettering site 2. , Element isolation region,
A device (not shown) is formed in a region surrounded by the device isolation region.

According to this structure, since the gettering site having the durability is formed on the surface of the semiconductor substrate, the diffusion time required for removing the metal impurities can be sufficiently secured even in the low temperature process. Furthermore, since polysilicon is closer to the thermal efficiency of a silicon substrate than silicon oxide, stress in the heating process is small, and there is no problem such as cracks. FIG. 2 is a modification of the first embodiment of the present invention. A trench is formed in advance at the bottom of the element isolation insulating film 4 formed in 1., a side wall insulating film 8 made of a silicon oxide film is formed as in the first embodiment, and a gettering layer made of phosphorus-doped polysilicon is formed inside. Two
Is filled.

In this structure, the trench can be thinned or thickened as shown in FIG. 3 according to the size of the element isolation region.

Next, as a second embodiment of the present invention, MO
It is characterized in that the well isolation in the S device is constituted by element isolation by a trench.

First, as shown in FIG. 4, an n-type diffusion layer 6 and a p-type diffusion layer 7 are sequentially formed on the surface of a semiconductor substrate 1, and a resist pattern 5 is formed. A trench T is formed between the type diffusion layer 6 and the p-type diffusion layer 7 so as to reach the substrate.

After this, as shown in FIG. 5, a silicon oxide film 8 is formed on the trench surface. The silicon oxide film may have any structure such as a single insulating film or a laminated insulating film as long as it is an insulating film.

Next, as shown in FIG. 6, the unnecessary silicon oxide film 8 and the silicon oxide film at the bottom of the trench are removed by etching. The acid or silicon film at the bottom may be partially removed.

After that, as shown in FIG. 7, a filling material made of amorphous silicon is deposited on the entire surface and etched back to form a gettering layer 3 by leaving the filling material made of amorphous silicon inside the trench (FIG. 8). .

Then, the upper surface of the trench is oxidized and insulated to complete the trench isolation (FIG. 9). In this way, the filling material having a gettering effect has a structure in which it directly contacts the silicon substrate at the bottom of the trench isolation.
The metal impurities in the substrate are captured by the filling material from the bottom.

It is not necessary to fill the entire trench with the filling material, and another material may be filled in, such as filling the insulating film 9 such as tetraethoxysilane in the upper portion as shown in FIG.

Next, FIG. 10 shows the result of measuring the gettering ability in the low temperature process by the present invention and the back surface EG of the conventional example at a constant processing time. Here, the change in the recombination life of the bulk minority carriers with the low temperature heat treatment time was measured for the wafer in which Fe was forcibly contaminated on the wafer surface of the semiconductor device having the gettering site 2 of Example 1. In the drawing, the case where no gettering is applied is shown as Comparative Example 3, and the case where back surface polysilicon gettering, which is the conventional EG method, is performed is shown as Comparative Example 4. As is clear from this result, in the present invention, the recombination life of the bulk minority carriers is restored to the level of a non-contaminated wafer by the heat treatment within 1 hour even at a low temperature of 600 ° C. On the other hand, in the conventional EG, since the gettering site is formed on the back surface of the wafer, it is necessary to diffuse impurities such as Fe to the back surface, so that the diffusion time becomes long.

As described above, it is understood that the front side gettering of the present invention is extremely effective in the low temperature process or the high temperature short time process for the contamination in the element active region near the wafer surface.

Next, as a third embodiment of the present invention, in a device using element isolation by trench isolation, the inside of the trench is filled with a gettering substance so as to make electrical contact with the substrate at the bottom of the trench. The semiconductor device will be described.

As shown in FIG. 12, in this semiconductor device, a trench T is formed in an n-type silicon layer 1W formed on the surface of a silicon substrate 1, and inside the trench T, boron-doped via a sidewall insulating film 8. It is characterized in that the gettering substance 3 such as polysilicon is filled so as to be electrically connected to the substrate 1 at the bottom of the trench and the device is isolated. In the element region surrounded by the element isolation trench T, a gate electrode 10 formed via a gate insulating film 11 and p-type diffusion layers as source / drain regions 12 and 13 are formed to form a MOSFET. There is.

Also in this case, since the element isolation region is used as a gettering site, the gettering layer can be arranged at a position close to the surface, and the gettering effect is extremely high.

Next, as a fourth embodiment of the present invention, MO
An example in which the gettering layer 3 is formed on the bottom of the capacitor of the DRAM including the SFET and the capacitor will be described with reference to the manufacturing process diagrams of FIGS.

In this example, first, as shown in FIG. 13, the element isolation insulating film 4 is formed on the surface of the substrate 1 by the LOCOS method (covered with the buffer oxide film 14), and then the silicon nitride film 15 is interposed. A silicon oxide film 5 having a desired film thickness is formed by a CVD method, and these are patterned and anisotropically etched using the mask as a mask to form a trench T.

Then, as shown in FIG. 14, a gettering layer 3 made of a phosphorus-doped polysilicon layer is formed in the trench.

Further, the gate electrode 10 is formed through the gate insulating film 11 by a usual method, and p-type diffusion layers as the source / drain regions 12 and 13 are formed by diffusion to form a MOSFET, and The surface of the trench T is oxidized and covered with the insulating film 8S, and the storage node electrode 16, the capacitor insulating film 17, and the plate electrode 18 are sequentially stacked to form a capacitor (FIG. 15).
Here, one of the source / drain regions 12 and 13 and the storage node electrode 16 are in contact with each other so as to be electrically connected. Reference numeral 19 is an interlayer insulating film.

According to this method, in addition to the above effects,
A highly reliable DRAM, in which metal impurities that tend to adhere to the inside of the trench are efficiently removed by the trench etching.
Can be obtained. That is, since a gettering site can be formed under the capacitor, M
It is possible to prevent a decrease in OS lifetime and a decrease in DRAM memory holding time.

As a modification of this structure, as shown in FIG. 16, there is an example in which the storage node of the trench capacitor is formed of the diffusion layer 20 formed on the outer periphery of the trench. In this case, the gettering layer 3 is formed at the bottom of the trench to form the gettering site 2, and the middle portion of the trench is filled with the silicon oxide film 9 by the CVD method to insulate and separate the gettering site and the trench. A capacitor is formed on. With this structure, it is possible to obtain a highly reliable DRAM as in the above embodiment.

Although the gettering site is formed in the bottom of the trench and the capacitor is formed in the upper part in the above embodiment, the present invention is not limited to this, and other elements may be formed in the upper part. It goes without saying that it is good.

Next, as a fifth embodiment of the present invention, an example in which the gettering site 2 is formed through the element isolation insulating film 4 will be described. Here, as shown in FIG. 17, a gettering layer formed of a phosphorus-doped polysilicon layer which is a substance penetrating the element isolation insulating film 4 to reach the silicon 1 and having a high efficiency of collecting impurities in the substrate. The gettering site 2 is provided with a groove 22 filled with 23.

First, in manufacturing, after forming the element isolation insulating film 4 by the LOCOS method, the groove 2 is formed by photolithography so as to penetrate the element isolation insulating film 4.
Form 2. An element (here, MOSFET) is formed in the element region surrounded by the element isolation insulating film 4. First, the gate oxide film 11 and the gate electrode 10 are formed, and then the phosphorus concentration is 10 ²¹ atoms / A cm ³ polysilicon layer 23 is formed and patterned to form a gettering layer 23. Here, the gettering layer 23 directly contacts the substrate 1 inside the element isolation insulating film 4. Although the surface of the gettering layer 23 is above the surface of the element isolation insulating film 4 here, it may be in the same plane.

Then, the formation is completed through the formation of the source / drain regions 12 and 13, the formation of the interlayer insulating film 9, the formation of the wiring layer, etc. The metal impurities mixed in these steps are the poly impurities of the gettering layer 23. The silicon crystal grain boundaries are quickly gettered, and contamination is removed from the device active region, resulting in improved performance and improved reliability.

Further, since the groove 22 can be provided at a distance of at most several μm from the transistor, a sufficient gettering effect can be obtained even at a low temperature heat treatment.
Furthermore, if the heat treatment temperature is the same, the gettering can be completed in a short time, so that the manufacturing time can be significantly reduced. Further, since this polysilicon is insulated by the element isolation insulating film 4, it has no electrical effect on the adjacent transistor.

In this embodiment, polysilicon is used as the filler having the gettering effect, but other materials such as those mentioned above may be used as the filler, and the filler may be in direct contact with the substrate. It only needs to be embedded, and the method of forming the groove and the method of filling the filler can be appropriately selected.

As a modification, as shown in FIG. 18, a polysilicon layer 23, which is a gettering layer, is buried slightly below the surface of the groove 22, and the upper portion is covered with a cap layer 24 made of a silicon oxide film. You can

Further, as shown in FIG. 19, the element isolation insulating film for forming the gettering site 2 is not limited to the one formed by the LOCOS method, and may be embedded in the buried oxide film 34 in the trench isolation trench. You may

Furthermore, in this example, the gettering layer can be formed in the same step as the gate electrode. The manufacturing process diagram is shown in FIGS.

First, at the time of manufacturing, as shown in FIG. 20, a trench T for element isolation is formed on the surface of the silicon substrate 1 and a buried insulating film is formed in the trench T to form the element isolation insulating film 34.

Thereafter, an element (here, MOSFET) is formed in the element region surrounded by the element isolation insulating film 34. First, the gate oxide film 11 is formed and then the resist pattern R is formed by photolithography. Then, the groove 22 is formed so as to penetrate the element isolation insulating film 34 (FIG. 21).

Then, as shown in FIG. 22, after removing the resist pattern R, a polysilicon layer having a phosphorus concentration of 10 ²¹ atoms / cm ³ is formed.

Finally, as shown in FIG. 23, this is patterned to obtain the gettering layer 2 simultaneously with the gate electrode 10.
3 is formed. Here, the gettering layer 23 directly contacts the substrate 1 inside the element isolation insulating film 4.

Then, the source / drain regions 12 and 13 are formed, the interlayer insulating film 9 is formed, the wiring layer is formed, and the surface protective film 1 is formed.
9 is completed, the metal impurities mixed in these steps are quickly gettered to the crystal grain boundaries of polysilicon of the gettering layer 23, and the contamination is removed from the device active region. Therefore, the performance is improved and the reliability is improved.
Although the FET is formed, the gettering layer 23 made of the polysilicon layer also functions as a flattening pseudo pattern for relaxing the step due to the gate electrode, and also has a function of facilitating the formation of the upper layer wiring. Here, since the polysilicon is fixed at the same potential as the substrate, there is no influence of noise on the upper wiring.

Further, when the element isolation insulating film is formed by LOCOS isolation, the gettering layer can be formed in the same step as the gate electrode. The manufacturing process diagrams are shown in FIGS. 24 to 27.

First, in manufacturing, as shown in FIG. 24, the element isolation insulating film 4 is formed on the surface of the silicon substrate 1 by the LOCOS method, the gate insulating films 11 and 11 'are formed, and then the gate is formed by photolithography. Insulating film 11
A resist pattern R is formed on top. Using the resist pattern R as a mask, the gate insulating film 11 'is removed by anisotropic etching to expose the substrate (FIG. 25).

Then, as shown in FIG. 26, after removing the resist pattern R, a polysilicon layer 10 having a phosphorus concentration of 10 ²¹ atoms / cm ³ is formed.

Finally, this is patterned to form the gettering layer 23 at the same time as the gate electrode 10. Here, the gettering layer 23 directly contacts the substrate 1 inside the element isolation insulating film 4.

Then, the source / drain regions 12 and 13 are formed, the interlayer insulating film 9 is formed, the wiring layer is formed, and the surface protective film 1 is formed.
9 is completed, the metal impurities mixed in these steps are quickly gettered to the crystal grain boundaries of polysilicon of the gettering layer 23, and the contamination is removed from the device active region. Therefore, the performance is improved and the reliability is improved.

Furthermore, the structure shown in FIG.
FIG. 28 shows an example applied to S. Here, similarly, it is possible to form the gettering layers 23a and 23b at the same time as the formation of the gate electrode 10, but in the CMOS, the gettering layers are fixed to the potentials of the p well 31 and the n well 32. , Gettering layer 23 in each well
a and b are insulated from each other.

In addition, FIG. 19 shows a sixth embodiment of the present invention.
An example will be described in which the gettering layer 23 having the structure shown in is used as a contact electrode for fixing the well potential. That is, as shown in FIGS. 29A and 29B, when a MOSFET is formed in the element region formed in the p well 31 on the surface of the silicon substrate 1 and surrounded by the element isolation insulating film 34, the element isolation insulating film is formed. A feature is that a gettering layer is formed in the trench formed in 34 and is used as a contact electrode. The steps up to the step of forming the gate electrode and the polysilicon layer to be the gettering layer are the same as the steps of the embodiment shown in FIG. 19, but here the silicide layer 2 is further formed on the polysilicon layer.
5 is formed to have a polycide structure. 23 to 2
The gettering layer is formed and the insulating film 19 is formed in exactly the same manner as in the step shown in FIG. 7, then the contact hole 36 is formed in the insulating film 19, the wiring 35 is formed, and the element formation region is formed in the p well 31. It is configured to uniformly apply a potential from around the. The silicide layer is formed here by avoiding the voltage drop due to the sheet resistance of the polysilicon layer,
This is to reduce the resistance.

Conventionally, a large number of well contacts are provided around the well in order to uniformly apply the p-well potential. According to this method, however, the well contacts are integrated because they are integrally connected by the gettering layer. The number of well contacts can be drastically reduced and the degree of freedom in layout can be increased.

Furthermore, as a seventh embodiment of the present invention, an example in which the gettering layer 23 having the structure shown in FIG. 19 is applied to a DRAM having a laminated capacitor structure will be described. In this structure, as shown in FIG. 30, when a storage node contact 41 is formed so as to be connected to one of the source / drain regions 12 and 13 after the MOSFET is formed and a storage node electrode 46 is formed, element isolation insulation is performed at the same time. A contact 41G is also formed in the film 34, and a P-doped polysilicon layer is embedded in the contact 41G in the same step as the storage node electrode and used as the gettering layer 23. In this structure, the capacitor insulating film 47 and the plate electrode 48 are formed on the gettering layer 23 similarly to the storage node electrode 46, so that the capacitor area can be increased.

In this way, without increasing man-hours,
It is possible to improve the gettering effect and form a highly reliable DRAM. Here, 42 is a bit line contact, and 50 is a bit line.

Although the gettering layer is formed at the same time as the step of forming the storage node electrode in the above embodiment, it may be formed at the same time as the formation of the bit line 50 as shown in FIG. In this case, the gettering layer is formed in the bit line forming step which is the final step, so that the planarization is more efficient. Furthermore, it is possible to form the gettering layer in the same process as the plate electrode and the wiring layer.

The semiconductor device of the present invention is characterized in that a gettering site is formed in the element isolation region, and the other structures are not limited in any way, and various devices are formed in the upper layer. It goes without saying that it is okay.

The gettering layer may be a single material or a composite material, and can be appropriately changed without departing from the spirit of the present invention.

[0079]

As described above, according to the present invention, the metal impurities can be efficiently removed even by the low temperature heat treatment, and the gettering can be completed in a short time to shorten the manufacturing time. It becomes possible to provide a highly reliable device even in a low temperature process required for a fine element structure.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a view showing a modified example of the same semiconductor device.

FIG. 3 is a view showing a modified example of the same semiconductor device.

FIG. 4 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 5 is a view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 6 is a view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 7 is a view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a view showing a manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a view showing the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a diagram showing a modification of the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a diagram showing the relationship between the processing time and the recombination lifetime in the gettering method of the present invention and the gettering method of the conventional example.

FIG. 12 is a diagram showing a third embodiment of the present invention.

FIG. 13 is a view showing a manufacturing process of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 14 is a view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 15 is a view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention.

FIG. 16 is a diagram showing a modification of the semiconductor device of the fourth embodiment of the present invention.

FIG. 17 is a diagram showing a manufacturing process of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 18 is a diagram showing a modification of the semiconductor device according to the fifth embodiment of the present invention.

FIG. 19 is a diagram showing a modification of the semiconductor device of the fifth embodiment of the present invention.

FIG. 20 is a view showing the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 21 is a view showing the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 22 is a diagram showing a manufacturing process of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 23 is a diagram showing the manufacturing process of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 24 is a diagram showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 25 is a diagram showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 26 is a diagram showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 27 is a diagram showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

FIG. 28 is a diagram showing a semiconductor device according to another embodiment of the present invention.

FIG. 29 is a diagram showing a semiconductor device according to a sixth embodiment of the present invention.

FIG. 30 is a diagram showing a semiconductor device according to another embodiment of the present invention.

FIG. 31 is a diagram showing a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Si substrate 2 Gettering site 3 Gettering layer 4 Element isolation insulating film 5 CVD oxide film 6 Diffusion layer 7 Diffusion layer 8 Sidewall insulating film 9 Insulating film 10 Gate electrode 11 Gate insulating film 12 Diffusion layer 13 Diffusion layer 14 Oxide film 15 Nitride film 16 Storage node electrode 18 Plate electrode 19 Interlayer insulating film 20 Diffusion layer 46 Storage node electrode 47 Capacitor insulating film 48 Plate electrode 49 Interlayer insulating film 50 Bit line

Claims (4)

[Claims] 1. An element isolation insulating film formed on a surface of a semiconductor substrate, and an element region surrounded by the element isolation insulating film, so as to penetrate the element isolation insulating film to reach the semiconductor substrate. A semiconductor integrated circuit device, characterized in that the semiconductor integrated circuit device is provided with a groove formed therein and filled with a metal impurity collecting substance. 2. A wiring layer formed on the surface of a semiconductor substrate, an insulating film provided on the semiconductor substrate and having a groove reaching the semiconductor substrate, and filling the groove and being in direct contact with the semiconductor substrate. And a pseudo wiring layer made of a metal impurity collecting material formed as described above. 3. An element isolation region formed of a groove formed on the surface of a semiconductor substrate, and an element region surrounded by the element isolation region, wherein the element isolation region is provided in the groove with a sidewall insulating film interposed therebetween. And a metal impurity collecting substance filled therein, and the substance is in direct contact with the substrate in at least a part of the groove. 4. An element isolation region formed on the surface of a semiconductor substrate, and an element region surrounded by the element isolation region, wherein the element region is filled with a metal impurity collecting substance at a portion deeper than the element portion. A semiconductor integrated circuit device having a groove configured so that at least a part of the material is in direct contact with the substrate.