JPH0737896A - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] To provide a semiconductor device including a bipolar transistor having a small occupied area. A trench is provided in an element formation region defined by an element isolation region of a first conductivity type substrate, and a trench is provided in an edge region of the trench opening and a second region below the trench bottom.
A conductive type collector and an emitter are provided, an insulating film is provided on the side wall of the trench, a polysilicon layer is buried, and a first conductive type base is formed in another adjacent element formation region. Collector, emitter, and base electrodes are connected to the silicon layer and the base, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device.
More specifically, it relates to a semiconductor device having a bipolar transistor.

[0002]

2. Description of the Related Art Conventional methods of manufacturing a lateral PNP bipolar transistor include a first method that does not use a trench and a second method that uses a trench. The first method is as follows. First, as shown in FIG. 4A, the substrate of the N ⁻ silicon substrate 51 is oxidized to form an oxide film, on which nitride deposition is performed, and a lateral PNP bipolar transistor is formed by photo and nitride etching. The locos oxidation is performed by leaving the nitride only in the portion that is formed and becomes the active region, and the locos oxide film 52 is formed.
Next, the nitride is removed.

As shown in FIG. 4 (b), the portions serving as the emitter and the collector are formed by photolithography using a resist film 53.
Ion implantation of ⁴⁹ BF ₂ ⁺ 54 is performed to form a P ⁺ layer 55.
As shown in FIG. 4 (c), a portion which becomes the base extraction diffusion is photolithographically opened using the resist film 55 and ⁷⁵ As ⁺ 56
Is ion-implanted to form an N ⁺ layer 57. As shown in FIG. 4D, NSG (non-doped silicate glass) and BPSG (boron, phosphorus-doped silicate glass) are deposited to form an insulating layer 58, a contact is opened by photo and etching, and a metal is formed. After deposition, the wiring 59 is formed by photo and etching to form a lateral PNP bipolar transistor. A plan view of a conventional lateral PNP bipolar transistor is shown in FIG. In the lateral PNP bipolar transistor of this structure,
Current flows laterally across the wafer surface from the emitter to the collector.

The second method is as follows. Figure 5
As shown in (a), the substrate 60 is oxidized to form an oxide film 61, and a resist film 62 is used to perform an oxide film etch and a silicon etch to form a trench 63. As shown in FIG. 5B, the P ⁺ layer 64 is formed by doping the trench sidewalls with P-type impurities that will serve as emitters and collectors. This is performed by the diffusion method using diborane or the like. Subsequently, polysilicon is deposited and P ⁺ is doped. This is performed by ⁴⁹ BF ₂ ⁺ ion implantation or the like. Then, photo and polysilicon etching are performed to form the P ⁺ polysilicon layer 6
5 is formed.

As shown in FIG. 5C, an oxide film is etched using the resist film 66 and ion implantation of ⁷⁵ As ⁺ 67 is carried out to form N ⁺ which serves as base extraction diffusion. Figure 5
As shown in (d), NSG and BPSG are deposited to form an insulating film 68, contacts are opened by photo and etching, metal deposition is performed, and wiring 69 is formed by photo and etching. Lateral PNP bipolar Form a transistor. A plan view of a trench type lateral PNP bipolar transistor is shown in FIG.
83030 publication).

[0006]

The first prior art lateral PNP bipolar transistor has a base region on the wafer surface and a current flows laterally from the emitter to the collector. Therefore, there is a problem that the transistor has a large occupied area and cannot pass a large current.

Second conventional trench-type lateral P
Since the NP bipolar transistor has a large area where the emitter and the collector face each other, a large current can flow. However, since it diffuses laterally from the side wall of the trench, it is necessary to secure a sufficient space between the emitter and the collector. Therefore, there is a problem that the area occupied by the transistor becomes large and high integration cannot be achieved.

The present invention has been made in order to solve the above problems, and provides a semiconductor device which is a bipolar transistor which occupies a small area and can flow a large current.

[0009]

According to the present invention, the first
An element formation region partitioned by an element isolation region is provided on a conductivity type substrate, and three or more second conductivity type diffusion layers are arranged in parallel in one element formation region to alternately constitute collectors and emitters. A collector electrode and an emitter electrode are alternately electrically connected to each other, and a diffusion layer of the first conductivity type is disposed in another adjacent element formation region to form a base. In a semiconductor device including a transistor, the second conductivity type diffusion layer is provided in an edge region of an opening of one or more trenches provided in an element formation region and a lower region of a bottom of the trench. Provided is a semiconductor device which comprises a collector and an emitter, respectively, and in which an insulating film for electrically insulating the collector and the emitter and a conductive layer for connecting the emitter and the emitter electrode are buried in a trench.

The semiconductor device of the present invention can be manufactured, for example, as follows. First, an element isolation region is formed on the first conductive silicon substrate by a known method to partition the element formation region. The element isolation region is formed by using, for example, the Locos method or the like. Next, a trench is formed in the element formation region by photolithography. The number of trenches may be one or two or more. The trench is typically 1-2 μm wide and 3-4 μm deep.

Next, a silicon oxide layer is laminated in a region including the inside of the trench by the CVD method and etched by the anisotropic dry etching method to form an insulating film (sidewall spacer) along the sidewall of the trench. This insulating film includes a second conductivity type diffusion layer (collector) arranged in an edge region of an opening of a trench formed in a later step and a second conductivity type diffusion layer (collector) arranged in a lower region of the bottom of the trench. It is to insulate the conductive layer connected to the emitter. This film thickness is usually 0.2 to 0.3 μm.

Next, the element formation region in which the trench is not formed is masked with a photoresist film, and the second conductivity type impurities are ion-implanted from above the element formation region in which the trench is formed. A second conductivity type diffusion layer is formed in the region and a region below the bottom of the trench. In the second conductivity type diffusion layer, the edge region of the trench opening serves as a collector,
The lower region of the bottom of the trench becomes the emitter.

Next, the element formation region in which the trench is formed is masked with a photoresist film, and impurities of the first conductivity type are ion-implanted from above the element formation region in which the trench is not formed, so that the first conductivity type diffusion layer is formed. To form. The first conductivity type diffusion layer serves as a base. This step can also be performed after forming the conductive layer in the trench. Next, a conductor is stacked in a region including the inside of the trench and etched back so that the conductor remains at least only in the trench to form a conductive layer. This conductor may be a metal for electrodes, but is preferably polysilicon containing impurities of the second conductivity type.

This conductive layer is connected to the emitter in the lower region of the trench bottom and is insulated from the collector in the edge region of the trench opening by an insulating film (sidewall spacer). Next, an insulating layer is formed on the entire surface, the collector,
The contacts of the emitter and the base are opened by the photolithography method, the metal for the electrode is deposited, the collector electrode, the emitter electrode and the base electrode are formed by performing the photo and the etching, the bipolar transistor is formed, and the semiconductor device is completed.

[0015]

By forming the trench, the second conductive type diffusion layer is provided in the edge region of the trench opening and in the lower region of the trench bottom to form a collector and an emitter, respectively, and a thin insulating film provided on the sidewall of the trench. Achieves insulation between the collector and the polysilicon layer connecting to the emitter with a small footprint.

[0016]

Embodiments of the present invention will be described with reference to the drawings. Example 1 As shown in FIG. 1A, an N ⁻ substrate (1 × 10 ¹⁶ cm ⁻³ )
250 Å oxidation on the 1st, nitride deposition 12
00 Å, the nitride is left only in the portion where the bipolar transistor is formed and becomes the active region by photo and nitride dry etching, the resist is removed, and the 6000 Å locos oxide film 2 is formed by the locos oxidation method. Next, the nitride is removed.

As shown in FIG. 1B, the portion to be trench-etched is opened by photo using the resist film 3, and silicon dry etching is performed to 3 μm to form a trench 4. As shown in FIG. 1C, the resist 3 is removed, the oxide film is deposited by 10000Å, and a sidewall spacer (insulating film) 5 is formed on the sidewall of the trench by anisotropic dry etching. Then, the portion where the emitter and collector are formed is opened by photo using the resist film 6 ⁴⁹ BF ₂ ⁺
5 × 10 ¹⁵ cm ^{−2 is} ion-implanted into the wafer vertically to form a P ⁺ layer.

As shown in FIG. 1D, the resist 6 is removed. P ⁺ polysilicon is deposited to a thickness of 4 μm and dry-etched so as to remain only in the trench to form a P ⁺ polysilicon layer 9. As shown in FIG. 1 (e), a portion of the base where diffusion is formed is opened by photo using a resist film 10 and ⁷⁵ As ⁺ is injected at 5 × 10 ¹⁵ cm ^-2 , and N ⁺
Form the layer 11.

As shown in FIG. 1 (f), NSG (non-doped tosilicate glass) 1000Å and BPSG (boron, phosphorus-doped tosilicate glass) 10000Å are deposited to form an insulating layer 12, and contacts are photo and etched. The metal 13 is deposited by 1 μm, and the wiring 13 is formed by photo and etching to form a PNP bipolar transistor. This occupied area is shown in FIG.
It is small as shown in (c).

Example 2 As shown in FIGS. 1A to 1C, the sidewall spacers 5 are formed in the same manner as in Example 1. Next in FIG.
As shown in (a), P ⁺ polysilicon is deposited by 4 μm, and a P ⁺ polysilicon layer 20 is formed by photo and etching, leaving only the emitter and collector. Thereafter, the impurities of the emitter and the collector are diffused from the P ⁺ polysilicon layer 20 by the unil.

As shown in FIG. 2B, the P ⁺ polysilicon layer 20 is separated on the emitter and the collector by photo and etching. The resist is removed, and the portion of the base where diffusion is formed is opened by photo using the resist film 21 and ⁷⁵ As ⁺ 22 is injected at 5 × 10 ¹⁵ cm ^-2 to form the base layer 23. As shown in FIG. 2 (c), NSG1000Å
And BPSG10000Å are deposited and insulation layer 24
Then, the contact is opened by photo and etching, the metal is deposited by 1 μm, and the wiring 25 is formed by photo and etching to form a PNP bipolar transistor. This occupied area is small as shown in FIG.

Example 3 As shown in FIG. 1A, the locos oxide film 2 is formed in the same manner as in Example 1. Next, as shown in FIG.
The two trench-etched portions are opened by photo using the resist film 31, and silicon dry etching is performed to 3 μm to form the trench 32.

As shown in FIG. 3B, the resist film 31 is removed, the oxide film is deposited by 10000Å, and the sidewall spacer 33 is formed on the side wall of the trench by anisotropic dry etching. Then, the portion where the emitter and collector are formed is opened by photo using the resist film 34 ⁴⁹ B
F ₂ ⁺ 35 is vertically ion-implanted into the wafer at 5 × 10 ¹⁵ cm ^-2 to form a P ⁺ layer 36.

As shown in FIG. 3C, the resist film 34
To remove. P ⁺ polysilicon is deposited by 4 μm and dry-etched so as to remain only in the trench to form a P ⁺ polysilicon layer 37. As shown in FIG. 3D, the resist film 38 is formed on the portion where the extraction diffusion of the base is formed.
Then, ⁷⁵ As ⁺ 39 is injected by photolithography using 5 × 10 ¹⁵ cm ⁻² to form an N ⁺ layer 40.

As shown in FIG. 3 (e), 1000Å and B
The insulating layer 41 is formed by depositing PS10000Å, the contact is opened by photo and etching, and the metal 1
After depositing μm, the wiring 42 is formed by photo and etching to form a PNP bipolar transistor. This occupied area is small as shown in FIG.

Further, this PNP bipolar transistor was able to increase the current drive capacity per unit area by about 5 times as compared with the conventional PNP bipolar transistor shown in FIG. 6 (b). Although P ⁺ polysilicon is used for extracting the emitter diffusion in the above-mentioned embodiment, it is also possible to directly extract the metal.

Besides the above embodiments, an NPN transistor may be used. Although the above-mentioned embodiment shows an example of a single PNP element, the structure of the present invention is usually applied to an integrated circuit.

[0028]

According to the present invention, it is possible to provide a semiconductor device including a bipolar transistor having a small occupied area.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a manufacturing process of a semiconductor device manufactured in an example of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process of a semiconductor device manufactured in an example of the present invention.

FIG. 3 is an explanatory diagram of a manufacturing process of a semiconductor device manufactured in an example of the present invention.

FIG. 4 is an explanatory diagram of a manufacturing process of a conventional semiconductor device.

FIG. 5 is an explanatory diagram of a conventional manufacturing process of a semiconductor device.

FIG. 6 is an explanatory diagram of the occupied area of the bipolar transistor of the semiconductor device manufactured in the example of the present invention.

[Explanation of symbols]

1 N ^- Substrate 2 Locos Oxide Film 3 Resist Film 4 Trench 5 Sidewall Spacer (Insulating Film) 6 Resist Film 7 ⁴⁹ BF ₂ ⁺ 8 P ⁺ Layer 9 P ⁺ Polysilicon Layer 10 Resist Layer 11 N ⁺ Layer 12 Insulating Layer 13 wiring

Claims (1)

[Claims] 1. A first-conductivity-type substrate has element-forming regions partitioned by element-isolating regions, and three or more second-conductivity-type diffusion layers are arranged in parallel in one element-forming region, and collectors are alternately arranged. And an emitter, the collector electrode and the emitter electrode are alternately electrically connected to this, and the first conductivity type diffusion layer is disposed in another adjacent element forming region to form a base,
In a semiconductor device in which a base electrode is electrically connected to this to form a bipolar transistor, the second conductivity type diffusion layer is arranged in an element formation region.
Alternatively, an insulating film disposed in the edge region of the opening of two or more trenches and in the lower region of the bottom of the trench to configure a collector and an emitter, respectively, and electrically insulating the collector and the emitter in the trench, and an emitter and an emitter electrode. A semiconductor device in which a conductive layer that connects the two is buried.