JPH0738005A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Objective] A thin film SO of a fully depleted type which improves carrier transport efficiency of an SOI lateral bipolar transistor.
Provided is a semiconductor device which can easily realize a high-performance CMOS device in combination with an I-structure MOS element. [Structure] An electrode (10, 12, 37) for biasing carriers is provided at a position facing a base (22, 32), and preferably a double gate thin film SOI structure MO.
A bipolar transistor formed on the same substrate as the S element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a high performance SOI lateral bipolar transistor suitable for a BiCMOS structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, further large scale and high performance of LSIs have been demanded. Among them, B which has high integration of CMOS, low power consumption and high speed of bipolar transistor.
An LSI having an iCMOS structure is receiving attention. This BiC
In the MOS structure, a bipolar element and a MOS element are simultaneously formed on the same substrate by being mixedly mounted, and the functions of both elements are combined.

On the other hand, in a MOS structure FET whose gate length is miniaturized to a sub-half micron level, deterioration of subthreshold characteristics due to a short channel effect becomes a problem, and complete depletion is an effective means for solving this problem. Type double-gate thin film SOI structures have been receiving attention.

Therefore, Bi of sub-half micron class
It is considered that in a CMOS structure LSI, a MOS structure FET element is mainly composed of a fully depleted thin film SOI structure, and an SOI lateral bipolar transistor is important as a bipolar element suitable for combination with such a MOS element. . This SOI lateral bipolar transistor has a structure in which an emitter, a base and a collector are formed in parallel on one surface side of a silicon diffusion substrate so as to face a gate oxide film. A combination of such an SOI lateral bipolar transistor and a MOS device made of the thin film SOI having the double-gate structure having the complete depletion type is used.
It is possible to realize a high-performance LSI with the iCMOS structure.

[0005]

However, the conventional SOI lateral bipolar transistor has a problem that the carrier transport efficiency is low. The cause is that carriers injected from the emitter to the base side are
Before reaching the collector from the base, S with many recombination centers
This is because the probability of recombination and disappearance at the interface of i-SiO ₂ is high.

The present invention has been made in view of the above-mentioned problems of the prior art, and improves the carrier transport efficiency of an SOI lateral bipolar transistor, and has a high performance in combination with a MOS device having a thin film SOI structure of a full depletion type. C
An object of the present invention is to provide a semiconductor device capable of easily realizing a MOS device and a manufacturing method thereof.

[0007]

To achieve the above object, a bipolar element constituting a semiconductor device according to the present invention is characterized by having an electrode for biasing carriers at a position facing a base.

Further, in the semiconductor device according to the present invention, a bipolar element having an electrode for biasing carriers at a position facing a base and a MOS element having a double gate thin film SOI structure are formed on the same substrate. Characterize.

In a preferred embodiment, the bipolar element is an SOI lateral bipolar transistor.

According to the present invention, in a method of manufacturing a semiconductor device in which a bipolar element and a MOS element having a double-gate thin film SOI structure are mixedly mounted on the same substrate, at the same time as the step of forming the back gate electrode of the MOS element, parallel to this step. A method for manufacturing a semiconductor device, characterized in that an electrode for carrier bias is formed at a position facing the base of the bipolar element.

Further, according to the present invention, in a method of manufacturing a semiconductor device in which a bipolar element and a MOS element having a double-gate thin film SOI structure are mixedly mounted on the same substrate, the step of forming the back gate electrode of the MOS element is performed in parallel with the step. An electrode for carrier bias is formed at a position facing the base of the bipolar element, and the same electric conductive film is used.
A bipolar element emitter, a collector contact,
Provided is a method for manufacturing a semiconductor device, which comprises forming a gate electrode of a MOS element.

Further, according to the present invention, in a method of manufacturing a semiconductor device in which a bipolar element and a MOS element having a double gate thin film SOI structure are mixedly mounted on the same substrate, the step of forming the back gate electrode of the MOS element is performed at the same time as the step of forming the back gate electrode. An electrode for carrier bias is formed at a position facing the base of the bipolar element, and the base of the bipolar element and the source and drain of the MOS element are formed by diffusion from the same electrically conductive film. A method for manufacturing a device is provided.

Further, in the present invention, in a method of manufacturing a semiconductor device in which a bipolar element and a MOS element having a double gate thin film SOI structure are mixedly mounted on the same substrate, the bipolar element is formed in parallel with the step of forming the back gate electrode of the MOS element. An electrode for carrier bias is formed at a position facing the base of the device, and the same electrically conductive film is used to form the emitter, collector contact, and MOS of the bipolar device.
The gate electrode of the device is formed, and the base and the MO of the bipolar device are formed by diffusion from the same electrically conductive film.
Provided is a method for manufacturing a semiconductor device, which comprises forming a source and a drain of an S element.

In a preferred embodiment, after forming a back gate electrode of the MOS element and an electrode for carrier bias of the bipolar element on a silicon substrate, a substrate for supporting the entire device is provided on the electrode forming surface side. It includes a step of laminating and a step of polishing the silicon substrate.

[0015]

Function: An electrode is provided on the SiO ₂ back gate oxide film side of the base region of the SOI lateral bipolar transistor,
By applying a bias, carriers injected from the emitter to the base are pushed back to the center of the base. This prevents recombination in the Si-SiO ₂ interface to improve the transport efficiency of the carrier.

Further, the carrier bias electrode is a MOSF of a fully depleted thin film SOI double gate structure.
By forming the back gate electrode of the ET element at the same time as and in parallel with it, it is possible to efficiently and easily perform high performance BiCMO.
Realization of an S-structure semiconductor device is achieved.

[0017]

1 to 5 show cross sections of a semiconductor device having a BiCMOS structure according to an embodiment of the present invention in the order of manufacturing steps. It should be noted that the thickness and size of each layer are slightly different in order to facilitate the understanding of the characteristic portions in the drawings for the sake of convenience of the drawings, but FIGS. 1 to 5 show a series of manufacturing steps using the same material. is there.

First, in FIG. 1, an N-type silicon (Si) substrate 1 of, for example, a (100) type lattice is LOCOS-oxidized to locally form a LOCOS SiO ₂ film 2 on the surface of the substrate 1. The LOCOS SiO ₂ film 2 functions as a stopper in the wafer polishing process described later. In this example, the LOCOS SiO ₂
About 1/2 of the film thickness of the film 2 is the film thickness of the thin film silicon layer of the SOI type MOS FET, and for example, LOCOS SiO
₂ By forming the film 2 to a film thickness of 200 nm, approximately 1
A thin film silicon layer having a thickness of 00 nm can be obtained.

Next, after forming a SiO ₂ gate oxide film 3 for the back gate, a polysilicon layer 4 is formed thereon by CVD.
To form. After that, a SiO ₂ film 5 is formed on the entire surface by CVD, and the surface is flattened by resist coating and etchback treatment. SiO ₂ film 5 after flattening
The film thickness is about 100 to 200 nm.

Next, the region 6 immediately below the base of the bipolar transistor and the region 7 immediately below the channel forming region of the MOS FET are opened, and S of these regions 6 and 7 is opened.
Remove iO ₂ . Subsequently, SiO ₂ is formed by CVD, and this is processed by RIE (reactive ion etching) to form sidewalls 8 and 9 in the opening regions 6 and 7. These sidewalls 8 and 9 are formed in the opening regions 6 and 7 so that the back gate electrode is not displaced from the base region of the bipolar transistor or the MOS channel region even if the displacement occurs during wafer bonding.
This is to give a margin to the accuracy of the opening position of.

Next, as shown in FIG. 2, polysilicon layers 10 and 11 are buried in the openings. To fill the polysilicon layers 10 and 11, first, polysilicon is entirely formed by CVD, and then the polysilicon layers 10 and 1 are formed in the openings by resist coating and etching back.
Leave 1 Alternatively, at this time, the selective CVD technique may be used. These polysilicon layers 10 and 11 function as back gate electrodes of bipolar transistors and MOS FETs. The thickness of these buried polysilicon layers 10 and 11 is about 50 to 100 nm.
Impurities are introduced into these polysilicon layers 10 and 11 so as to form a necessary conductivity type by ion implantation and annealing treatment in consideration of a work function and the like as necessary.

Next, in order to reduce the resistance of each back gate electrode, the tungsten layers 12 and 13 are buried on the polysilicon layers 10 and 11 in the opening by the selective CVD technique of tungsten (W). Then, CVD is used to form SiO
_{2 The} film 14 is formed.

Subsequently, wafer bonding and polishing steps are performed. First, a wafer (silicon substrate) for supporting the entire device is attached on the SiO ₂ film 14 in FIG. 2, and then the lower silicon substrate 1 in FIG. 2 is polished. In the wafer polishing process for polishing the silicon substrate 1, when the polishing depth reaches the LOCOS SiO ₂ film 2, the polishing is stopped. As a result, approximately half the thickness of the LOCOS SiO ₂ film 2 of silicon remains in the region between the LOCOS SiO ₂ films without being polished. FIG. 3 is a diagram in which the state after polishing is drawn upside down (the same applies to FIGS. 4 and 5).
In FIG. 3, a silicon layer (silicon substrate) 30 left after polishing the silicon substrate 1 (FIG. 2) is formed on the gate oxide film 3 in the bipolar transistor formation region and the MOS FET formation region. Reference numeral 15 is a bonded support wafer (silicon substrate).

Next, as shown in FIG. 4, a gate oxide film 16 and a polysilicon layer 17 made of SiO ₂ are formed on the silicon layer 30 in each of the base forming region of the bipolar transistor and the MOS element forming region. In order to form each gate oxide film 16 and the polysilicon layer 17, first a SiO ₂ oxide film is formed on the entire surface, and then this S
Polysilicon is formed on the iO ₂ oxide film by CVD. Next, the base formation region of the bipolar transistor and the formation region of the MOS element are covered with a resist, and using this resist as a mask, the laminated body of the SiO ₂ oxide film and the polysilicon is etched by RIE to remove the portions other than the resist. As a result, a gate oxide film 16 of SiO ₂ and a polysilicon layer 17 are formed in each of the bipolar transistor forming portion and the MOS forming portion. After that, the resist is removed.

Next, a polysilicon layer 18 is formed on the entire surface by CVD. This polysilicon layer 18 will be used together with the polysilicon layer 17 as an extraction electrode of the emitter and collector of the bipolar transistor and a gate electrode of the MOS after etching in a later step. If necessary, the polysilicon layers 17 and 18 are ion-implanted and annealed in consideration of the work function and the like, and impurities are introduced so as to have a required conductivity type. After that, the SiO ₂ film 19 is formed on the entire surface by CVD.

Next, as shown in FIG. 5, the bipolar transistor forming portion and the MOS forming portion are covered with a resist, and the polysilicon layer 18 and the SiO 2 layer are covered with this as a mask.
_{2 The} film 19 is etched by RIE.

Next, the SiO ₂ film 19, the polysilicon layers 18 and 17 and the gate oxide film 16 in the base portion of the bipolar transistor are opened by RIE. Then S
io ₂ is formed by CVD, and this is etched by RIE to form an emitter / emitter in the opening as shown in FIG.
A base separation sidewall 20 and a base / collector separation sidewall 21 are formed. In this case, the MOS FET side is LDD (Lightly Do).
In the case of a ped drain structure, ion implantation for LDD is performed before forming the sidewalls 20 and 21. In this case, the separating sidewalls 20 and 21 also simultaneously function as LDD sidewalls.

Next, a polysilicon layer is formed by CVD. An unnecessary portion of this polysilicon layer is removed in a later step, and a polysilicon electrode layer 22 is formed in the bipolar transistor forming portion and the MOS forming portion. These polysilicon electrode layers 22 function as the base electrode of the bipolar transistor and the source and drain electrodes of the MOS, respectively.

Subsequently, impurities are introduced from the polysilicon layer by ion implantation and annealing, and the subsequent heat treatment forms the emitter, base and collector of the bipolar transistor and the source and drain of the MOS. After that, the unnecessary portion of the polysilicon layer is removed.

Next, a SiO ₂ film (not shown) is formed on the entire surface by CVD, and then a contact is opened in a necessary portion,
The emitter electrode 31, the base electrode 32, and the collector electrode 3 of the bipolar transistor are formed by using an appropriate metal material.
3, and the source electrode 34, the gate electrode 35, and the drain electrode 36 of MOS are formed.

The tungsten layers 12 and 13 which will be the back gate electrodes of the bipolar transistor and the MOS are taken out from the side surface of the substrate in the direction vertical to the drawing and connected to the back gate electrode. Such a back gate electrode extracting step may be performed immediately after forming the tungsten layer, or may be performed during another appropriate step.

As described above, the double-gate structure MOS FET element having the back gate and the bipolar transistor element having the back gate, which is a feature of the present invention, are simultaneously formed in parallel on the same substrate.

When the bipolar transistor having the above structure is operated, by applying a bias voltage from the back gate electrode 37, the carriers injected from the emitter to the base side are pushed back to the center side of the base, whereby the silicon 30 and the SiO ₂ are removed. Recombination at the interface with the gate oxide film 3 is prevented.

[0034]

As described above, in the present invention, the SOI (Silicon) in which the emitter, the base and the collector are laterally arranged in parallel on one surface side of the silicon substrate.
In an on-insulator lateral bipolar transistor, a back gate electrode is provided immediately below the base (at a position facing the base). Therefore, when a bias voltage is applied from this electrode, the back gate electrode is applied from the emitter to the base side during operation. The injected carriers are pushed back toward the center of the base, which prevents recombination at the interface between the silicon substrate and the oxide film on the back gate side of SiO ₂ , and improves carrier transport efficiency to achieve a high-performance bipolar transistor function. It

Further, the back gate electrode of such a lateral bipolar transistor is formed into a fully depleted thin film SOI.
By forming in parallel with the back gate electrode of the double gate type MOS FET of the structure on the same substrate,
BiCMOS structure can be easily applied to LSI, and high performance and high accuracy BiCMOS without increasing the number of processes
The achievement of the device is achieved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view in one stage of a manufacturing process of a semiconductor device having a BiCMOS structure according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view in the next stage of the manufacturing process of the BiCMOS structure semiconductor device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view in a further next step in the manufacturing process of the BiCMOS structure semiconductor device according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view in a further next stage of the manufacturing process of the BiCMOS structure semiconductor device according to the embodiment of the present invention.

FIG. 5 is a cross-sectional view in a further next stage of the manufacturing process of the BiCMOS structure semiconductor device according to the embodiment of the present invention.

[Explanation of symbols]

1, 15 and 30 ... Silicon substrate 2 ... LOCOS oxide film 3 ... Gate oxide film 4 ... Polysilicon layer 5 ... SiO ₂ film 10 ... Poly for back gate electrode of bipolar transistor Silicon layer 11 ... Polysilicon layer for back gate electrode of MOS 12 ... Tungsten layer for back gate electrode of bipolar transistor 13 ... Tungsten layer for back gate electrode of MOS 14, 16, 19 ... SiO ₂ Films 17, 18, 22 ... Polysilicon layers 31-33 ... Emitters of bipolar transistors,
Base, collector electrodes 34 to 36 ... MOS source, gate, drain electrodes 37 ... Bipolar transistor back gate electrode 38 ... MOS back gate electrode

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (9)

[Claims] 1. A semiconductor device comprising a bipolar element having an electrode for biasing carriers at a position facing a base. 2. A semiconductor device in which a bipolar element having an electrode for biasing carriers at a position facing a base and a MOS element having a double gate thin film SOI structure are formed on the same substrate. 3. The semiconductor device according to claim 1, wherein the bipolar element is an SOI lateral bipolar transistor. 4. A method of manufacturing a semiconductor device in which a bipolar element and a MOS element having a double-gate thin film SOI structure are mixedly mounted on the same substrate, wherein the bipolar element is formed in parallel with the step of forming the back gate electrode of the MOS element. A method of manufacturing a semiconductor device, characterized in that an electrode for carrier bias is formed at a position facing the base of (1). 5. A method of manufacturing a semiconductor device in which a bipolar element and a MOS element having a double-gate thin film SOI structure are mixedly mounted on the same substrate, wherein the bipolar element is formed in parallel with the step of forming the back gate electrode of the MOS element. In the semiconductor device, an electrode for carrier bias is formed at a position facing the base of the semiconductor device, and an emitter, a collector contact, and a gate electrode of a MOS device are formed by the same electrically conductive film. Production method. 6. A method of manufacturing a semiconductor device in which a bipolar element and a MOS element having a double-gate thin film SOI structure are mixedly mounted on the same substrate, wherein the bipolar element is formed in parallel with the step of forming the back gate electrode of the MOS element. An electrode for carrier bias is formed at a position opposite to the base of the semiconductor device, and the base of the bipolar device and the source and drain of the MOS device are formed by diffusion from the same electrically conductive film. Method. 7. A method of manufacturing a semiconductor device in which a bipolar element and a MOS element having a double-gate thin film SOI structure are mixedly mounted on the same substrate, wherein the bipolar element is formed in parallel with the back gate electrode forming step of the MOS element. An electrode for carrier bias is formed at a position opposite to the base of, and the same electric conductive film forms the emitter and collector contact of the bipolar element and the gate electrode of the MOS element, and from the same electric conductive film. A method of manufacturing a semiconductor device, characterized in that the base of a bipolar element and the source and drain of a MOS element are formed by diffusion of the element. 8. A step of forming a back gate electrode of the MOS element and an electrode for carrier bias of the bipolar element on a silicon substrate, and then laminating a substrate for supporting the entire device on the electrode formation surface side. 7. The method of manufacturing a semiconductor device according to claim 4, 5 or 6, further comprising: polishing the silicon substrate. 9. The method of manufacturing a semiconductor device according to claim 5, wherein the electrically conductive film is formed of a polysilicon layer or a laminated film including a polysilicon layer.