JPH0738079A - Hot carrier semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a hot carrier semiconductor device, R having different peak voltage V _P and valley voltage V _V on the same substrate.
A HET or RTB can be formed easily and easily, and an optimum element can be selected from those elements to configure a circuit. [Structure] Collector layer 43 and base layer 4 on substrate 41
5, the emitter layer 47 and the like are formed, and the peak voltage V is obtained by forming the emitter electrode 49L of ohmic contact and the emitter electrode 49H of Schottky contact.
First RHET40 with different _{P and} valley voltage V _V
L and the second RHET 40H are incorporated and appropriately selected to form a logic circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a hot carrier semiconductor device which is a semiconductor device utilizing the quantum effect.

[0002] Currently, research on semiconductor devices utilizing the quantum effect is active, and among them, hot electron transistors (hot electron transistors).
Resonant tunneling barrier as an emitter barrier in a system: HET
Resonant tunneling hot electron transistor using nneling barrier (RTB)
electron transistor (RHET)
Since it has a negative conductance characteristic, it is being applied to various circuits.

However, RHET has various problems that need to be improved in order to be universally used. For example, it is required to reduce power consumption and improve operating margin.

[0004]

2. Description of the Related Art FIG. 11 is a circuit diagram of a main part of a NOR gate or an XNOR gate using an RHET having an SE (single emitter) structure in which a base electrode is directly drawn from a base layer.

In the figure, 1 is RHET, 2 is input resistance, 3 is input resistance, 4 is base bias resistance, 5 is load resistance, 6 is input end, 7 is input end, 8 is output end, 9 Is V
_DD supply line 10 indicates a ground line. Incidentally, N
The difference between the OR gate and the XNOR gate is that the circuit constants are different, and they are the same in terms of circuit configuration.

FIG. 12 is a diagram showing input / output characteristics for explaining the operation of the NOR gate or the XNOR gate shown in FIG. 11. The horizontal axis shows the base-emitter voltage V _BE.
And the vertical axis represents the collector current I _C.

[0007] In figure shows (A) the properties of the NOR gate, (B) the characteristics of the XNOR gate, V _P is the peak voltage, V _V Valley voltages, respectively. The slanted solid line in the figure is the load line for the base.

In this case, the peak voltage V _P indicates the base-emitter voltage V _{BE at} which the collector current I _C reaches its peak, and similarly, the valley voltage V _V is the base-emitter voltage at which the collector current I _C reaches the valley. It refers to the voltage V _BE and does not mean that any voltage has a peak or valley.

[0009]

Generally, in an integrated circuit device composed of RHET, all RHETs having the same characteristics, that is,
The peak voltage V _P and the valley voltage V _V are the same and are used to form a NOR gate and an XNOR.

When a NOR gate is constructed using such RHET, the input resistance value must be sufficiently higher than that of the XNOR gate in order to prevent the operating point of RHET from exceeding the peak voltage V _P. I won't.

Therefore, the operating speed is lowered due to the increase of the CR time constant of the NOR gate, or the size of the resistance layer pattern needs to be extremely changed between the NOR gate and the XNOR gate. There is a problem such as being severely restricted in the design and placement of.

[0012] On the other hand, the ME (multi) is obtained by taking out the electrode, which is substantially the base electrode, through the emitter layer.
RHET with an emitter structure (if necessary, Japanese Patent Application No. 4-
188382), NOR gate and X
The NOR gate can be constructed relatively easily, but there is a problem in constructing a state holding circuit using the negative resistance characteristic of the emitter current of RHET.

FIG. 13 is a main part circuit diagram showing a state holding circuit using the RHET of the ME structure. In the figure, 22 is an input resistance, 23 is an input resistance, 24 is a base bias resistance, 25 is a load resistance, 26 is an input end, 27 is an input end, 2
8 is an output terminal, 29 is a V _DD supply line, 30 is a ground line, 31 is a RHET with a peak voltage V _P = 0.9 [V], and 31 'is a RHET with a peak voltage V _P = 0.9 [V]. Shown respectively.

In this state holding circuit, the input is (0, 1).
Alternatively, when it is (1, 0), it becomes a bistable state, and the output before the state change can be held.

By the way, in the illustrated RHET 31, when the input is (1, 1), the operating point is the peak voltage V _P.
The junction area of the emitter and the base is smaller than that of RHET, that is, the peak current is small.
For ET, that is, RHET31 ', the input is (1,
Even in the case of 1), it is necessary to make the RHET having a large emitter-base junction area so that the operating point, that is, the intersection of the load line and the characteristic line of RHET does not reach the peak voltage V _P.

FIG. 14 is a diagram showing input / output characteristics for explaining the operation of the state holding circuit shown in FIG. 13. The horizontal axis represents the base-emitter voltage V _BE , and the vertical axis represents the voltage. Each collector current I _C is taken. The same symbols as those used in FIG. 12 represent the same parts or have the same meanings.

As is apparent from the figure, in this case, the peak voltage V _PH is 0.9 [V], and S seen in FIG.
NOR gate or XNOR using E-structure RHET
Compared with the peak voltage V _{P of the} gate being 0.6 [V], it is about 1.5 times. This is because in the RHET having the ME structure, two RTBs are inserted between the emitter and the base.

As a result, RHET 31 and 31 'and ME
In the state holding circuit using the RHET having the structure, it is necessary to increase the power supply voltage, and it is not possible to match with other circuits.

Generally, in order to reduce power consumption in an integrated circuit device using RHET, a circuit using RHET as an active element and RTB as a load element is effective.

FIG. 15 shows XNO using RHET and RTB.
FIG. 3 is a circuit diagram of a main part of an R gate (if necessary, Japanese Patent Application No. 4-29).
No. 2715), the same symbols as those used in FIG. 11 represent the same parts or have the same meanings.

In the figure, reference numeral 11 indicates a load element using an RTB. Here, the load element 11 is RHET1.
The RHET having the same structure as the above is diode-connected and its RTB is used.

FIG. 16 is a diagram for explaining the operation of the XNOR gate shown in FIG. 15, which is shown in FIG. 12 or FIG.
The same symbols as those used in represent the same parts or have the same meanings.

In the figure, (A) is an input / output characteristic, and (B) is
Shows V _CE -I _C characteristic, V _ON is operating point RHET is turned on (low level), V _OFF is RHET operating point to be turned off (high level), respectively. The input / output characteristic (A) relates to the normally connected RHET, that is, RHET1. Also, the characteristic line of the load element 11 connected to the diode is almost the same, but the input / output characteristic is
Must be read as current characteristics.

As can be seen from the input / output characteristic (A) in the figure,
The peak voltage V _P in normal RHET is 0.6 [V]
The valley voltage V _V is 1.2 [V], and therefore,
When V _BE > 1.2 [V], the collector current I _C becomes large.

The peak voltage V _P is 0.6 [V] because, for example, in RHET based on InGaAs, the energy difference between the Γ valley and the L valley is about 0.55 [eV]. Therefore, it is a value that is physically determined.

[0026] where it left the, in the V _CE -I _C characteristic, the state of the power supply voltage to 2 V, the operating point V _ON when the RHET is on becomes 1.8 [V] degree , R
Since the characteristics of TB exceed the valley, the current naturally rises and cannot be made sufficiently small.

To solve such a problem, it is necessary to lower the power supply voltage. However, in such a case, the operating margin of the gate is lost, that is, the difference between the high level and the low level becomes small, which is not practical.

In the present invention, the peak voltage V _P is formed on the same substrate.
Different RHETs or RTBs can be formed easily and easily, and an optimum element can be selected from these elements to configure a circuit.

[0029]

FIG. 1 is a diagram for explaining input / output characteristics in a hot carrier semiconductor device for explaining the principle of the present invention, and FIG. 12, FIG. 13, FIG.
The same symbols as those used in 6 represent the same parts or have the same meanings.

In the figure, RT1 is an input / output characteristic line relating to the first RHET in which both the peak voltage V _P and the valley voltage V _V are low, and RT2 is the peak voltage V _P and the valley voltage V _V.
Shows the input / output characteristic lines for the second RHET, both of which are high.

To construct various logic circuits in use, the peak voltage V _P for the first RHET is set to, for example, about 0.6.
By setting it to about [V] and setting the peak voltage V _P for the second RHET to, for example, about 0.9 [V], it is possible to cope with a fairly wide range.

FIG. 2 shows an X constructed using the first RHET.
6 is a circuit diagram of a main part for explaining a NOR gate. FIG.

In the figure, 21 is RHET, 22 is input resistance, 23 is input resistance, 24 is base bias resistance,
Reference numeral 25 is a load resistance, 26 is an input end, 27 is an input end, 28 is an output end, 29 is a _VDD supply line, and 30 is a ground line.

The RHET 21 shown in the figure, as described above,
For example, the XNO having a low peak voltage V _P of about 0.6 [V] and performing an appropriate operation depending on the peak voltage V _P.
It is possible to configure an R gate.

FIG. 3 shows an N constructed using the second RHET.
FIG. 3 is a circuit diagram of an essential part for explaining an OR gate, and the same symbols as those used in FIG. 2 represent the same parts or have the same meanings. In the figure, 31 indicates RHET.

The RHET 31 shown in the figure is, as described above,
It has a high peak voltage V _{P of} , for example, about 0.9 [V], and a NOR for performing an appropriate operation depending on the peak voltage V _P.
It is possible to configure the gate.

FIG. 4 is a diagram for explaining the input / output characteristics of the XNOR gate and NOR gate shown in FIGS. 2 and 3, and the horizontal axis represents the base-emitter voltage V.
_BE is taken, and the vertical axis is the collector current I _C. The same symbols as those used in FIG. 1 represent the same parts or have the same meanings.

In the figure, (A) is a characteristic relating to the XNOR gate, (B) is a characteristic relating to the NOR gate, and L _B1,
L _{B2 and} L _B3 respectively indicate load lines for the base.

As is clear from the figure, both the XNOR gate and the NOR gate can operate in a well-balanced manner, and what is required to construct both such well-matched gates is the RHET21. It suffices to select which of RHET31 and RHET31.

Therefore, it is not necessary to change the constants of the input resistance 22, the input resistance 23, the base bias resistance 24, the load resistance 25, etc., and the XNOR gate and the NOR gate may have the same constants. Also, RHE
It is not necessary to change the sizes of T21 and RHET31.

FIG. 5 is a main part circuit diagram for explaining a state holding circuit constituted by using the first RHET and the second RHET. The same symbols as those used in FIGS. 2 and 3 are given. They represent the same part or have the same meaning.

In the figure, 32 indicates a resistance.

As shown, the RHET used as a resonant tunneling diode has a peak voltage V _P
Low RHET, that is, RHET that is the first RHET
21 is used, the RHET for voltage amplification has a peak voltage V _P
High RHET, that is, RHET that is the second RHET
31 is used.

As described above, R having different peak voltages V _P
By using HET21 and RHET31, the objects can be achieved while using those having the same bonding area. In this way, if the junction area is the same, the influence of the parasitic resistance is the same for all RHETs, so that the ease of circuit design and the uniformity of operating characteristics are improved.

Incidentally, in the conventional state holding circuit shown in FIG. 13, RHET31 and RHET31 'have the same characteristics, that is, the peak voltage V _P and the valley voltage V _V are the same. In order to make the circuit function, the resistors 22 and 23 are connected to other NOR circuits and XNO.
If the R circuit is changed or if it is still insufficient, the RHET has a larger junction area than the RHET31.
Is used as RHET31 '.

However, when manufacturing a high-density integrated circuit device, when miniaturizing to the limit of the minimum size in processing, it is desirable that the junction areas of the transistors are all the same.

Further, when transistors having different junction areas are used, there is a problem that the peak voltage V _P and the valley voltage V _V cannot be controlled as designed due to the influence of the base resistance and the emitter resistance. However, in the present invention, the peak voltage V
By appropriately selecting _P and the valley voltage V _V , RHET having the same junction area can be used, and such a problem does not occur.

As is clear from the above description, RH
By short-circuiting the base and collector in ET to form a so-called diode connection, and using the RTB, it is possible to configure various characteristic logic circuits.

FIG. 6 shows an XNO in which the first RHET is an active element and the second RHET is a load element (RTB).
FIG. 17 is a diagram showing characteristics relating to an R gate, and the same symbols as those used in FIG. 16 represent the same parts or have the same meanings. In the figure, (A) shows the voltage-current characteristic of RTB, and (B) shows the I _C -V _CE characteristic.

Here, the voltage-current characteristic (A) is the voltage-current of RTB in the diode-connected device in which the base and collector of the second RHET, which is RHET having a high peak voltage V _P, is short-circuited. Characteristic, this element is XN
Used as load of OR gate. Here, the second RHET having a peak voltage V _P of 0.9 [V] is used.

As the active element, the peak voltage V _P
The first RHET which is a low RHET is used.
Here, the first RHET having a peak voltage V _P of 0.6 [V] is used.

FIG. 7 shows a NOR in which the second RHET is an active element and the second RHET is a load element (RTB).
FIG. 17 is a diagram showing characteristics regarding gates, and FIG.
The same symbols as those used in represent the same parts or have the same meanings. In the figure, (A) is RTB
Voltage - current characteristic shows (B), respectively the I _C -V _CE characteristics.

Here, the voltage-current characteristic (A) is XNO.
RHET having a high peak voltage V _P as in the case of the R gate
The voltage-current characteristics of the RTB in a diode-connected device in which the base and collector of the second RHET are short-circuited, and this device is used as the load of the NOR gate. Here, the second RHET having a peak voltage V _P of 0.9 [V] is used.

As the active element, the second RHE, which is RHET having a high peak voltage V _P, is used as in the load.
T is used.

The operation of the XNOR gate to which the principle of the present invention is applied will be described with reference to FIG.

If the two inputs are (0,0), then RH
The active element that is ET is off, the load element that is RTB is near the rising edge, and the output is high level (“1”)
Becomes

Two inputs are (0,1) or (1,0)
, The active element (RHET) is turned on and the load element (RTB) enters the valley region, so that the output becomes low level (“0”).

When the two inputs are (1,1), the active element (RHET) enters the valley region and turns off, and the load element (RTB) rises, so that the output goes high again.
At the level (“1”), the XNOR gate operates.

The operation of the NOR gate to which the principle of the present invention is applied will be described with reference to FIG.

If the two inputs are (0,0), then
The output is high level (“1”) as in the XNOR gate.
Becomes

Two inputs are (0,1) or (1,0)
, The output is low, similar to the XNOR gate.
It becomes the level (“0”).

When the two inputs are (1,1), the peak voltage V _P of the active device (RHET) is high, so that the valley region is not entered, and therefore the output is at the low level (“0”).
Then, the operation of the NOR gate is performed.

In both the XNOR gate and the NOR gate, the current at the operating point is small, so that the power consumption is small.

As is clear from the above, XN
In the OR gate, an RHET having a low peak voltage V _P is used as an active element, and a load element (RTB) is used.
By using a RHET having a high peak voltage V _P , the valley voltage V _V of the load element, that is, RTB is increased to improve the voltage gain.

The NOR gate having a high RHET peak voltage V _P is used so as not to enter the valley region even if the input is (1, 1).

From the above, in the hot carrier semiconductor device according to the present invention, (1) the first resonance tunneling with different peak voltage V _P and valley voltage V _V on the same substrate. A transistor and a second resonant tunneling transistor are formed, or

(2) In the above (1), the emitter electrode in the first resonant tunneling transistor is made into an ohmic contact, and the emitter electrode in the second resonant tunneling transistor is Schottky.
It is characterized in that the peak voltage V _{P and the} valley voltage V _V are made different by making the contacts, or

(3) In the above (1), the resonance tunneling in the first resonance tunneling transistor.
Resonant tunneling in the second resonant tunneling transistor with respect to the emitter barrier layer consisting of the barrier
The peak voltage V _{P and the} valley voltage V _V can be changed by changing the thickness of the well layer in the emitter / barrier layer made of barrier.
Is different from the above, or

(4) In the above (1), the base electrode in the second resonant tunneling transistor is ohmic-contacted with the emitter layer, and two resonant tunneling barriers are interposed between the base electrode and the emitter electrode. Or

(5) The first resonant tunneling transistor and the second resonant tunneling transistor formed on the same substrate and having different peak voltage V _P and valley voltage V _V are used as active elements and have the same constant. It is characterized in that an XNOR gate and a NOR gate configured by using resistors and driven by the same power source are incorporated, or

(6) A state-holding transistor in which the first resonance tunneling transistor and the second resonance tunneling transistor formed on the same substrate and having different peak voltage V _P and valley voltage V _V are diode-connected. And a state holding circuit used as a voltage amplifying transistor, or

(7) In the above (4), the XNOR is used as a load element by using the first resonant tunneling transistor as an active element and shorting the base and collector of the second resonant tunneling transistor. Characterized in that the gate is incorporated, or

(8) In the above item (4), the second resonant tunneling transistor is used as an active element, and the base and collector of the second resonant tunneling transistor are short-circuited to serve as a load element. It is characterized in that a gate is incorporated.

[0074]

By adopting the above means, it is possible to construct a logic circuit which consumes less power, has a large voltage gain, and has a sufficient operation margin, and moreover, enables the RHE.
In order to form T, that is, RHET having different peak voltage V _P and valley voltage V _V on the same substrate, no special technique is required, and it is easy to apply the technique that has been widely used in the past. Can be created.

[0075]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 8 is a side sectional view showing a hot carrier semiconductor device for explaining a first embodiment of the present invention.

In the figure, 40L is a first RHET having a low peak voltage V _P , 40H is a second RHET having a high peak voltage V _P , 41 is a substrate, 42 is a buffer layer, 43 is a collector layer, and 44 is Collector / barrier layer, 45 is base layer, 46 is emitter barrier layer made of RTB, 47 is emitter layer, 48 is emitter contact layer, 49L is emitter electrode in first RHET, and 49H is second RHET. , 51 is a base electrode, and 5 is a base electrode.
Reference numerals 2 respectively indicate collector electrodes.

The main data regarding each part in the illustrated first embodiment will be illustrated as follows. (1) About substrate 41 Material: Semi-insulating InP (2) About buffer layer 42 Material: i-InAlAs Thickness: 200 [nm]

(3) Regarding collector layer 43 Material: n ⁺ -InGaAs Impurity concentration: 5 × 10 ¹⁸ [cm ⁻³ ] Thickness: 300 [nm] (4) About collector / barrier layer 44 Material: i-In ( AlGa) As Thickness: 200 [nm]

(5) About the base layer 45 Material: n-InGaAs Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ] Thickness: 30 [nm] (6) About the emitter / barrier layer 46 made of RTB Barrier layer Material: i-InAlAs Thickness: 3.0 [nm] Well layer Material: i-InGaAs Thickness: 3.0 [nm]

(7) Regarding Emitter Layer 47 Material: n-InGaAs Impurity Concentration: 5 × 10 ¹⁹ [cm ⁻³ ] Thickness: 200 [nm] (8) Regarding Emitter Contact Layer 48 Material: n-InAlAs Impurity Concentration : 1 × 10 ¹⁷ [cm ^-3 ] Thickness: 100 [nm]

(9) Regarding emitter electrodes 49L and 49H Material: Cu / Au Thickness: 20 [nm] / 300 [nm]

Second RHET40H in the first embodiment
Since the emitter electrode 49H is formed on the emitter contact layer 48 made of n-InAlAs and is in Schottky contact, the second RHET 40H rises as compared with the first RHET 40L having the normal emitter electrode 49L. The voltage is about 0.6 [V] higher.

[0083] Thus, lowering the peak voltage V _P of the first RHET40L, and, the peak voltage V _P of the second RHET40H it is possible to increase.

FIG. 9 is a cutaway side view of an essential part showing a hot carrier semiconductor device for explaining the second embodiment of the present invention. The symbols used in FIG. 8 are the same as those used in FIG. Represent or have the same meaning.

In the figure, 49 is the first RHET 40L.
And an emitter electrode in the second RHET40H, 53
Shows the emitter-barrier layers of RTB in the second RHET 40H, respectively.

Second RHET40H in Second Embodiment
The emitter barrier layer 53 made of RTB in the first RHET 40L is the emitter barrier layer 53 made of RTB in the first RHET 40L.
It is different from the barrier layer 46.

That is, in the second embodiment, the emitter / barrier layer 46 is formed on the entire surface, and then only the emitter / barrier layer 46 in the second RHET 40H is selectively removed. Then, an emitter / barrier layer 53 is selectively formed.

Therefore, the emitter / barrier layer 53 is free from the restriction of the emitter / barrier layer 46, and its structure can be set arbitrarily. Incidentally, in the RTB, when the well width (thickness of the well layer) is narrowed, the peak voltage V _P is high, and when it is wide, the peak voltage V _P is low.

FIG. 10 is a sectional side view of a main part of a hot carrier semiconductor device for explaining a third embodiment of the present invention. The same symbols as those used in FIGS. 8 and 9 are given. They represent the same part or have the same meaning.

As is clear from the figure, the second RHET4
The base electrode 51 at 0H is formed on the surface of the emitter layer 47 and is in ohmic contact. Therefore, the base electrode 51 and the base layer 45 are in contact with each other.
An emitter / barrier layer 46 of B is interposed.

Therefore, the second RHET 40H has a structure in which two RTBs are interposed between the emitter and the base, and the rise voltage, the peak voltage V _P , and the valley voltage V _V are all covered. It is about 1.5 times that of the first RHET 40L. The second RHET in this case
It can be considered that 40H has an ME structure.

[0092]

In the hot carrier semiconductor device according to the present invention, the first resonant tunneling transistor and the second resonant tunneling transistor having different peak voltage V _P and valley voltage V _V are formed on the same substrate. And a transistor are formed.

By adopting the above configuration, it is possible to construct a logic circuit with low power consumption, large voltage gain, and sufficient operating margin, and moreover, an RHE that enables it.
In order to form T, that is, RHET having different peak voltage V _P and valley voltage V _V on the same substrate, no special technique is required, and it is easy to apply the technique that has been widely used in the past. Can be created.

[Brief description of drawings]

FIG. 1 is a diagram for explaining input / output characteristics in a hot carrier semiconductor device for explaining the principle of the present invention.

FIG. 2 is a circuit diagram of a main part for explaining an XNOR gate configured using a first RHET.

FIG. 3 is a main part circuit diagram for explaining a NOR gate configured using a second RHET.

FIG. 4 is an XNOR gate and N as seen in FIGS. 2 and 3.
It is a diagram for explaining the input / output characteristics regarding the OR gate.

FIG. 5 is a circuit diagram of a main part for explaining a state holding circuit configured by using a first RHET and a second RHET.

FIG. 6 is a diagram showing characteristics relating to an XNOR gate in which the first RHET is an active element and the second RHET is a load element (RTB).

FIG. 7 is a diagram showing characteristics relating to a NOR gate in which a second RHET is an active element and the second RHET is a load element (RTB).

FIG. 8 is a cutaway side view of a main part of a hot carrier semiconductor device for explaining a first embodiment of the present invention.

FIG. 9 is a side sectional view showing a main part of a hot carrier semiconductor device for explaining a second embodiment of the present invention.

FIG. 10 is a side sectional view showing a main part of a hot carrier semiconductor device for explaining a third embodiment of the present invention.

FIG. 11 is a circuit diagram of a main part of a NOR gate or an XNOR gate using an RHET having an SE (single emitter) structure.

FIG. 12 is a NOR gate or XNO as seen in FIG.
It is a diagram showing the input-output characteristic for explaining the operation of the R gate.

FIG. 13 is a principal part circuit diagram showing a state holding circuit using RHET of ME structure.

14 is a diagram showing input / output characteristics for explaining the operation of the state holding circuit shown in FIG.

FIG. 15 is a circuit diagram of a main part of an XNOR gate using RHET and RTB.

16 is a diagram for explaining the operation of the XNOR gate seen in FIG.

[Explanation of symbols]

40L peak voltage V _P is low first RHET 40H peak voltage V _P is higher second RHET 41 substrate 42 the buffer layer 43 the collector layer 44 collector-barrier layer 45 base layer 46 emitter-barrier layer 47 emitter layer made of RTB 48 Emitter contact layer 49L Emitter electrode in first RHET 49H Emitter electrode in second RHET 51 Base electrode 52 Collector electrode 49 First RHET 40L and second RHET 40H
53. Emitter barrier layer consisting of RTB in the second RHET40H

Claims (8)

[Claims] 1. A hot resonance characterized in that a first resonant tunneling transistor and a second resonant tunneling transistor having different peak voltage V _P and valley voltage V _V are formed on the same substrate. Carrier semiconductor device. 2. The peak voltage V _{P and the} valley voltage are set by making the emitter electrode of the first resonance tunneling transistor an ohmic contact and making the emitter electrode of the second resonance tunneling transistor a Schottky contact. 2. The hot carrier semiconductor device according to claim 1, wherein the voltage V _V is different. 3. An emitter barrier layer comprising a resonant tunneling barrier in a first resonant tunneling transistor versus an emitter barrier layer comprising a resonant tunneling barrier in a second resonant tunneling transistor. 2. The hot carrier semiconductor device according to claim 1, wherein the peak voltage V _{P and the} valley voltage V _V are made different by changing the thickness of the well layer. 4. A second resonance tunneling transistor, wherein the base electrode of the second resonance tunneling transistor is in ohmic contact with the emitter layer, and two resonance tunneling barriers are interposed between the base electrode and the emitter electrode. 1. The hot carrier semiconductor device according to 1. 5. A first resonance tunneling device formed on the same substrate and having different peak voltage V _P and valley voltage V _V.
A hot resonant circuit comprising a transistor and a second resonant tunneling transistor as active elements, an XNOR gate and a NOR gate which are configured by using resistors of the same constant and are driven by using the same power source. Carrier semiconductor device. 6. A first resonant tunneling device formed on the same substrate and having different peak voltage V _P and valley voltage V _V.
A hot carrier semiconductor device comprising a transistor and a second resonance tunneling transistor as a diode-connected state-holding transistor and a state-holding circuit used as a voltage amplification transistor. 7. An XNOR gate is used, wherein the first resonant tunneling transistor is an active element and the base and collector of the second resonant tunneling transistor are short-circuited to serve as a load element. The hot carrier semiconductor device according to claim 4. 8. A NOR gate, wherein the second resonant tunneling transistor serves as an active element and a base element and a collector of the second resonant tunneling transistor are short-circuited to serve as a load element. The hot carrier semiconductor device according to claim 4.