JPH0738579B2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH0738579B2
JPH0738579B2 JP62110540A JP11054087A JPH0738579B2 JP H0738579 B2 JPH0738579 B2 JP H0738579B2 JP 62110540 A JP62110540 A JP 62110540A JP 11054087 A JP11054087 A JP 11054087A JP H0738579 B2 JPH0738579 B2 JP H0738579B2
Authority
JP
Japan
Prior art keywords
mosfet
gate
source
terminal
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62110540A
Other languages
Japanese (ja)
Other versions
JPS63276322A (en
Inventor
廣 大和田
良孝 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62110540A priority Critical patent/JPH0738579B2/en
Publication of JPS63276322A publication Critical patent/JPS63276322A/en
Publication of JPH0738579B2 publication Critical patent/JPH0738579B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に係り、特に制御部と主駆動部が電
気的に絶縁された電気結合方式の半導体装置に関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an electrically coupled semiconductor device in which a controller and a main driver are electrically insulated.

〔従来の技術〕[Conventional technology]

入出力間が絶縁され、電圧がフローテイング状態でも動
作が可能な主駆動部として、ホトカプラを使用した装置
がある。しかしこの装置はモノリシツク化ができない。
モノリシツク化が可能な半導体装置としては特公昭61−
7665号公報記載の様に、主駆動部にバイポーラ素子を使
用し、そのスイツチ素子としてＰ及びＮチヤネルMOSFET
をバイポーラ素子のベース、コレクタ間に並列に接続し
た半導体装置があるが、スイツチ素子の制御方式が記載
されておらず、主駆動部の制御については配慮されてい
なかつた。There is a device that uses a photocoupler as a main drive unit that is isolated from the input and output and that can operate even when the voltage is floating. However, this device cannot be monolithic.
As a semiconductor device that can be monolithic, Japanese Patent Publication No. Sho 61-
As described in Japanese Patent No. 7665, a bipolar element is used in the main driving part, and P and N channel MOSFETs are used as the switching element.
There is a semiconductor device in which the bipolar element is connected in parallel between the base and collector of the bipolar element, but the control method of the switch element is not described, and the control of the main drive section was not considered.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上記従来技術は、主駆動部をオン・オフ駆動する制御方
式には配慮がなされておらず、主駆動部を制御する為に
は問題があつた。The above-mentioned prior art does not consider the control method for driving the main drive unit on and off, and there is a problem in controlling the main drive unit.

本発明の目的はモノリシツク構造で、且つ主駆動部と制
御部を直流的に絶縁せしめ得るとともに、主駆動部の電
位がフローテイング状態にあつても、オン・オフ制御が
可能な半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device which has a monolithic structure and can insulate a main drive unit and a control unit from each other in a direct current manner, and can perform on / off control even when the potential of the main drive unit is in a floating state. To do.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的を達成するために、本発明の半導体装置は次の
ような構成を持っている。主駆動部に、一対の主端子と
制御端子を備えるオン・オフ可能な３端子素子を有し、
この３端子素子を駆動するために、一方の主端子と制御
端子の間に、ｎチャンネル及びｐチャンネルの３端子素
子駆動用のMOSFETのソース及びドレインを接続する。３
端素子駆動用のMOSFETの各々が、ゲートの制御のため
に、電源と、複数のMOSFETから構成されるフリップフロ
ップ回路とを備える。ここで、各電源は電位が異なって
いる。そして、各フリップフロップ回路は、３端子素子
駆動用のMOSFETのソースと電源とに接続されるともに、
各フリップフロップ回路の出力は、３端子素子駆動用の
MOSFETのゲートに接続される。In order to achieve the above object, the semiconductor device of the present invention has the following configuration. The main drive unit has a three-terminal element that can be turned on and off, including a pair of main terminals and control terminals,
In order to drive the three-terminal element, the source and drain of the n-channel and p-channel MOSFET for driving the three-terminal element are connected between one main terminal and the control terminal. Three
Each of the end element driving MOSFETs includes a power supply and a flip-flop circuit including a plurality of MOSFETs for controlling the gate. Here, the power supplies have different potentials. Each flip-flop circuit is connected to the source of the MOSFET for driving the three-terminal element and the power supply,
The output of each flip-flop circuit is for driving a three-terminal element.
Connected to MOSFET gate.

〔作用〕[Action]

上記のようなフリップフロップ回路は、３端子素子駆動
用のMOSFETのゲートに対し、そのMOSFETのソース電位を
出力するとともに、ゲートの制御のための電源の電位を
出力する。３端素子駆動用のMOSFETは、出力がソース電
位のときにはオフし、電源電位のときにはオンする。こ
こで、各電源は電位が異なっているので、３端子素子の
主端子の電位がフローティング状態であっても、ｎチャ
ンネル及びｐチャンネルのMOSFETの少なくとも一方は十
分大きなゲート電位を与えられて確実にオンすることが
できる。また、３端子素子駆動用のMOSFETをオフする際
には、ｎチャンネル及びｐチャンネルのMOSFETのどちら
においても、ゲートとソースが同電位になるので、ノイ
ズなどの影響を受けることがなく、確実にオフすること
ができる。従って、本発明におけるフリップフロップを
用いた制御回路によれば、３端子素子の主端子の電位が
フローティング状態であっても、３端子素子を確実にオ
ン・オフ駆動できる。The flip-flop circuit as described above outputs the source potential of the MOSFET to the gate of the MOSFET for driving the three-terminal element, and also outputs the potential of the power supply for controlling the gate. The MOSFET for driving the three-terminal element is turned off when the output is at the source potential, and is turned on when the output is at the power source potential. Here, since the power supplies have different potentials, even if the potential of the main terminal of the three-terminal element is in a floating state, at least one of the n-channel and p-channel MOSFETs is given a sufficiently large gate potential to ensure the potential. Can be turned on. Further, when turning off the MOSFET for driving the three-terminal element, the gate and the source have the same potential in both the n-channel MOSFET and the p-channel MOSFET, so there is no influence of noise, etc. Can be turned off. Therefore, according to the control circuit using the flip-flop of the present invention, the three-terminal element can be reliably driven on / off even if the potential of the main terminal of the three-terminal element is in the floating state.

〔実施例〕〔Example〕

以下、本発明の一実施例を第１図により説明する。１は
主制御部の３端子半導体スイツチング素子であり、本実
施例の場合はnpnトランジスタである。2,3,4,5,6,7はｎ
チヤネルMOSFET、8,9,10,11,12はＰチヤネルMOSFET、1
4,15はダイオード、16,17は電源、G1は入力信号用端子
である。An embodiment of the present invention will be described below with reference to FIG. Reference numeral 1 denotes a three-terminal semiconductor switching element of the main control unit, which is an npn transistor in this embodiment. 2,3,4,5,6,7 is n
Channel MOSFET, 8,9,10,11,12 are P channel MOSFET, 1
4, 15 are diodes, 16 and 17 are power supplies, and G 1 is an input signal terminal.

トランジスタ１が順バイアス時の制御を第１図で説明す
る。入力信号端子G1に電源17と同電位の高電圧VHを入力
すると、MOSFET12のゲートとソース電位は同電位となる
のでオフ状態であるが、MOSFET7はオンし、MOSFET11の
ゲートには電源16の電圧が印加され、ソースには電源17
が印加されているのでオン状態となる。この結果MOSFET
3のゲートには電源17が印加され、ソースはトランジス
タ１のベースに接続されているのでMOSFET3もオンとな
る。一方、MOSFET4のゲートとソースは同電位となるの
でMOSFET4はオフ状態である。この結果トランジスタ１
のコレクタ接合を短絡する様に接続されているMOSFET2
のソースとゲートG2は同電位となるので、MOSFET2はオ
フ状態であり、トランジスタ１のベースに電流が供給さ
れない状態にある。The control when the transistor 1 is forward biased will be described with reference to FIG. When a high voltage V H having the same potential as that of the power supply 17 is input to the input signal terminal G 1 , the gate and source potentials of the MOSFET 12 become the same potential, so the MOSFET 7 is turned on, and the gate of the MOSFET 11 is turned on and the power supply 16 Voltage is applied to the source of the power supply 17
Is applied, it is turned on. This results in a MOSFET
The power supply 17 is applied to the gate of 3 and the source is connected to the base of the transistor 1, so that the MOSFET 3 is also turned on. On the other hand, since the gate and the source of the MOSFET 4 have the same potential, the MOSFET 4 is in the off state. This results in transistor 1
MOSFET2 connected to short the collector junction of
Since the source and the gate G 2 of the transistor have the same potential, the MOSFET 2 is in the OFF state and the base of the transistor 1 is not supplied with current.

又、MOSFET5のソースとゲートは同電位であるのでオフ
状態、MOSFET6のゲートには入力信号すなわち電源17と
同じ電圧VHが印加され、ソースは電源16の電位なのでオ
ン状態となる。従つて、MOSFET10のゲートには電源16が
印加され、ソースはトランジスタ１のコレクタに接続さ
れているのでオン状態となり、MOSFET9及びMOSFET8のゲ
ートG3にはそれぞれソース電位と同電位となるのでオフ
状態であり、トランジスタ１のベースに電流が供給でき
ない。このように入力端子G1に電源17と同電位の電圧VH
が入力された場合はトランジスタ１はオフの状態であ
る。Further, since the source and the gate of the MOSFET 5 are at the same potential, the MOSFET 5 is in the OFF state, and the gate of the MOSFET 6 is in the ON state because the input signal, that is, the same voltage V H as the power source 17 is applied and the source is the potential of the power source 16. Therefore, the power supply 16 is applied to the gate of the MOSFET 10 and the source is connected to the collector of the transistor 1 so that it is turned on, and the gates G 3 of the MOSFET 9 and the MOSFET 8 are at the same potential as the source potential, so that they are off. Therefore, current cannot be supplied to the base of the transistor 1. Voltage V H at the same potential thus to the input terminal G 1 and the power supply 17
Is input, the transistor 1 is off.

次に入力端子に電源16と同電位の低電圧VLを入力する
と、MOSFET13がオンとなり、MOSFET11のソースとゲート
は同電位となりオフ状態となる。MOSFET12のゲートには
電源16の電圧と同じVLが印加されるのでオンとなり、MO
SFET4のゲートには電源17が印加されオンとなる。従つ
てMOSFET3のゲートとソースは同電位となりMOSFET3はオ
フとなる。MOSFET2のゲートG2にも電源17が印加されて
オンとなり、トランジスタ１のベースに電流が流れ、ト
ランジスタ１はオンする。Next, when a low voltage V L having the same potential as that of the power supply 16 is input to the input terminal, the MOSFET 13 is turned on and the source and the gate of the MOSFET 11 are brought to the same potential and turned off. Since the same V L as the voltage of the power supply 16 is applied to the gate of the MOSFET 12, it turns on and the MO
The power supply 17 is applied to the gate of the SFET4 and turned on. Therefore, the gate and the source of the MOSFET 3 have the same potential, and the MOSFET 3 is turned off. The power supply 17 is also applied to the gate G 2 of the MOSFET 2 to turn it on, a current flows through the base of the transistor 1, and the transistor 1 turns on.

MOSFET6のゲートには電源16と同じ電圧VLが印加される
のでオフになる。MOSFET5のゲートには電源17が印加さ
れるのでオンとなり、 MOSFET9のゲートには電源16が印加されオンとなる。従
つてMOSFET10のゲートとソースは同電位となりオフとな
る。又、MOSFET8のゲートG3には電源16が印加されるの
でオン状態となり、トランジスタ１のベースにやはり電
流を供給し、トランジスタ１はオンする。この時、A,B
端子の電位がフローテイング状態にあつてもMOSFET2及
び３のゲート端子G2,G3電位とA,B端子の電位の高低関係
によらずnpnトランジスタ１をオンさせることができる
がその動作機構は端子間電位の相対関係により異なる。Since the same voltage V L as that of the power supply 16 is applied to the gate of the MOSFET 6, it turns off. The power supply 17 is applied to the gate of the MOSFET 5 and thus is turned on, and the power supply 16 is applied to the gate of the MOSFET 9 and is turned on. Therefore, the gate and the source of the MOSFET 10 have the same potential and are turned off. Further, since the power supply 16 is applied to the gate G 3 of the MOSFET 8, the MOSFET 8 is turned on, the current is also supplied to the base of the transistor 1, and the transistor 1 is turned on. At this time, A, B
Even when the potential of the terminal is in a floating state, the npn transistor 1 can be turned on regardless of the relationship between the potentials of the gate terminals G 2 and G 3 of the MOSFETs 2 and 3 and the potentials of the A and B terminals. Depends on the relative relationship of the potential between the terminals.

ゲート端子G2,G3の電位がA,B端子の電位よりも低い場合
はMOSFET2,8のソース、ドレイン電位がゲート電位より
高い状態になつている。従つてｎチヤネルMOSFET2はオ
フのままであるが、ＰチヤネルMOSFET8がオンする。そ
の結果、ＰチヤネルMOSFET8のソース・ドレイン間電流
がトランジスタ１のベースに流れ込みnpnトランジスタ
１がオンする。When the potentials of the gate terminals G 2 and G 3 are lower than the potentials of the A and B terminals, the source and drain potentials of the MOSFETs 2 and 8 are higher than the gate potential. Therefore, the n-channel MOSFET 2 remains off, but the p-channel MOSFET 8 turns on. As a result, the source-drain current of the P-channel MOSFET 8 flows into the base of the transistor 1 to turn on the npn transistor 1.

一方、ゲート端子G2,G3の電位がA,B端子の電位よりも高
い場合はMOSFET2,8のソース・ドレイン電位がゲート電
位よりも低い状態になつている。従つてＰチヤネルMOSF
ET8はオフ状態のままであるが、ｎチヤネルMOSFET2がオ
ンする。その結果、ベース電流が供給されることになり
npnトランジスタ１がオンする。On the other hand, when the potentials of the gate terminals G 2 and G 3 are higher than the potentials of the A and B terminals, the source / drain potentials of the MOSFETs 2 and 8 are lower than the gate potential. Therefore, P channel MOSF
ET8 remains off, but n-channel MOSFET2 turns on. As a result, the base current is supplied.
The npn transistor 1 turns on.

ゲート端子G2,G3の電位がＢ端子よりも高く、Ａ端子よ
りも低い場合は上記の両ケース又はいずれか一方のケー
スの動作が起こりnpnトランジスタ１がオンする。When the potentials of the gate terminals G 2 and G 3 are higher than the B terminal and lower than the A terminal, the operation of both cases or one of the above cases occurs and the npn transistor 1 is turned on.

以上のごとく、本実施例では主端子A,Bの電位がフロー
テイング状態にあつても確実に主駆動部のnpnトランジ
スタ１をオンオフ制御ができる。As described above, in this embodiment, the on / off control of the npn transistor 1 of the main drive section can be reliably performed even when the potentials of the main terminals A and B are in the floating state.

本実施例になる素子の特性は次のとおりである。npnト
ランジスタのBVCEOは200V,BVCBOは350Vである。又、入
出力間絶縁耐圧即ちA,B端子とG1端子間の絶縁耐圧は300
Vである。電源16,17として各々−5V及び＋5Vの電源を用
いた場合、G1に10Vのパルス信号を供給することによりn
pnトランジスタをフローテイング状態でもオンオフ駆動
することができ、その時のnpnトランジスタの通電電流
は30mAであつた。The characteristics of the device according to this example are as follows. The BV CEO of the npn transistor is 200V and the BV CBO is 350V. In addition, the dielectric strength between input and output, that is, the dielectric strength between terminals A, B and G 1 is 300.
V. When -5V and + 5V power supplies are used as the power supplies 16 and 17, respectively, by supplying a pulse signal of 10V to G 1 , n
The pn transistor can be driven on and off even in the floating state, and the energization current of the npn transistor at that time was 30 mA.

以上のように主駆動部の３端子のスイツチング素子とし
てnpnトランジスタを用いて本発明の詳細を説明した
が、本発明はこれに限定されるものではなく、３端子の
スイツチング素子としては、npnトランジスタやFET,IGT
などの様な他の周知の３端子半導体スイツチング素子を
用いても全く同様の機能を達成できるものである。Although the present invention has been described in detail by using the npn transistor as the switching element with three terminals of the main drive unit as described above, the present invention is not limited to this, and an npn transistor is used as the switching element with three terminals. FET, IGT
The same function can be achieved by using other well-known 3-terminal semiconductor switching elements such as.

〔発明の効果〕〔The invention's effect〕

本発明によれば主駆動部と制御部がMOSゲートを介して
結合されているので、入出力間が絶縁され、フリツプフ
ロツプ回路のオンオフ入力信号により主駆動部の電位が
フローテイング状態であつても確実にオンオフ制御がで
きる。According to the present invention, since the main drive unit and the control unit are coupled via the MOS gate, the input and output are insulated, and even if the potential of the main drive unit is in the floating state by the ON / OFF input signal of the flip-flop circuit. ON / OFF control can be reliably performed.

【図面の簡単な説明】[Brief description of drawings]

第１図は本発明の一実施例の主駆動部及びフリツプフロ
ツプ制御の回路図である。 １……npnトランジスタ、2,3,4,5,6,7……ｎチヤネルMO
SFET、8,9,10,11,12,13……ＰチヤネルMOSFET、14,15…
…ダイオード、16,17……直流電圧源。FIG. 1 is a circuit diagram of a main drive unit and flip-flop control according to an embodiment of the present invention. 1 …… npn transistor, 2,3,4,5,6,7 …… n channel MO
SFET, 8,9,10,11,12,13 …… P channel MOSFET, 14,15…
… Diodes, 16,17 …… DC voltage source.

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】主駆動部に、一対の主端子と制御端子を備
えるオン・オフ可能な３端子素子を有し、 一方の主端子と制御端子の間には、ｎチャンネル及びｐ
チャンネルの３端子素子駆動用のMOSFETのソース及びド
レインを接続し、 ３端子素子駆動用のMOSFETの各々が、ゲートの制御のた
めに、電源と、複数のMOSFETから構成されるフリップフ
ロップ回路と、を備え、 各電源は電位が異なり、 各フリップフロップ回路は、３端子素子駆動用のMOSFET
のソースと電源と、に接続され、 各フリップフロップ回路の出力は、３端子素子駆動用の
MOSFETのゲートに接続されることを特徴とする半導体装
置。1. A main driving section has a three-terminal element which is provided with a pair of main terminals and a control terminal and can be turned on and off, and an n channel and a p channel are provided between one main terminal and the control terminal.
The source and the drain of the MOSFET for driving the three-terminal element of the channel are connected, and each of the MOSFET for driving the three-terminal element has a power supply for controlling the gate, and a flip-flop circuit including a plurality of MOSFETs. Each power supply has a different potential, and each flip-flop circuit is a MOSFET for driving a three-terminal element.
Is connected to the source and the power supply of each, and the output of each flip-flop circuit is
A semiconductor device characterized by being connected to the gate of a MOSFET.
JP62110540A 1987-05-08 1987-05-08 Semiconductor device Expired - Lifetime JPH0738579B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62110540A JPH0738579B2 (en) 1987-05-08 1987-05-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62110540A JPH0738579B2 (en) 1987-05-08 1987-05-08 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS63276322A JPS63276322A (en) 1988-11-14
JPH0738579B2 true JPH0738579B2 (en) 1995-04-26

Family

ID=14538402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62110540A Expired - Lifetime JPH0738579B2 (en) 1987-05-08 1987-05-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0738579B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS617665A (en) * 1984-06-22 1986-01-14 Nippon Telegr & Teleph Corp <Ntt> Semiconductor device

Also Published As

Publication number Publication date
JPS63276322A (en) 1988-11-14

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