JPH0738708B2 - Field discrimination circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to an image memory of a digital image recording device to which video signals introduced from a plurality of diagnostic devices such as CT (computer tomography) and US (ultrasonography) are stored. More specifically, the present invention relates to a field discriminating circuit that outputs a field discriminating signal relating to a video signal used as an address signal of an image memory when recording, and more specifically, various video output devices (eg, a television set) constituting various diagnostic devices. When recording multiple video signals with different number of scanning lines output from the camera) in the image memory of one digital image recording device, frequency voltage conversion circuit (hereinafter referred to as F / V conversion circuit)
A field discrimination signal controlled by the field discrimination circuit is used to generate a field discrimination signal from the video signals having different scanning lines, and the field discrimination signal is used as an address signal of an image memory to obtain a plurality of images having different scanning lines. The present invention relates to a field discriminating circuit incorporated in an image recording device capable of orderly recording signals in an image memory in the digital image recording device.

[Prior Art] For example, if CT, US, etc., for example, can continuously obtain image information around the affected part of the human body as image information, the condition of the affected part itself and its surroundings can be grasped, which is very convenient for doctors and the like. Is. In this case, if a plurality of image information is recorded as a hard copy by exposing and recording a plurality of image information in real time, in particular, on a photographic film or the like, it can be used for medical diagnosis regardless of time and place.

However, the video signals output from these medical image diagnostic apparatuses are not always the same in specifications, and for example, the number of scanning lines, field frequency, etc. often differ depending on the diagnostic apparatus.

Therefore, conventionally, in order to store the video signals related to different scanning lines in the image memory of the digital image recording device, the field determination is performed by the image recording device including the field determination circuit in which the constant is set for each video signal. The signal is derived and recorded in the image memory according to the field discrimination signal.

However, with the recent technical development of medical diagnostic equipment, the types of medical diagnostic equipment are DF (digital fluorography), MRI (magnetic resonance imaging), and RI (radioisotope) equipment in addition to the above-mentioned CT and US. Therefore, adopting and introducing a digital image recording device corresponding to each diagnostic device significantly increases the economical burden and requires a large accommodation space. It has come to expose the inconvenience.

[Problems to be Solved by the Invention] The present invention has been made in order to overcome the above-mentioned inconvenience, and a plurality of different scanning lines output from various video output devices constituting various diagnostic devices and the like are provided. Video signal of 1
When recording an image for each frame of the video signal in the image memory of the digital image recording device of the stand, the field discrimination time constant is automatically controlled by the control signal from the F / V converter. Of the composite video signal, a field discrimination signal for an odd field and an even field is derived, and the field discrimination signal is used as an address signal of the image memory to obtain a plurality of video signals having different scanning lines. It is an object of the present invention to provide a field discriminating circuit incorporated in an image recording device that enables real-time storage of each frame of a video signal in an image memory in the recording device.

[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides a field discrimination signal from a composite sync signal relating to a plurality of composite video signals output from various video output devices and having different scanning lines. Is a field discrimination circuit for deriving the
Input to the conversion circuit, the equalization pulse removal circuit and the vertical synchronization separation circuit controlled by the F / V conversion circuit, and at least 1
A field detecting circuit including substantially delay flip-flop means, an output terminal of the equalizing pulse removing circuit is connected to the data input terminal, and an output terminal of the vertical sync separating circuit is connected to a trigger input terminal, and a time constant F / V for control terminal
The output terminal of the conversion circuit is connected and introduced into the data input terminal by the field detection circuit at a time point or a predetermined time after a predetermined time has elapsed from a predetermined leading edge of the rectangular wave output signal of the vertical sync separation circuit. It is characterized in that it is configured to judge the binary level of the output signal of the equalization pulse removal circuit and derive a high level or low level field discrimination signal.

[Embodiment] Next, the field discriminating circuit according to the present invention will be described in detail below with reference to the accompanying drawings.

In FIG. 1, reference numeral 10 is an overall block diagram of a field discriminating circuit incorporated in a video image recording device (not shown).
Equalized pulse removal circuit 14 controlled by F / V conversion circuit 12
And a field detection circuit 16 and a vertical sync separation circuit 18 which are controlled by the F / V conversion circuit 12.
Here, the F / V conversion circuit 12 is a low-pass filter (hereinafter, LP converter) including a pulse shaping circuit 20 and a level shift circuit described later.
It is called F).

In FIG. 1, first, the composite sync signal separated from the composite video signal (hereinafter referred to as the C.SYNC signal) is the F / V conversion circuit 1
It is supplied to the pulse shaping circuit 20, the equalization pulse removal circuit 14 and the vertical synchronization separation circuit 18 in the second circuit. Here, as is well known, the C.SYNC signal is a signal that combines a horizontal sync signal (hereinafter, H.SYNC signal), a vertical sync signal (hereinafter, V.SYNC signal), an equalization pulse and a cut pulse. Say.

Next, the output signal of the F / V conversion circuit 12 is equalized pulse removal circuit 1
It is introduced to the time constant control input terminal α of 4 and the time constant control input terminal CNTL of the field detection circuit 16.

On the other hand, the output signal of the equalization pulse removal circuit 14, i.e., H.
The output signal of the SYNC signal and the vertical sync separation circuit 18, that is,
The V.SYNC signal is introduced to the data input terminal DATA and the trigger input terminal TRIG of the field detection circuit 16, respectively. In this case, the field detection circuit 16 is configured to output an even or odd field discrimination signal FIELD at its output. The field discriminating signals FIELD, H.SYNC and V.SYNC signals output from the field discriminating circuit 10 shown in FIG. 1 are sent to an image memory or a sampling pulse generator (not shown), and an address signal or a timing signal. Used as etc.

Next, FIG. 2 shows a more detailed circuit of the field discrimination circuit shown in FIG. Note that, in FIG. 2, details of the vertical synchronization separation circuit 18 are omitted because a well-known double integration circuit or the like may be adopted, for example. Further, in FIG. 2, the same components as those shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

As can be easily understood from FIG. 2, the pulse shaping circuit 20 basically comprises a first monostable multi-vibrator IC10 (hereinafter referred to as M / MIC10 or IC10), and L
The PF22 includes a low-pass filter unit 22a composed of the first operational amplifier IC20 and a level shift unit 22b composed of the second operational amplifier IC30. On the other hand, the equalization pulse removal circuit 14 is composed of M / MIC 40 and M / MIC 50, and the field detection circuit 16 is basically composed of M / MIC 60 and a D type flip-flop IC80 (hereinafter referred to as F / FIC80 or IC80). In FIG. 2, reference numeral V _C indicates a power supply voltage, and although not shown, each IC has a power supply voltage + V _C or −V _C.
V _C shall be supplied.

The field discriminating circuit according to the present invention is basically constructed as described above. Next, its operation and effect will be described.

FIG. 3a shows a C.SYNC signal obtained by removing the video signal portion from the composite video signal and separating the synchronization. In this case, the C.SYNC signal is the H.SYNC signal, V.
It is a signal including a SYNC signal, an equalizing pulse, and a cutting pulse. Then, in the C.SYNC signal shown in FIG.
The period T _{H of the} NC signal is 63.5 μs, the number of scanning lines is 525, and the field frequency is 60 Hz. Incidentally, FIG. 3 shows the states of various signals in the vicinity of the first field V.SYNC in the C.SYNC signal.

Therefore, this C.SYNC signal is introduced to the F / V conversion circuit 12, the equalization pulse removal circuit 14, and the vertical synchronization separation circuit 18. As described above, the F / V conversion circuit 12 is substantially composed of the M / MIC 10 and the operational amplifier IC20. That is, the output signal of the M / MIC 10 is smoothed by the low-pass filter unit 22a including the operational amplifier IC20 and converted into a DC signal. In this case, the time constant of the M / MIC 10 is determined by the resistor R10 and the capacitor C10, and the time constant is set shorter than the cycle of the maximum horizontal frequency input to the field discrimination circuit 10. By setting in this way, the output signal of the operational amplifier IC20 can be a voltage signal V _H that increases in proportion to the horizontal frequency, as shown in the characteristic curve diagram of FIG. The voltage signal V _H is kept at a constant voltage as long as the horizontal frequency is constant, that is, when the input composite video signal is a video signal output from the same imaging device.

Next, the voltage signal V _H is inverted in polarity and amplified by the level shift unit 22b including the operational amplifier IC30, and is amplified by the time constant control input terminal α of the equalization pulse removal circuit 14 and the time constant control input terminal CNTL of the field detection circuit 16. Supplied.

Here, first, the operation of the equalization pulse removal circuit 14 will be described. The equalizing pulse removing circuit 14 is the second M
/ MIC40 and 3rd M / MIC50, in this case, 2nd M / MIC40
Operates as a retriggerable M / M, and the third M / MIC 50 operates as a normal M / M. In this case, retriggerable M / M,
That is, the time constant of the second M / MIC 40 is approximately 3 / of the horizontal synchronization period T _H.
The time constant of the 3rd M / MIC50 selected for the time of 4T _H is approximately H.SYN.
SYNC width of C signal, for example, is selected in 7 / 100T _H time. Here, the reason for selecting the time constant of the second M / MIC 40 to 3 / 4T _H is that the error exceeds the range of 1 / 2T _{H to} 1T _H even if there is an error in the insertion position and setting accuracy of the equalization pulse. This is because it is assumed that there is no such thing.

Therefore, the output signal of the equalization pulse removal circuit 14, that is,
The output signal of the third M / MIC 50 becomes the H.SYNC signal shown in FIG. That is, since the selected time constant of the 2M / MIC 40 in 3 / 4T _H, among C.SYNC signal shown in FIG. 3 a, is inserted at the position of about 1/2 cycle of H.SYNC signal period The equalized pulse and the cut pulse that are generated are removed. This H.SYNC signal is introduced to the data input terminal DATA of the field detection circuit 16.

Next, before describing the operation of the field detection circuit 16, the characteristics of the vertical synchronization signal V.SYNC signal input to the input terminal TRIG of the field detection circuit 16 will be described.

As described above, the vertical synchronizing signal V.SYNC signal is represented by a signal obtained by double integrating the C.SYNC signal, for example, the signal shown in FIG. In this case, the V.SYNC signal is delayed by the integration process. FIGS. 3d to 3h are time-enlarged views of the broken line portions of the waveforms and the like according to FIGS. 3a to 3c.
The enlarged waveform shown in FIG. 3 corresponds to the waveform shown in FIGS. Therefore, FIG. 3f is an enlarged waveform of the V.SYNC signal,
As can be seen from the waveform diagram, the delay time of the V.SYNC signal is the time delayed by Ta time from the falling edge E _{N of} C.SYNC shown in FIG. 3d. The V.SYNC signal is supplied to the trigger input terminal TRIG of the field detection circuit 16.

Next, the operation of the field detection circuit 16 will be described. Field detection circuit 16 has three input terminals CNTL, DATA and
TRIG respectively includes the output voltage signal V _H of the F / V conversion circuit 12, the output signal H.SYNC of the equalization pulse removal circuit 14 (see FIG. 3e) and the output signal V.SYNC of the vertical sync separation circuit 18 (first 3f) is introduced. As described above, the field detection circuit 16 is composed of the fourth M / MIC 60 and the first F / FIC 80.
Then, the fourth M / MIC 60 is triggered by the falling edge of the V.SYNC signal, and the first F / FIC 80 is triggered by the falling edge of the fourth M / MIC 60. In this case, the time constant of the 4th M / MIC60 is F /
It is controlled by the output signal of the V conversion circuit 12. That is, as described above, the output voltage of the F / V conversion circuit 12, in other words, the voltage of the input terminal CNTL of the field detection circuit 16 decreases in proportion to the horizontal frequency of the signal input to the field determination circuit 10. , The base voltage of transistor TR60 drops and the collector current of TR60 increases, so
It is controlled so that the time constant of / MIC60 becomes small. That is, the time constant of the fourth M / MIC 60 decreases in proportion to the horizontal frequency. This is shown in the characteristic curve diagram of FIG. 4b. In this case, when the time constant of the fourth M / MIC 60 is T _FV , the value is determined as shown in the following first formula.

However, Ta: delay time related to vertical sync separation circuit T _H : period of horizontal frequency For example, if horizontal period T _H ≈ 63.5 μs and delay time Ta ≈ 6 μs, the time constant T _FV of the fourth M / MIC60 is T _FV It suffices to set ≈26 μs. At this time, the output signal of the fourth M / MIC 60 has the waveform shown in FIG. Therefore, this output signal is the 1st F / FIC
When input to the clock input terminal CK of 80, the level data input to the data input terminal D of the first F / FIC 80 is transmitted to the output terminal Q at the falling edge portion thereof.
The level data is the H.SYNC signal shown in FIG.
In this case, the level is high, so the first F / FIC
80 output signals, i.e.
The odd field discrimination signal FIELD becomes a signal which transits from a low level to a high level as shown in FIG.
Therefore, when the field discrimination signal FIELD is high level, it is an odd (ODD) field, and when it is low level,
If it is defined as an even (EVEN) field, the field can be discriminated.

Although not described in detail because the field discrimination signal FIELD is not the gist of the present invention, the address of an image memory (not shown) can be determined and accurately recorded in the memory.

As described above, the explanation of the above operation is based on the number of scanning lines 525.
Book, field frequency 60Hz, ie horizontal frequency 15.7
It is an explanation of the operation when the input signal relates to an odd field in the case of 5 KHz.

Next, the operation when the input signal relates to the even field will be described. The time chart in this case is shown in FIG.
To h. Here, the respective signals in FIG. 5 correspond to those in FIG.
Each of the signals a to h corresponds in the same order. In this case, the fifth
As can be easily understood from FIGS. A and b, in the C.SYNC signal, the time relationship between the V.SYNC signal and the H.SYNC signal is the same as that of the odd field shown in FIG. There is a 1 / 2T _H shift at the time of the fall. Therefore, the enlarged waveform of the H.SYNC signal shown in FIG. 5e inputted to the data input terminal D of the first F / FIC 80 and the 4M / 4M / shown in FIG. 5g inputted to the clock input terminal CK of the first F / FIC80 are shown. By comparing the falling edge part of the output signal of MIC60, the output signal of the first F / FIC80,
That is, since the output signal FIELD of the field detection circuit 16 becomes a signal which transits from the high level to the low level as shown in FIG. 5h, it is understood that it is an even field. Therefore, the even field discriminating signal is also used as address data of an image memory (not shown) like the odd field discriminating signal.

The above is 525 scanning lines, that is, the horizontal frequency is 15.75KHz.
The field discriminating circuit 10 according to the present invention, as shown in FIGS. 4A and 4B, shows the equalizing pulse removing circuit in proportion to the horizontal frequency. the time constant of the 2M / MIC 40 within 14 to follow so as to automatically 3 / 4T _H. Therefore,
Since the time constant T _FV of the 4th M / MIC60 in the field detection circuit 16 is also automatically tracked so that T _FV = T _H / 2−Ta, the horizontal frequency is 33.75 KHz and the number of scanning lines is 1000, for example. Even in the case of the video signal of, as shown in FIG. 7 (in the case of odd field discrimination) and FIG. 8 (in the case of even field discrimination), the field discrimination signal can be automatically obtained without changing the constant of the circuit. Can be done. Note that, in FIGS. 7 and 8, the respective signals correspond to the signals in FIGS. 3 and 5 in the same order.

Further, as another embodiment of the present invention, the field detection circuit 16 can be configured as shown in FIG. 8, for example. The field detection circuit 16 is basically the fifth M /
It is composed of a MIC100, a sixth M / MIC120, a negative logic AND circuit IC125, and a second F / FIC130.

As shown in FIG. 8, the sixth M / MIC 120 is configured to be driven by the output signal of the fifth M / MIC 100, and the field detection circuit is provided during the low level period of the negative output terminal of the sixth M / MIC 120.
H.SYNC width of the H.SYNC signal input to 16 input terminals DATA T _SH
Negative logic AND circuit IC whether (low level) exists
The determination is made at 125, and the field discrimination signal FIELD is derived at the output terminal of the second F / FIC 130. That is, in this embodiment, the edge detection method in the above-mentioned embodiment is changed to the level detection method.

In this case, the time constant T _FVO of the 5th M / MIC ₁₀₀ is as follows from the second equation Ta + T _FVO <T _H (2) The time constant T _{FV1 of the} 6th M / MIC 120 is Based on the third equation of T _FV1 > T _SH (3), the time constant T _{FVO of the} 5th M / MIC100 and 6th M / MIC120
Determine T _FV1 . In this case, the number of elements constituting the circuit is slightly increased, but the design condition of the circuit is remarkably relaxed as compared with the previous embodiment.

The time charts in FIGS. 9 and 10 are 52 scanning lines, respectively.
It is a drawing relating to the even / odd field discrimination in the case of 5 pieces,
The time charts in FIGS. 11 and 12 each show 10 scanning lines.
The drawing related to the even / odd field discrimination in the case of 00 lines is shown.
Since the time chart is easily understood by referring to the above description, detailed description thereof will be omitted.

[Effects of the Invention] As described above, according to the present invention, a plurality of video signals with different numbers of scanning lines output from various video output devices constituting various diagnostic devices can be stored in one digital image recording device. When recording an image for each frame of a video signal in the image memory,
The time constant of the equalization pulse removal circuit and the time constant of the field detection circuit are automatically controlled by the control signal from the F / V conversion circuit. Therefore, the field discriminating signal according to the present invention is used to derive the field discriminating signal for the odd field and the even field in the composite video signal, and the field discriminating signal is used as the address signal of the image memory in the image recording device. As a result, it is possible to accurately store a plurality of video signals having different scanning lines in the image memory in the image recording device for each frame of the video signal.

The images recorded by the present invention are used as signal sources for various image recording devices (multi-format cameras, laser printers, thermal printers, ink jets, etc.), simple integrated image diagnostic system PACS (Picture Archiving and Comm.
It can be preferably used as an input signal source of a file, an primary image storage system for an X-ray TV or a cine system, an image buffer to which an image memory is applied, a scan converter, or the like.

Although the present invention has been described with reference to the preferred embodiment, the present invention is not limited to this embodiment,
It goes without saying that various improvements and design changes can be made without departing from the scope of the present invention.

[Brief description of drawings]

FIG. 1 is a block diagram of a field discriminating circuit according to the present invention, FIG. 2 is a detailed circuit block diagram of an essential part of the field discriminating circuit according to the present invention, and FIG. 3 is an explanation of the operation of the field discriminating circuit according to the present invention. 4A is a characteristic diagram relating to the F / V converter, FIG. 4B is a characteristic diagram showing the time constant of the monostable multivibrator relating to the field detection circuit, and FIGS. 8 is a timing chart for explaining the operation of the field discriminating circuit according to the invention, FIG. 8 is a detailed circuit block diagram showing another embodiment of the field discriminating circuit according to the invention, and FIGS. 9 to 12 are related to the invention. 9 is a timing chart for explaining the operation of another embodiment of the field discrimination circuit. 10 …… Field discrimination circuit, 12 …… F / V conversion circuit 14 …… Equalized pulse removal circuit 16 …… Field detection circuit 18 …… Vertical sync separation circuit, 20 …… Pulse shaping circuit 22 …… Low-pass filter IC10… … 1st monostable multivibrator IC20 …… 1st operational amplifier IC30 …… 2nd operational amplifier, IC40 …… 2nd M / M IC50 …… 3rd M / M, IC60 …… 4th M / M IC80 …… 1st F / F, IC100 …… 5th M / M IC120 …… 6th M / M IC125 …… Negative logic AND circuit IC130 …… 2nd F / F

Claims (3)

[Claims] 1. A field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relating to a plurality of composite video signals having different numbers of scanning lines outputted from various video output devices, wherein the composite synchronizing signal is a frequency / voltage signal. Conversion circuit (hereinafter,
(Referred to as an F / V conversion circuit) and data of a field detection circuit which is input to an equalization pulse removal circuit and a vertical synchronization separation circuit controlled by the F / V conversion circuit and includes at least one delay flip-flop means. Connect the output terminal of the equalized pulse removal circuit to the input terminal, connect the output terminal of the vertical sync separation circuit to the trigger input terminal, and connect the output terminal of the F / V conversion circuit to the time constant control terminal. The output signal of the equalization pulse removing circuit introduced to the data input terminal at a time point or a predetermined time after a predetermined leading edge of the rectangular wave output signal of the vertical sync separation circuit by the field detection circuit. A field discriminating circuit configured to determine a binary level and derive a high-level or low-level field discriminating signal. 2. The circuit according to claim 1, wherein the field detection circuit is substantially composed of monostable multivibrator means and D type flip-flop means, and is perpendicular to the trigger input terminal of the monostable multivibrator means. Derives the output signal of the sync separation circuit,
The output signal of the F / V conversion circuit is introduced to the time constant control input terminal of the monostable multivibrator means, the output terminal of the monostable multivibrator means is connected to the clock input terminal of the D type flip-flop means, and the D type flip-flop is connected. A field discriminating circuit configured to introduce the output signal of the equalization pulse removing circuit to the data input terminal of the means so that the output signal of the D type flip-flop means is derived as a field discriminating signal. 3. The circuit according to claim 1, wherein the field detection circuit comprises a first monostable multivibrator means, a second monostable multivibrator means, a D type flip-flop means and a negative logic AND means. Therefore, the output signal of the vertical sync separation circuit is introduced to the trigger input terminal of the first monostable multivibrator means, and the output signal of the F / V conversion circuit is introduced to the time constant control input terminal of the first monostable multivibrator means. , Introducing the output signal of the first monostable multivibrator means to the trigger input terminal of the second monostable multivibrator means and introducing the positive output signal of the second monostable multivibrator means to the clock input terminal of the D-type flip-flop means. 2nd monostable multivibrator The negative output signal of the negative logic AND circuit is introduced to one input terminal of the negative logic AND circuit, and the output signal of the equalization pulse removing circuit is introduced to the other input terminal of the negative logic AND circuit. Is introduced into the set input terminal of the D type flip-flop means, and the data input terminal of the D type flip-flop means is grounded so that the negative output signal of the D type flip-flop means is derived as the field discrimination signal. Discrimination circuit.