JPH0740257B2 - Memory access controller - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access control device, and more particularly, to a data flow type information processing device which can be executed by executing an instruction as soon as data to be operated is prepared. The present invention relates to a memory access control device that stores a data flow program and accesses a cache memory that fetches instructions according to an input data packet.

[Prior Art and Problems to be Solved by the Invention] In a conventional computer, various instructions are stored in a program memory as a program, addresses of the program memory are sequentially designated by a program counter, and the instructions are sequentially read. Most are Neumann computers that execute instructions.

On the other hand, the data flow type computer is a kind of non-Neumann type computer that does not have the concept of sequentially executing instructions to the program counter. Such a data flow type computer employs an architecture based on parallel processing of instructions. Instructions can be executed as soon as the data to be operated are prepared, and a plurality of instructions are simultaneously driven by the data, so that the programs are executed in parallel according to the natural flow of the data. As a result, it is considered that the time required for calculation is significantly shortened.

Incidentally, the conventional data flow type computer generally has a built-in program memory, and there is no concept of providing the program memory externally. If a program memory is provided externally, the problem is how to access the built-in cache memory and external program memory.

Therefore, a main object of the present invention is to provide a memory access control device in which a large capacity program memory is externally attached and an internal cache memory can be accessed at high speed.

[Means for Solving the Problem] The present invention is an information processing apparatus including a program control unit, a pair data detection unit, an arithmetic processing unit, and an external program storage unit, and the program control unit is configured as follows.
That is, an input means to which an execution packet or a data flow program to be loaded into the external program storage unit is given from the outside, and the input data flow program is output to the external program storage unit or read from the external program storage unit. Whether the data flow program or the execution packet fetched by the external program storage unit is input is controlled every time the data flow program or the execution packet is input asynchronously, based on the information included in each of them. First input / output control means, a cache memory that stores a data flow program and outputs program data corresponding to an execution packet, and a cache memory that accesses the cache memory according to address information included in the packet input from the input means. Accessing the cache memory in succession at least twice to the control unit and the address information included in the execution packet inputted from the input-output control means,
Data is asynchronously input according to the copy information, the second control means for outputting together with the copy information, the execution packet fetched in the cache memory and the execution packet fetched by the external program storage unit input from the input / output control means. And output control means for controlling the output for each.

[Operation] The memory access control device according to the present invention loads the data flow program into the external program storage unit when the data flow program is given from the outside, and includes the execution packet when the execution packet is given from the outside. For the address information to be fetched, the next different instruction is accessed twice in succession in the cache memory, the fetched instruction is output, and when there is a miss in the cache memory, the external program memory is accessed to fetch the execution packet. Then, the execution packet is output.

[Embodiment] FIG. 1 is a schematic block diagram of an information processing apparatus to which the present invention is applied. First, the configuration of the information processing apparatus will be described with reference to FIG.

An external program memory 2 is externally attached to the information processing device 1. The information processing device 1 includes branch coupling units 3, 4, 5 and 10 and a buffer 11 which form an input / output control circuit. An input data packet is given to the branch coupling unit 3, and this input data packet is branched by the branch coupling unit 3 and given to the branch coupling unit 4 or 5. The branching / coupling unit 5 gives to the program control unit 6 either the input data packet output from the branching / coupling unit 3 or the data packet given from the buffer 11 described later. The program control unit 6 stores a plurality of key codes that are a combination of the node N # and G / C (Generation / Color). When the corresponding key code is input, the destination node N # and its destination on the program are stored. A TAG indicating what processing is to be performed at destination node N # is output to paired data detection unit 7.

The paired data detection unit 7 determines whether or not a pair of program data and processed data has been input to the program data and processed data read from the program control unit 6. When a pair of program data and processed data is detected and generated by the pair data detection unit 7, the contact 8 is closed. Even when the program data is nop, the contact 8 is closed because the program data to be paired is unnecessary. The output of the paired data detection unit 7 is also given to the external program memory 2. The program data and the processed data output from the paired data detection unit 7 are given to the ALU 9 via the contact 8 to be operated, and the operation result is branched to the buffer 11 or the branch connection unit 4 by the branch connection unit 10. . The calculation result stored in the buffer 11 is given to the program control unit 6 via the branch / coupling unit 5.

External program memory 2 uses the N # and G / C included in the program data output from paired data detection unit 7 as key codes to read the program data of the next command and upload it to program control unit 6.

The above-mentioned buffer 11 is provided to perform a delay operation for giving the operation result of the ALU 9 to the program control unit 6 after the external program memory 2 reads the program data. The external program memory 2 is configured so that the program controller 6 can initially write (download) the program data.

FIG. 2 is a diagram showing an example of a program processed by the information processing apparatus shown in FIG. 1, and FIGS.
The figure is a diagram showing changes in the program data of each unit when the program shown in FIG. 2 is executed by the information processing apparatus 1 shown in FIG.

Next, a specific operation of the program processing by the information processing device will be described with reference to FIGS. 1 to 10.
First, as is apparent from the program shown in FIG. 2, the program data following the node N # A is data 0 at the node.
It is desirable that the program control unit 6 be arranged so that it can execute the add instruction at the node and the data given from the node D and the NOP instruction is executed at the node while executing the nop instruction at.

To this end, as shown in FIG. 3, the information processing device 1 has data 0, TAG source, G /
C0 and N # A are given. Here, nodes N # A and G /
A part of each C0 indicates the physical address of the program control unit 6, and the TAG source is that the node N # A designates the input unit of the program data.
Is used as an identifier for identifying at what time data 0 is the sampled data.

The nodes N # A and G / C0 are used as key codes for giving the physical address of the program controller 6 and accessing the memory. The above-mentioned input data packet is given to the program control unit 6 via the branch / coupling units 3 and 5. The program control unit 6 uses the node N # A,
Use G / C0 as a key code to access the corresponding program data. For example, node N # 3, TAG + L is fetched as corresponding program data.

This program data is shown to provide the left input of the addition at the node of the program shown in FIG. At this time, since the same data 0 is given to process the nop instruction in the node, the copy flag is set in advance in the program control unit 6 for the key codes of N # A and G / C0. Then, the program control unit 6 successively fetches N # 8 and TAGnop indicating nop instructions for the key codes of N # A and G / C0.

The program control unit 6 adds G / C0 and data 0 included in the input data packet to the fetched program data of N # 3, TAG + L, and sets a flag 0 indicating that the data is normally fetched. Add.
It should be noted that flag 1 is added when a mishit has occurred.
The pair data detection unit 7 determines whether or not the program data to be paired with this program data has already been fetched. That is, it is determined whether or not the data on the right side of the node shown in FIG. 2 has been fetched.
Since the data on the right side of the node has not been fetched yet, the paired data detection unit 7 puts this program data on standby.

On the other hand, the program data for the nop instruction in the node does not require the program data to be paired, so the program control unit 6 fetches the fetched N # 8, TAGn
G / C0 and data 0 included in the input data packet are added to op, and flag 0 indicating that the data has been normally fetched is added and output. The contact 8 is closed by fetching the program data from the program control unit 6. Therefore, the program data for the nop instruction is given to the ALU 9 and the external program memory 2.

At this time, it is assumed that the information processing apparatus 1 is given the next input data packet. That is, the data 1, TAG source, G / C0, N # B as the program data for the next processing in the node B shown in FIG. Given to. This program data corresponds to N # A described in FIG.
This is almost the same as the above, and the node executes the nop instruction of the data 1 and adds the data 1 to the data given from the node D and executed by the node in the nop instruction.

For this purpose, the program control section 6 uses N # B, G / C0 as the physical address and key code of the memory as shown in FIG. Fetch N # 4, TAG + L. This program data is data which gives the left input of addition at the node of the program shown in FIG. Since the same program data 1 is given to process the nop instruction in the node, the program control unit 6 is
A copy flag is preset for the #B and G / C0 key codes.

Therefore, the next no with the same N # B, G / C0 as the key code
Program data of N # 9 and TAGnop indicating the instruction of p are continuously fetched. Further, to the program data N # 4, TAG + L fetched by the program control unit 6, G / C0 and data 1 included in the input data packet and the flag 0 indicating that the data has been normally fetched are added. Then, the paired data detection unit 7 determines whether or not the paired program data has already been fetched for the program data. That is, it is determined whether or not the data on the right side of the node shown in FIG. 2 has been fetched, but since it has not been fetched yet, this program data is made to wait.

On the other hand, the above-mentioned input data packet is the program control unit 6
While the external program memory 2 is being input to the third
As shown in the figure, the nop given from the pair data detector 7
The next instruction is read from the address corresponding to the key code determined by the combination of N # 8 and G / C0 included in the program data for the instruction. That is, in order to output the data processed by the nop instruction at the node to the node N # x,
The N # 8, G / C0, N # x and TAG syncs are output to the program control unit 6.

Further, although data for the nop instruction is given to the ALU9, since the nop instruction is an instruction indicating that no operation is performed, this program data is output as it is.
Program data of nop instruction is branch / coupling unit 10, buffer 1
1, provided to the program control unit 6 via the branch coupling unit 5.

The program data read from the external program memory 2 is input to the program control unit 6 via the buffer 11 prior to fetching the delayed program data. Therefore, the program controller 6 fetches N # x, TAG sync as shown in FIG. 5 as the program data corresponding to the key code of N # 8, G / C0 included in the program data. Then, the N # y, TAG sync, which is the program data corresponding to the key code of N # 9, G / C0 included in the program data given via the buffer 11, can be fetched.

Next, in the information processing device 1, as the program data of the node D, as shown in FIG. 5, data 3, TAG source, G /
C0 and N # D are given. That is, as shown in FIG. 2, the program data of the node D executes the nop instruction at the node and the inc (increment) instruction at the node. Therefore, the program control unit 6 fetches the program data N # 1, nop using N # D, G / C0 included in this program data as a key code,
The same key code N # D, G / C0 is subjected to copy processing to fetch the corresponding program data N # 2, inc. That is, program control unit 6 determines key code N #.
2, G / C0, data 0, and flag 0 included in the input data packet are added to TAGinc and output to the pair data detection unit 7.

While these processes are being executed, the program data N # 9, G / C0, N # y and TAG sync corresponding to the key codes N # 9 and G / C0 are read out from the external program memory 2 and the program is read. It is given to the control unit 6. This program data indicates that the data processed by the nop instruction at the node shown in FIG. 2 is output to the node y.

Also, ALU9 is N # 1, G / C0, TAGnop, L data shown in FIG.
3, because the program data of flag 0 is a nop instruction,
The data to be processed is passed through, and the branch / coupling unit 10, buffer 11,
It is given to the program control unit 6 via the branch connection unit 10. As shown in FIG. 6, the program control unit 6 uses N # 1, G / C0 of the program data as a key code and N # 3, TAG.
Fetch + R. Then, the program control unit 6
Program data consisting of N # 3, G / C0, TAG + R, data 3 and flag 0 is given to the paired data detection unit 7.

Such instruction fetching is possible because the external program memory 2 has N # 1, G / C0, TAGnop, L data shown in FIG.
Key code N # of program data consisting of 3, flag 0
Based on 1, G / C0, two corresponding sets of program data, G
This is because / C0, N # 3, TAG + R, N # 4, TAG + R are continuously read and these instructions are given to the program control unit 6 before being fetched. Therefore, the program control unit 6 also fetches the data of N # 4, TAG + R using N # 1, G / C0 of the program data as a key code,
Program data of N # 4, G / C0, TAG + R, and data 3 is given to the paired data detection unit 7.

That is, the paired data detection unit 7 is provided with the processed data on the left side of the node and the processed data on the right side of the node shown in FIG. As described above with reference to FIG. 3, the program data and processed data on the left side of the node have already been given to the paired data detection unit 7,
Further, as described with reference to FIG. 4 described above, the program data and processed data on the left side of the node have already been given to the paired data detection unit 7. Therefore, the paired data detection unit 7 detects that the two processed data of the node and the two processed data of the node are aligned, and as shown in FIG. 7, first, N # 3, G / C0, TAG +, L data 0, R data 3,
The program data of flag 0 is given to ALU9. Depending on,
The ALU9 executes arithmetic processing for addition in the node. Further, the paired data detection unit 7 supplies the program data of N # 4, G / C0, TAG +, L data 1 and R data 3 to the ALU 9, and causes the arithmetic processing in the node to be executed.

As described above, the ALU 9 executes the arithmetic processing of the node, and then executes the isel instruction at the node, as shown in FIG. This isel instruction is an integer type read instruction.

Next, when executing the isel instruction, the program control unit 6
The operation when a hash collision occurs will be described.
In this example, a combination of N # and G / C is used as a key code for fetching program data. in this case,
If N # 5 and N # 6 are represented by a 4-bit code, “010
It becomes 1 "and" 0110 ", and it is possible to identify each. However, for example, when the upper 2 bits are used as a key code and the lower 2 bits are used as a physical address, both are the same because they are" 01 ". That is, when the upper 2 bits are used as a key code, N # 5, N # 6
Cannot be identified. Therefore, when the isel instruction of the node is executed after the isel instruction of the node shown in FIG. 2, the ALU 9 executes the following processing.

That is, when the ALU 9 executes the node operation, it outputs the operation result of N # 5, G / C0, and data 3 to the buffer 11, as shown in FIG. The program control unit 6 fetches the data of N # 7, TAG * R corresponding to the key code of N # 5, G / C0. On the other hand, the ALU 9 executes the isel operation processing at the node, then executes the isel operation processing at the node, and outputs the operation result N # 6, G / C0, and data 4 to the buffer 11.

By the way, the program control unit 6 tries to fetch the corresponding program data by using N # 5, G / C0 of the first operation result as a key code. Since it cannot be distinguished from N # 6, external program memory 2 with N # 6, G / C0 as a key code is added to the program data given from external program memory 2 with N # 5, G / C0 as a key code.
Since the next program data given by the above is written, the program control unit 6 cannot fetch the normal data corresponding to the key code of N # 5, G / C0, resulting in a mishit. Even in such a case, it is necessary to operate normally.

Therefore, in this example, when a mishit occurs, the program control unit 6 sets a mishit flag 3 in the program data as shown in FIG. 9 to indicate that a hash collision has occurred. The pair-to-data detector 7 does not close the contact 8 when the program data has a mishit flag. Therefore, the program data output from the paired data detection section 7 is given only to the external program memory 2 and not to the ALU 9.

As shown in FIG. 9, the external program memory 2, based on the key code N # 5, G / C0 of the program data given from the paired data detection unit 7, sends the node command as shown in FIG. Program data for execution N # 7, G / C
Not only 0, TAG * L is read, but also data 3 and flag 3 to be operated are read.

That is, in this example, when the program control unit 6 makes a mishit, the external program memory 2 is directly accessed, and data is also given to the program control unit 6 together with the next instruction.

The program data of the node read from the external program memory 2 is given to the program control unit 6. Since the data is also added to this program data,
The data is passed through the program control unit 6 according to the mishit flag and given to the paired data detection unit 7. Pair data detector 7
Waits until the data to be paired with the program data is input. After the program data of the node is directly read from the external program memory 2, the program data N # 6, G / C0, TAGR and flag 0 of the node are input to the program control unit 6 as shown in FIG.

The program control unit 6 uses N # 6, G / C0 as a key code,
Fetch program data of N # 7, TAG * R. This program data is given to the paired data detector 7.
The paired data detection unit 7 detects that two pieces of data necessary for executing the operation in the node are gathered, closes the contact 8 again, and gives the two program data to the ALU9,
Perform arithmetic processing.

Thereafter, the same operation is performed, and based on the operation result of the node and the program data input in the node C, the operation process for addition in the node is performed, and the node u
Is output to.

11A and 11B are specific block diagrams of the program control unit according to the embodiment of the present invention.

First, with reference to FIGS. 11A and 11B, the configuration of the program control unit 6 and the operation thereof when the program data input from the outside are loaded into the external program memory 2 and the memory array 49 will be described. Although the program data is serially input from the outside, all the program data are loaded into the external program memory 2, and the initial 1k word of the program data is also loaded into the memory array 49.

The program data includes any instruction of ULD, LDI, and LDX. ULD means unload and represents a normal execution state. LDI is an instruction to load the initial 1k word of program data into the memory array 49, and LDX is an instruction to load the remaining program into the external program memory 2. Program data including such an instruction is given to the input port 11.
The input port 11 sends a selection signal to the route selection unit according to each instruction.
Give to thirteen. Further, the input port 11 decodes the address of the inputted program data, and when it detects the address of 1k word, gives a detection signal to the input / output port 32.
Input port 11 sequentially latches program data in data latch 12
Give to. The data latch 12 is configured to output data by a so-called handshake method of shifting data according to the fact that the previous stage is in an empty state,
Each of the data latches 15, 18, 20 ... Described below is similarly configured.

The program data output from the data latch 12 is given to the path selection unit 13. The path selection unit 13 selectively outputs the program data to the merging unit 14 or the data latch 33 according to the selection signal given from the input port 11. That is, if the instruction included in the program data is ULD, the normal execution processing is performed, so the input data packet is output to the confluence unit 14, and if the instruction is LDI or LDX, the program data is stored in the external program memory. The program data is output to the data latch 33 for loading into 2. The data latch 33 latches the program data and then supplies the program data to the input / output port 32. The input / output port 32 outputs the program data to the outside and supplies it to the external program memory 2 and also outputs it to the data latch 34. When the input port 11 detects an address exceeding 1 k word, the input / output port 32 outputs the program data only to the external program memory 2 and does not output it to the data latch 34.

The instruction packet read from the external program memory 2 is given to the input / output port 32. The program data latched by the data latch 34 is output to the path selection unit 35. The path selection unit 35 selectively branches the program data into the branch unit 36 or the merge unit 14. That is,
When the program data to be uploaded to the cache memory or the initial load data from the outside is given, the input data packet is output to the branch unit 36, and when the data packet fetched by the external program memory 2 is given, it merges. Branch to section 14.

Upon receiving the data packet, branching unit 36 causes data latch 42 to latch the key data composed of the combination of N # and G / C included in the data packet as write address information, and N #, included in the data packet. The write data composed of TAG is latched by the data latch 37. Data latch 42
The latched write address information of the
Latched to 43. A copy address is generated by a copy address generation unit 44 based on the write address information latched in the data latch 43, and key data composed of G / C and N # is used as a part of the write data in the data latch 45.
The key code as the address information is latched by the data latch 46.

On the other hand, the write data latched by the data latch 37 is latched by the data latch 38, and this write data and a part of the write data latched by the data latch 45 are latched by the write data latch 39. The write data latched by write data latch 39 is applied to write / read controller 50.

On the other hand, the write address information latched by the data latch 46 is given to the write / read arbitration control unit 47. As will be described later, read / write arbitration control unit 47 is also supplied with read address information from data latch 20. Then, the write / read arbitration control unit 47 selects the write address information or the read address information, whichever comes first, and gives it to the decoder 48.
The write / read arbitration control unit 47 outputs the write address information to the decoder 48 and then the read address information when the write address information is given and subsequently the read address information is given. Output to. The decoder 48 decodes the write address information and the read address information, and supplies the column address information and the row address information to the memory array 49. Then, in the memory array 49,
Write data is written in the memory cell addressed by the write address information.

By the above-mentioned operation, 1 k word of program data is written in the memory array 49, and when the input port 11 detects the 1 k word address, the input / output port 32 thereafter outputs the program data only to the external program memory 2, It is not output to the data latch 34. As a result, all program data are loaded into the external program memory 2.

Next, an actual program execution procedure will be described. An input data packet is given to the input port 11. This input data packet contains instructions that indicate normal execution status.
Contains ULD. The input port 11 determines that it is unloaded by the instruction ULD, and switches the route selection unit 13 to the merging unit 14 side. Then, the input data packet is given only to the merging unit 14 via the data latch 12 and the route selecting unit 13,
It is not output to the data latch 33 side. The merging unit 14 causes the data latch 15 to latch the input data packet if the next-stage data latch 15 is in an empty state. Data latch
The input data packet latched by 15 is supplied to branching unit 16, and N # and G / included in the input data packet are included.
The key code consisting of C and the operand data are branched,
The key code is latched in the data latch 18 and
It is given to the mode control unit 17. Operand data latched in data latch 28 is transferred to data latches 29, 30 and 3
Sequentially transmitted to 1.

The mode control unit 17 reads a 1k word program loaded in the memory array 49, and responds based on a key code and a dump mode for dumping to determine whether the program data is normal or not. The read mode for reading an instruction from the memory array 49 is set. If the read mode is set by the mode control unit 17, the key code latched by the data latch 18 is given to the copy address generation unit 19, and different instructions are fetched for the same address information based on the key code. To do so, a copy address is generated and the same address information is sequentially latched in the data latch 20. The address information latched in the data latch 20 is given to the write / read arbitration control unit 47 and also latched in the data latch 21.

The write / read arbitration control unit 47 determines which of the read information given from the data latch 20 and the write address information given from the data latch 46 arrives earlier, and the read address information arrives first. If so, the address information is given to the decoder 48. The decoder 48 decodes the read address information and designates a predetermined address of the memory array 49. Then, from the designated address of the memory array 49, N #, G / C included in the input data packet
The program data of the instruction corresponding to is read and latched in the read data latch 40. This read data is applied to the instruction fetch control logic unit 23 and also latched in the data latch 41.

On the other hand, the key code latched by the data latch 21 is latched by the data latch 22, and the latch output is given to the instruction fetch control logic unit 23 and the data latch 24.
Latched on. The instruction fetch control logic unit 23 includes a key code given from the data latch 22 and a read data latch 40.
If the key code read from the memory array 49 latched in the memory array is compared and it is determined that they match, the program data is read again from the memory array 49 following the key code. If the flag to be read is set, the read data latched in the data latch 41 is selected by the output port selection unit 25 and output to the output port 26. Further, the subsequently read program data is output to the output port 27 via the output port selection unit 25.

If a hash collision occurs in the memory array 49 due to a miss hit for a predetermined instruction, a key based on the read key code latched in the read data latch 40 and the input data packet latched in the data latch 22. Since the codes do not match, the instruction fetch control logic unit 23 gives a mismatch signal to the output port selection unit 25. The output port selection unit 25 determines that a hash collision has occurred in response to the non-coincidence signal, and latches the data.
Without outputting the read data latched in 41,
The key code latched in the data latch 24 and the operand data latched in the data latch 31 are selected and output to the output port 26.

Next, when the execution packet of the next instruction fetched by the external program memory 2 is given to the input / output port 32, the input / output port 32 data latches the execution packet.
Let 34 latch.

The execution packet latched by the data latch 34 is given to the route selection unit 35. When the path selection unit 35 determines that the execution packet has been fetched from the external program memory 2 according to the mishit flag, it outputs the execution packet to the merging unit 14 and causes the data latch 15 to latch it. The branching unit 16 branches the key code and operand data of the execution packet, causes the data latch 18 to latch the key code, and causes the data latch 28 to latch the operand data. In this case, since it is not necessary to read the program data from the memory array 49, the key code is the data latch 18, the copy address generator 19, the data latches 20, 21, 22.
And is passed through 24 and given to the output port selection unit 25,
Operand data is from data latch 28 to data latch 2
It is passed through 9, 30, and 31 and given to the output port selection unit 25. Then, the output port selection unit 25 outputs the key code and the operand data to the output port 26.

[Effects of the Invention] As described above, according to the present invention, when a data flow program is given from the outside, the program is uploaded to the external program storage unit, and when the execution packet is given from the outside, the execution is executed. For the address information contained in the packet, the next different instruction is accessed twice in succession to the cache memory, and the fetched instruction is output. If the cache memory misses, the external program By fetching and outputting the processed data together with the next instruction to the storage unit, the instruction fetch can be efficiently executed without waste by the cache program memory and the external program memory.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an information processing apparatus to which the present invention is applied. FIG. 2 is a diagram showing an example of a program processed by the information processing apparatus shown in FIG. FIGS. 3 to 10 are diagrams for explaining the execution procedure when the information processing apparatus shown in FIG. 11A and 11B are concrete block diagrams of an embodiment of the present invention. In the figure, 1 is an information processing device, 2 is an external program memory, 6 is a program control unit, 7 is a pair data detection unit, and 8 is a data detection unit.
Is a contact, 9 is an ALU, 11 is an input port, 12,15,18,20,21,2
2,24,28,29,30,31,33,34,37,38,41,42,43,45,46 are data latches, 13,35 are route selectors, 14 are merge sections, 16,36 are Branching unit, 19 and 44 copy address generating unit, 23 instruction fetch control logic unit, 25 output port selecting unit, 26 and 27 output ports, 32 I / O port, 39 write data latch, 40 read A data latch, 47 is a write / read arbitration control unit, 48 is a decoder, 49 is a memory array, and 50 is a write / read control unit.

Claims (1)

[Claims] 1. A program control unit that stores a data flow program and fetches instructions in accordance with an execution packet, and paired data that determines that paired program data and processed data have been input from the program control unit. A detection unit, an arithmetic processing unit for executing an arithmetic operation based on the program data and the processed data in response to the detection of the paired program data and the processed data by the paired data detection unit, and the program control unit In an information processing device including an external program storage unit for giving program data to the, the program control unit, an input means to which a data flow program for loading an execution packet or a path of the external program storage unit from the outside is given, Data flow program input to the input means Data flow program to the external program storage unit, to input the data flow program read from the external program storage unit, or to input the execution packet fetched by the external program storage unit Alternatively, each time an execution packet is input asynchronously, input / output control means for controlling the output destination based on the information contained therein, storing the data flow program, and outputting the corresponding program data according to the execution packet Cache memory, first control means for accessing the cache memory according to address information included in the packet input from the input means or the input / output control means, packet input from the input means or the input / output control means Address information contained in On the other hand, second control means for accessing the cache memory at least twice in succession and outputting it together with copy information, and execution packets fetched in the cache memory and the external program storage input from the input / output control means. An output control means for asynchronously and selectively controlling the output of the execution packet fetched by the unit every time data is input according to the copy information, and the data read from the cache memory and the packet data input from the outside. A memory access control device characterized in that an instruction to be executed next is fetched based on the comparison, collation, and judgment of.