JPH0744276B2 - MIS type semiconductor device - Google Patents

Description

The present invention relates to a MIS type semiconductor device, and more particularly to an LDD (Lightl)
The present invention relates to an MIS type semiconductor device having a y Doped Drain structure.

(B) Conventional technology As LSI and DRAM have become highly integrated,
Although the breakdown voltage of the MIS type semiconductor device used in them and the reliability due to hot carriers have deteriorated, in order to solve these problems, as shown in FIG. Also, an MIS type semiconductor device having an LDD structure having a double structure of a high concentration diffusion region has been developed and put into practical use.

In the figure, 13 is a gate electrode, which is provided on the surface of the p-type silicon substrate 11 with an insulating film 12 interposed therebetween. A low concentration n-type diffusion region 14 is formed by ion implantation using the gate electrode 13 as a mask. The high-concentration n diffusion region 16 joined to the low-concentration n-type diffusion region 14 is formed by ion implantation using the gate electrode 13 provided with the sidewall 15 as a mask after the sidewall 15 is formed on the gate electrode 13. It is formed. Then, by the two regions of the low concentration and high concentration n-type diffusion regions 14 and 17, the source region 1
7 and a drain region 18 are formed. In this example, the diffusion length in the depth direction of the low concentration n-type diffusion region 14 does not exceed the diffusion length in the depth direction of the high concentration n-type diffusion region 16.

(C) Problems to be Solved by the Invention However, although the low-concentration n-type diffusion region of the LDD structure can suppress the generation of hot carriers by relaxing the drain electric field, on the other hand, it is parasitic due to the low-concentration n-type diffusion region. There is a problem that the current driving capability is reduced due to the increase in resistance. Further, in the MIS type semiconductor device used in the DRAM and the like, there is a problem that the breakdown voltage of the source / drain junction is deteriorated as the miniaturization thereof progresses and the concentration of the semiconductor substrate increases.

The present invention has been made in view of the above circumstances. It is possible to prevent the generation of hot carriers, prevent the current driving force from decreasing due to an increase in parasitic resistance, and prevent the breakdown voltage of source / drain junctions from being deteriorated. It is intended to provide an MIS type semiconductor device.

(D) Means for Solving the Problems According to the present invention, a gate electrode is provided on the first conductivity type semiconductor substrate via an insulating film, and the gate electrode and the side surface portion of the gate electrode are formed. In the MIS type semiconductor device having a source region and a drain region formed by ion implantation using the sidewalls as a mask, the source region and the drain region are each formed by ion implantation using the gate electrode as a mask. Two
A first impurity diffusion layer having a higher concentration than the impurity concentration of the first impurity diffusion layer formed in the first impurity diffusion layer by ion implantation using the conductive type first impurity diffusion layer, the gate electrode and the sidewall as a mask. The impurity concentration of the second conductivity type second impurity diffusion layer is higher than that of the second impurity diffusion layer formed in the second impurity diffusion layer by ion implantation using the gate electrode and the sidewall as a mask. It has a three-layer structure including a third impurity diffusion layer of the second conductivity type, and a boundary surface between the semiconductor substrate and the first impurity diffusion layer is formed by the first impurity diffusion layer and the second impurity diffusion layer. It is located on the channel side with respect to the channel direction with respect to the boundary surface and deeper with respect to the depth direction, and the boundary surface between the first impurity diffusion layer and the second impurity diffusion layer is the above. Second non The interface between the pure substance diffusion layer and the third impurity diffusion layer is located on the channel side in the channel direction and deep in the depth direction, and at least the first impurity diffusion layer is located. There is provided a MIS type semiconductor device characterized in that a boundary surface between the layer and the second impurity diffusion layer is directly under the side walk.

(E) Action Since the first, second, and third impurity diffusion layers have higher impurity concentrations in this order, they alleviate the electric field of the junction in the depth direction and the lateral direction. This improves the junction breakdown voltage and suppresses the generation of hot carriers.

In addition, the second impurity diffusion layer reduces the parasitic resistance of the source region and the drain region, thus improving the driving capability.

(F) Embodiment Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, but the present invention is not limited to the following embodiments.

In FIG. 1, reference numeral 1 denotes a first conductivity type semiconductor substrate (hereinafter referred to as a substrate), which is made of, for example, p-type silicon. A gate electrode 3 is provided on the surface of the substrate 1 with a gate oxide film 2 which is an insulating film interposed therebetween. Reference numeral 4 is a sidewall formed on the side surface of the gate electrode 3.

5 is a source region, 6 is a drain region,
It is formed so as to sandwich the channel region 7 directly below the gate electrode 3. The source region 5 and the drain region 6 respectively include a first impurity diffusion layer 8, a second impurity diffusion layer 9 having a higher concentration than the impurity concentration of the first impurity diffusion layer 8 formed in the first impurity diffusion layer 8, The third impurity diffusion layer 10 is formed in the second impurity diffusion layer 9 and has a concentration higher than that of the second impurity diffusion layer 9. Each impurity diffusion layer 8,9,
10 is formed by ion-implanting impurities of a conductivity type different from that of the substrate 1.

The second impurity diffusion layer 9 is formed without exceeding the diffusion length in the depth direction and the diffusion length in the lateral direction of the first impurity diffusion layer 8. Similarly, the third impurity diffusion layer 10 is formed without exceeding the diffusion length in the depth direction and the diffusion length in the lateral direction of the second impurity diffusion layer 9.

In FIG. 1, the source electrode, the drain electrode,
Further, since electrode wirings for them may have a known structure, their illustration is omitted.

Next, the structure process of this embodiment will be described with reference to FIG.

First, as shown in FIG. 2 (a), a gate oxide film 2 having a thickness of 200 Å and a thickness of 3500 are formed on a p-type silicon substrate 1.
After depositing the n-type polycrystalline silicon film of Å, the gate electrode 3 is formed by the photoetching technique. Then, using the gate electrode 3 as a mask, phosphorus is ion-implanted under the conditions of an acceleration voltage of 70 KeV and a dose amount of 3 × 10 ¹³ cm ^-2 , and activation is performed at a temperature of 950 ° C. for 30 minutes to perform self-alignment. The first impurity layer 8 is formed.

Although the n-type polycrystalline silicon film is used as the material of the gate electrode 3 in this embodiment, a polycide film or a p-type polycrystalline silicon film may be used.

Then depositing an SiO ₂ film having a thickness of 2500Å on the entire surface, subjected to the entire surface is etched by reactive ion etching, as shown in FIG. 2 (b), made of SiO ₁ adjacent to the gate electrode 3 side The wall 4 is formed.

Then, using the gate electrode 3 and the sidewall 14 as a mask, phosphorus is used as an accelerating voltage as shown in FIG.
Arsenic with a diffusion coefficient of 50 KeV and a dose of 2 × 10 ¹⁴ cm ^-2 and a smaller diffusion coefficient than phosphorus is used at an acceleration voltage of 50 KeV and a dose of 5 × 10 ¹⁵ c.
Double ion implantation is performed under the condition of m ⁻² , and diffusion is performed for 40 minutes at a temperature of 900 ° C. to perform double diffusion to form the second impurity diffusion layer 9 and the third impurity diffusion layer 7.

By forming through the above steps, the first to third impurity diffusion layers 8, 9 and 10 have the second impurity diffusion layer 8 and the second impurity diffusion layer 8 each having a lower impurity concentration than the second impurity diffusion layer 9. The concentration of the diffusion layer 9 can be set lower than the concentration of the third impurity diffusion layer 10. Further, the lateral diffusion length of the second impurity diffusion layer 9 does not exceed the lateral diffusion length of the first impurity diffusion layer 8,
The lateral diffusion length of the second impurity diffusion layer 9 is set to the third impurity diffusion layer.
It can be set not to exceed the lateral diffusion length of 10. In addition, the depth-direction diffusion length of the third impurity diffusion layer 10 does not exceed the depth-direction diffusion length of the second impurity diffusion layer 9, and the depth-direction diffusion length of the first impurity diffusion layer 8 is equal to the second impurity diffusion layer. The depth direction diffusion length of 9 can be set so as not to exceed.

In this embodiment, the simultaneous ion implantation and the simultaneous diffusion are performed to form the second diffusion region and the third diffusion region, but the ion implantation and the diffusion may be performed separately.

Further, in the above-mentioned embodiment, the example applied to the n-channel MOS IC has been described, but it goes without saying that it can also be applied to the CMOS IC and the like.

(G) Effect of the Invention According to the present invention, a MIS with a high breakdown voltage and a high driving capability is provided.
Type semiconductor device is obtained.

That is, by forming the source and drain regions by stacking three impurity diffusion layers whose impurity concentrations are sequentially reduced from the surface of the semiconductor substrate toward the inside thereof, the electric field of the junction in the depth direction of each region is formed. Is relaxed, the junction breakdown voltage is improved, and the electric field of the junction in the lateral direction is also relaxed, so that the generation of hot carriers is suppressed and the reliability is also improved.

Further, the introduction of the second impurity diffusion layer having a medium concentration reduces the parasitic resistance of the source and drain regions, so that the driving ability is improved.

[Brief description of drawings]

FIG. 1 is a longitudinal sectional view showing the structure of an embodiment of the present invention, and FIG.
FIG. 3 is a process drawing for explaining the process of manufacturing the embodiment, and FIG. 3 is a vertical sectional view showing the structure of the conventional example. 1 ... First conductivity type semiconductor substrate, 2 ... Gate oxide film, 3 ... Gate electrode, 4 ... Side wall, 5 ... Source region, 6 ... Drain region, 8 ... First impurity diffusion layer, 9: second impurity diffusion layer, 10: third impurity diffusion layer.

Claims (1)

[Claims] 1. A gate electrode provided on a first conductivity type semiconductor substrate via an insulating film, and formed by ion implantation using the gate electrode and a sidewall formed on a side surface of the gate electrode as a mask. A source region and a drain region, the source region and the drain region are each a second conductivity type first impurity diffusion layer formed by ion implantation using the gate electrode as a mask, A second conductivity type second impurity diffusion layer having a higher concentration than the impurity concentration of the first impurity diffusion layer formed in the first impurity diffusion layer by ion implantation using the gate electrode and the sidewall as a mask. , The second impurity diffusion layer formed in the second impurity diffusion layer by ion implantation using the gate electrode and the sidewall as a mask. It has a three-layer structure including a second conductivity type third impurity diffusion layer having a higher concentration than the diffusion layer impurity concentration, and the interface between the semiconductor substrate and the first impurity diffusion layer is the first impurity diffusion layer. Is located on the channel side with respect to the channel direction and deeper with respect to the depth direction than the boundary surface between the first impurity diffusion layer and the second impurity diffusion layer. The boundary surface with the impurity diffusion layer is located on the channel side with respect to the channel direction and deeper with respect to the depth direction by the boundary surface between the second impurity diffusion layer and the third impurity diffusion layer. The MIS type semiconductor device is characterized in that at least the boundary surface between the first impurity diffusion layer and the second impurity diffusion layer is directly below the side walk.