JPH0745543A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding a method for manufacturing a semiconductor device including a step of forming an organic silicon film by a CVD method, it is possible to stably control the speed and taper angle during wet etching.
Provided is a method for manufacturing a semiconductor device, which can improve the electrical characteristics (insulating property) of an organic silicon film and can improve the film quality of the organic silicon film even at low temperature heat treatment. [Structure] An organic silicon film obtained from TEOS or the like is used as C
Step I of forming by the VD method and Step I of implanting inert ions such as Ar ions by an ion implantation method with a structure having a range at one third or more of the thickness of the organic silicon film.
A method of manufacturing a semiconductor device, which includes I, step III of performing annealing, and step IV of etching the organic silicon film by wet etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method for manufacturing a semiconductor device including a step of forming organic silicon by a CVD method.

[0002]

2. Description of the Related Art Conventionally, when manufacturing a semiconductor device having an organic silicon film, the organic silicon film is generally subjected to CVD.
Formed by a method to strengthen the organic silicon film (Densi
After performing fy), by photolithography technology,
A resist is left in the non-etched portion as a mask during wet etching, and the organic silicon film is etched and patterned by hydrofluoric acid-based wet etching. However, in such a conventional technique, the etching rate of the organic silicon film during etching is twice or more that of the thermal oxide film, and the variation in etching in the silicon substrate wafer is as large as 15% or more, and the shape (taper angle) after etching is large. It was a factor that caused variations in dimensions and dimensions. Further, this may cause deterioration of the film quality of the formed organic silicon film, and the electrical characteristics (insulating property) may be deteriorated.

[0003]

It is an object of the present invention to solve the above problems of the prior art and to provide a method for manufacturing a semiconductor device including a step of forming an organic silicon film by a CVD method, in which the speed and taper angle during wet etching are stably controlled. It is possible to improve the electrical characteristics (insulating property) of the organic silicon film, and to improve the film quality of the organic silicon film even at low temperature heat treatment. To do.

[0004]

According to the invention of claim 1 of the present application, a range is provided at a step of forming an organic silicon film by a CVD method and at a position of 1/3 or more of the film thickness of the organic silicon film. A method of manufacturing a semiconductor device, which has a configuration having, and includes a step of implanting inert ions by an ion implantation method, a step of performing annealing, and a step of etching the organic silicon film by wet etching. This achieves the above-mentioned object.

The invention of claim 2 of the present application is the method of manufacturing a semiconductor device according to claim 1, wherein the organic silicon film is a film formed of TEOS and the inert ions are Ar ions. Therefore, the above object is achieved thereby.

The structure of the present invention will be described below with reference to FIG. That is, the method for manufacturing a semiconductor device according to the present invention comprises a step I of forming an organic silicon film by a CVD method, and a structure having a range at a position of 1/3 or more of the film thickness of the organic silicon film. Step II of implanting by the ion implantation method and Step I of performing annealing
II, and a step IV of etching the organic silicon film by wet etching.

In the present invention, the organic silicon film means a film obtained from an organic silicon compound as a raw material.
TEOS is typically used as the organic silicon compound.
(Tetraethoxyoxysilane), other, DA
DBS (deacetoxy / tertiary-ptoxysilane
diacetoxyditertiarybutoxy silane), TMCTS
(Tetramethylcyclotetrasilane), DES (diethylsilane), and the like, which are gases that are compounds having silicon and an organic group in the molecule. Such compounds are also attracting attention because of their good flattening performance and coating property (Nikkan Kogyo Shimbun, article on March 2, 1990, and 1988 Spring Society of Applied Physics, Proceedings 30p-V-11, Akahori). Report,
SEMICONDUCTOR INTERNATIONAL, MARCH 1990, P82-85 Paper "Selecting An Organosilicon Source For LPCVD O
See xide).

[0008]

FIG. 2 shows ion implantation energies of depths of 50 nm, 100 nm, 150 nm and 17 for a sample in which an organic silicon film is formed by TEOS to a film thickness of 300 nm.
It is the figure which investigated by carrying out the experiment so that an ion might be injected into a 0 nm place, and investigated the etching rate in that case. The ion implantation was performed by implanting Ar ⁺ which is an inert ion. De
Nsfy was performed at 900 ° C. for 30 minutes in a nitrogen atmosphere.

From FIG. 2, one third of the film thickness (300 nm)
If the range has a range above 100 nm, that is, 100 nm, 150 nm, or 170 nm is ion-implanted, below the range (50 nm)
In comparison with the above, it is understood that a uniform etching rate can be obtained with a critical meaning regardless of the etching time.

Although the operation of the present invention is not always clear, it is supported by the data as described above. According to the data in FIG. 2, at 50 keV the surface (~ 1
It is considered that the film quality is improved only up to near (00 nm). As described above, it is understood that the effect can be obtained by performing ion implantation so that the range is provided at a position of 1/3 or more of the film thickness.

FIG. 3 shows the ion implantation energy and etching rate of the sample of the organic silicon film (thickness: 300 nm) formed by TEOS, and Dens after annealing.
It is the figure which described the relationship of the ify rate.

FIG. 4 is a diagram showing the relationship between Densify (30 minutes in N ₂ ) temperature, etching rate, and uniformity for a sample having a TEOS film thickness of 300 nm.
Raising the Densify temperature, for example from 900 ℃ to 1
If the temperature is raised to 000 ° C, the etching rate will slow down,
It alone cannot improve the etching uniformity.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. It should be understood that the present invention is not limited to the illustrated embodiments.

Embodiment 1 This embodiment is an NPN of a normal Bip (bipolar) IC.
The present invention is applied to a transistor, and the present invention will be described by taking this as an example.

Referring to FIG. As shown in FIG. 5, the collector 1 and the base 2 are formed by using a known technique. A thin thermal oxide film 3 is attached to the silicon surface. In the figure, 11 is a substrate (particularly a P-type Si substrate), 12 is an N ⁻ epitaxial layer, 13 is an N ⁻ buried layer, and 14 is an element isolation isolation region.

Next, as shown in FIG. 6, a resist 4 is formed by a photolithography technique, an opening is formed in the resist 4, and the ion is used as a mask for ion implantation II.
Do ₁

After removing the resist 4 of FIG. 6, an organic silicon film 5 is formed by the CVD method as shown in FIG.

One third of the thickness of the organic silicon film 5 in FIG.
Inert ions are implanted by the ion implantation method so as to have the above range. This is shown in FIG. In FIG. 8, reference numeral II ₂ indicates this ion implantation.

After that, an annealing process is performed for forming the emitter and also for the Densify of the organic silicon film 5 (FIG. 9).
reference).

In order to form an electrode, the resist 6 is opened by a photolithography technique, and the organic silicon film 5 and the thin thermal oxide film 3 are wet-etched with a hydrofluoric acid system using the resist as a mask. This gives the structure of FIG.

After the wet etching shown in FIG. 10, the resist 6 is used.
Is peeled off, an electrode is formed of aluminum 7 or the like by using a known technique, and an NPN transistor is completed as shown in FIG.

The photolithography technique, the formation of the diffusion region, the ion implantation, the etching and the like in each of the above steps should be carried out by appropriately adopting the means usually used for forming this kind of semiconductor device. You can

In this embodiment, the speed and taper angle during wet etching could be controlled stably.
In addition, the electrical characteristics (insulating property) of the organic silicon film could be improved. It was possible to improve the quality of the organic silicon film even by the low temperature heat treatment.

The present structure can be applied to formation other than the electrodes, and is effective not only for wet etching but also for dry etching. Further, it is effective in improving the film quality of the organic silicon film without etching.

[0025]

According to the present invention, the organic silicon film is CV-coated.
In the method of manufacturing a semiconductor device including the step of forming by the D method, the speed and taper angle during wet etching can be stably controlled, and the electrical characteristics (insulating property) of the organic silicon film can be improved. It was possible to provide a method for manufacturing a semiconductor device in which the film quality of an organic silicon film can be improved even by low-temperature heat treatment.

[Brief description of drawings]

FIG. 1 is a flow chart illustrating a process of the present invention.

FIG. 2 is an operation explanatory view.

FIG. 3 is an operation explanatory view.

FIG. 4 is an operation explanatory view.

5A to 5C are sectional views showing the steps of Example 1 in order (1).

FIG. 6 is a sectional view showing the steps of Example 1 in order (2).

7A to 7C are sectional views showing the steps of Example 1 in order (3).

FIG. 8 is a sectional view showing the steps of Example 1 in order (4).

9A to 9C are sectional views showing the steps of Example 1 in order (5).

FIG. 10 is a sectional view showing the steps of Example 1 in order (6).

FIG. 11 is a sectional view sequentially showing the steps of Example 1 (7).

[Explanation of symbols]

 I CVD process of organic silicon film II Ion implantation process of inert ions III Annealing process IV Etching process of organic silicon film

Claims (2)

[Claims] 1. A step of forming an organic silicon film by a CVD method, and a step of implanting inert ions by an ion implantation method with a range having a range at a third or more of the thickness of the organic silicon film. And a step of annealing, and a step of etching the organic silicon film by wet etching, a method of manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the organic silicon film is a film formed of TEOS, and the inert ions are Ar ions.