JPH0746315B2 - Instruction prefetch control method for computer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction reading control method for an electronic computer, and more particularly to an instruction reading method for an electronic computer provided with a main memory and a buffer memory for storing a copy of a part of its contents. The present invention relates to a prefetch control method.

[Conventional technology]

There is a buffer storage method as one method for speeding up the processing in an electronic computer. In this method, a copy of a part of an instruction or data on the main memory is stored in a high-speed buffer memory and then read out from the desired instruction or buffer memory. If the target instruction or data does not exist in the buffer memory, block transfer is performed from the main memory to the buffer memory.

As another method of speeding up the processing in the electronic computer, there is an instruction prefetching method. In an electronic computer equipped with the buffer memory, the instruction prefetching is performed in the buffer memory. For the prior art of this type of instruction look-ahead system, see, for example, “Nikkei Electronics” December 24, 1979, pages 104 to 130, “The fastest commercial general-purpose computer with an enhanced pipeline system with the help of LSI technology. It is described as ".

[Problems to be solved by the invention]

In the conventional instruction prefetching method, as seen in the above-mentioned document, many registers, half-cycle switching control of buffer memory, complicated control, etc. are required, and there are problems of cost and development difficulty.

SUMMARY OF THE INVENTION An object of the present invention is to realize a prefetch control of an instruction having high performance with a small amount of metal and a simple control in an electronic computer equipped with a buffer memory.

[Means for solving problems]

The present invention reads the instruction from the buffer memory when the instruction to be read exists in the buffer memory, but when the instruction to read from the buffer memory does not exist, the instruction to read from When the preceding instruction is not being processed, block transfer from the main memory to the buffer memory is activated, and when an instruction preceding the instruction to be read is being processed, block transfer is not activated and reading is disabled. To do.

[Action]

When the instruction read target instruction exists in the buffer memory, even if the preceding instruction is being processed, the instruction is prefetched from the buffer memory through the buffer memory access gap of the instruction operand read during the processing. On the other hand, if there is no instruction read target instruction in the buffer memory, block transfer from the main memory to the buffer memory is required. However, if the block transfer is executed, the preceding instruction is being processed. In this case, prefetching of an instruction is disabled without performing block transfer, and if the preceding instruction is not being processed, block transfer is executed to prefetch the instruction.
However, when the preceding instruction is a branch instruction, if the branch destination instruction that is the target instruction of the branch instruction does not exist in the buffer memory, the block transfer of the branch destination instruction is executed during the processing of the branch instruction. As a result, the pre-reading process of a command with good performance is realized with a small amount of metal and simple control.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. 1 in the figure
Shows a block diagram of an embodiment of the present invention. In the figure, 1 is a main memory, 2 is a fast access time buffer memory (BS) that stores a copy of the main memory 1, 3 is an address array (AA) that holds the registered address of BS2, and 4 and 5 are both 8 bytes. Instruction buffer register (IBRA, IBRB), 6
And 7 are validity indicators (IBVA, IBVB) of IBRA4 and IBRB5. 80 is an operand buffer register (OBR).
8 is an instruction cutout circuit, 16 is an instruction cutout pointer (IP),
Reference numeral 9 is a 4-byte instruction register (IR) that holds the cut out instruction. 10 is the instruction address register (NIA), 11
Is the incrementer (INC
A) and 12 indicate an incrementer (INCB) that updates the NIA 10. 14 is an operand address register (ADR). 1
7 is an operand address control circuit. Reference numeral 50 indicates a control circuit (ICTL) that controls the instruction processing, and 51 indicates a control circuit (BCTL) that controls AA3 and BS2. Reference numeral 70 is a decode success indicator (TS) under the block transfer of the instruction.

Next, the operation will be described with reference to FIG. Figure 2 (a) is 4
Indicates that a byte length instruction is stored in the main memory 1. This copy is also included in BS2, and the address is registered with AA3.

Now, the case where the instruction address is set to NIA10 and the address 100 is set as the initial value and the instruction execution is started will be described.

In the initial state, both IBVA6 and IBVB7 are “0”. IBR
Both A4 and IBRB5 are empty. The instruction reading stage of FIG. 2C is activated by the start instruction. That is, IC
At TL50, INCA the contents of NIA10 (containing 100 addresses)
The addition (NIA + 0 in this case) of FIG. 2 is performed at 11 and the control is performed to send this address (address 100) to AA3 via line 22 via the selector 15. At the same time, ICT
An instruction read instruction (AI instruction) is issued from L50 to BCTL51 via control line 60. In response to this, the BCTL 51 refers to AA3 at the address. In addition, the bit value indicating even / odd in units of 8 bytes of the address line 22 is set to the flip-flop IFP1.
Set to 3. (In this case, since the address is 100, the IF
P13 becomes “0”. ) The above is the operation of the AI stage in the first cycle of FIG. In the cycle, the operation of the LI stage is performed. In this stage, the ICTL50 gives BCTL51 instructions for the LI stage. In response to this, the BCTL51 reads 8 bytes of the instruction from BS2 if 100 is registered in AA3 based on the reference result of AA3 in the AI stage,
Send to BRA44 and IBRB5. At the same time, it will be reported to ICTL 50 via line 61. As a result, the ICTL50 fetches 8 bytes of data into IBRA4 according to the value of IFP13 set in advance (“0” in this case), and simultaneously sets IBVA6 to “1”.

If the address 100 is not registered in AA3, the BCTL 51 sends the address to the main memory 1 and transfers the block from the main memory 1 to BS2. Then, the address is registered in AA3. During this time, a block transfer instruction from BCTL51
ICTL50 suspends operation. This block transfer will be described later in detail.

As described above, an 8-byte instruction is set in IBRA4 by the AI-LI stage.

On the other hand, at the same time as the start, in the ICTL50, the D stage from the cycle is activated as shown in FIG. This is the instruction decoding stage, and the instruction cutout circuit 8 from IBRA4, IBRB5 according to the instruction cutout pointer IP16.
At, the instruction (instruction (1)) is cut out and set in IR9, and its operand is sent to the address control circuit 17, in which the operand address is calculated and the result is set in ADR14. In this D stage, since the instruction reading is not successful in the cycle, the D stage fails. The same applies to cycles. Then, the D stage succeeds in the cycle after the instruction is taken into IBRA4. At this time, since the IP16 is in the initial state “0” (because it starts at address 100), the first 4 bytes of IBRA4 are cut out and set to IR9. After this cutout, the IP16 is updated by the instruction length and set to "4".

In ICTL50, the D stage of the cycle was successful, so
In the cycle, the A stage is activated. That is, the operand address is sent from the ADR 14 to the AA 3 via the selector 15. At the same time, the BCTL 51 is instructed to perform the A operation. In BCTL51,
The reference operation of AA3 at the address is performed. In the next cycle, the L operation is instructed from ICTL50 to BCTL51. In BCTL51, if the address is in AA3, the corresponding data is read from BS2 and set in OBR80. If it is not in AA3, block transfer processing is performed. In the next cycle, the ICTL 50 issues an instruction to the microprogram control circuit, and the operation according to the microprogram is performed.

The D stage of the next instruction (instruction (2)) is a cycle of ICTL
It starts at 50. This is to start by observing the instruction code of the instruction (1) and confirming that the E stage of the instruction (1) is completed in one machine cycle. If E is an instruction of 2 cycles or more, the D stage activation of the next instruction by the microprogram is issued to ICTL50 in the stage immediately before the final E stage.

As described above, the commands are processed one after another. IBVA6 is reset to "0" when the D stage of the instruction (2) is successful. (Insufficient use of IBRA4) On the other hand, AI for the cycle of instruction read in Fig. 2 (c)
After LI, the procedure is as follows.

That is, at the beginning of the cycle, since the D stage has not succeeded yet, the AI stage is activated again in the cycle. However, in the operation of INCA 11 at this time, as shown in FIG. 2B, since IBVA6 is "1", NIA + 8 (that is, address 108) is output. AA3 is referenced at this address. On the other hand, IFP13 is set to "1".

When the D stage is in a successful state at the end of the cycle, the Lp instruction is issued from ICTL50 to BCTL51 in the cycle. this
The BCTL 51 that has received the Lp instruction performs the following operation according to the reference result of AA3. That is, if the address (address 108) is on AA3, the corresponding data (instruction) is read from BS2 and sent to the instruction buffer, but if it is not on AA3, nothing is done. That is,
Do not generate block transfer.

Now, assuming that address 108 is on AA3, the 8-byte instruction read from BS2 is taken into IBRB because IFP13 is "1", and at the same time IBVB7 is set to "1".

At the L stage of instruction processing, NIA10 adds the instruction length at INCB12. That is, 4 is added to 100 and updated to 104 in the cycle. At the time of a branch instruction, the branch destination address is set in NIA10 by the path from ADR14. Next IC
In TL50, the next instruction read is activated in the cycle next to the cycle of the A stage. At this time, since the A to E stages of the preceding instruction (1) are being performed, the Ap instruction is issued by the ICTL50 in the next cycle. The address is 116 according to FIG.

This is an instruction prefetch instruction when the E stage of the preceding instruction (1) is not completed. The difference from the AI stage is Ap.
The next stage is always the Lp stage, and the Ap stage AA
As a result of the reference of 3, even if it is found that the instruction address is not in AA3, the block transfer is not activated regardless of the success or failure of the D stage of the next instruction (2).

Ap-Lp is shown in Fig. 2 (c) as a preemptive command prefetch.
It is started with ,,,.

However, looking at Ap-Lp of the instruction prefetching operation,
According to the figure (b), the AI address is NIA + 16, that is, 104 + 16 = 120 address, and IP16 indicates “0”. The 8-byte instruction (address 120) read from BS2 in the Lp stage (cycle 1) has an IP16 of "0".
Therefore, I try to import it into IBRA4. However, IBVA6 is "1"
Therefore, it cannot be loaded into IBRA4 and the read data (instruction) is discarded.

In this way, the instructions are processed as shown in FIG.

If the instruction address is not updated sequentially, as in the case of successful branching in a branch instruction, IBVA6 and IBVB7 are both reset to "0" and the newly read instruction is IB.
It is set to RA4 and IBRB5. Depending on the branch instruction type, this read may be performed by converting the data read from BS2 as an operand read into an instruction read.
Incorporated into RA4 or IBRB5. Details are omitted because they are known techniques.

Next, the case where the corresponding address is not on AA3 in the instruction prefetch Ap-Lp will be described. At this time, the instruction reading fails. Then, even if Ap-Lp is newly activated, it is not successful (except when the instruction is brought for the same block in the block transfer in the reading of the operand). When the prefetch instructions on IBRA4 and IBRB5 are used up, the pre-control of the stage of instruction (2) fails and the instruction read is restarted after the instruction (1) is completed. -Started in the form of LI, instruction (2) will be read by block transfer.

In block transfer, 64 bytes (hereinafter, byte is abbreviated as B) from the main memory 1 are transferred to BS2 and written. At this time, if the path 20 is 8B, it is transferred in 8 times. Therefore, in the data transfer order, the desired 8B is not always transferred first. During the block transfer, the ICTL50 is in a waiting state until the desired 8B reaches BS2. When the desired 8B is transferred, the ICTL 50 starts operating again and activates the D stage of instruction processing. Subsequent processing depends on the value of the instruction address and the processing type of the next instruction.

When the desired 8B data in the block transfer is transferred from the memory 1, the data (8 bytes) is written to BS2 and is kept as it is, depending on the value of IFP13, IBRA4 (when IFP13 is “0”) or IBRB5. (When IFP13 is “1” ”) At the same time, when the value of IFP13 is "0", IBVA6 is "1".
IBVB7 is set to “1” when IFP13 is “1”. In this state, the ICTL 50 activates the D stage, but when this D stage succeeds (that is, all the next instructions are in the instruction buffer), TS70 is set to "1" in this D stage. Then, the A stage is activated. In this A stage, an instruction to access the operand memory,
The operation differs depending on the instruction that does not access the operand memory (for example, using register data). For instructions that do not access the memory, input to the L stage after the A stage, and subsequently to the E stage (that is, instruction arithmetic processing)
to go into. Then, Ap-Lp is activated behind the instruction processing, but this Ap-Lp operation is ignored unless the block transfer processing is completed, and apparently, as if Ap activation did not occur (that is, Command processing continues without waiting.

FIG. 3 (a) will be described in more detail. Block transfer is performed by the AI-LI stage, data is transferred 8B by 8B and written to BS2. Now, when the desired 8B is transferred by, the data is written into the BS, and at the same time, taken into the IBRA4 as it is, and IBVA6 is set to "1". And the instruction (2) succeeded in D stage, and TS70
Set to “1”. This TS70 is reset to "0" at the end of the block transfer. Since both the instruction (2) and the instruction (3) do not access BS2 as an operand, they flow to the instruction stage D-AL-E. However, the instruction (4) does not operate if the operand requires memory access. )
After the end of the D stage, the block transfer completion waiting state is entered, and the E stage of the instruction (3) and the E stage of the instruction (4) are waited until the block transfer is completed. When the block transfer is completed, the BS2 access of the operand of the instruction (4) is processed as the AL stage, and the E stage of the instruction (3) is also executed.

Also, in the block transfer of an instruction, the D stage may fail even if the desired 8B data comes. For example, this is the case when the instruction to be decoded crosses the 8B boundary.
At this time, the 8B data pointed to by the address (target address + 8) adjacent to the desired 8B data (this is called 8B pointed by the target address) is transferred, and this is transferred to IBRA4 or IBRB5 on the opposite side pointed to by IFP13. The D stage becomes successful when it is captured. Until the D stage is successful, the instruction control stage will be continuous with the D stage. This case is shown in FIG. In this case, the desired 8B of block transfer data and the target address + 8 of data have been transferred. The instruction (3) has a waiting state in which the operand accesses BS2.

Next, a case where the D stage does not succeed even if the block transfer of the instruction is completed will be described. In this case, the decoding target instruction exists across the 64B boundary.
In this case, the AI stage is activated again after the block transfer is completed. That is, when TA70 is "0" and the block transfer for instruction read is completed, the AI stage at the end is started. By this AI-LI, the unfetched portion of the instruction to be decoded is fetched from BS2 to the instruction buffer 4 or 5. At this time, if the corresponding block is not in BS2 again, block transfer is activated.

Next, the operation when the target instruction of the branch instruction (the branch destination instruction when the branch is successful) is not present in BS2 will be described. In this case, the block transfer of the target instruction is performed at the A-L stage of the branch instruction itself (this is originally an operand stage, but the target instruction is fetched by the branch instruction) without waiting for the completion of the branch instruction. I do. This example is shown in FIG. The success or failure of the branch of the branch instruction is determined in the L stage. When the branch is successful and the target instruction is not in BS2, the block transfer is activated, and when the target instruction is fetched by the data, the E stage of the branch instruction itself and the D stage of the target instruction are activated.

FIG. 4B shows a case where the target instruction crosses block boundaries. At this time, after the block transfer is completed, the AI-LI stage is activated again at the target address + 8 address.

Further, when the E stage controlled by the microprogram does not end in one cycle, as shown in FIG. 5, instruction reading by the microprogram instruction or D of the next instruction (2) is performed.
The stage is activated.

In this embodiment, the instruction buffer register has two 8 bytes, but it is obvious that this can be applied to any configuration.

Further, the execution control is to shift the next instruction by two machine cycles in the basic instruction processing, but this may be shifted by one machine cycle or three machine cycles or more. When shifting by one machine cycle, it is necessary to read the operand, and when the operation cycle is one machine cycle of instructions, the buffer memory is occupied by the operand read every cycle, and the instruction prefetch access is not performed. It will be. However, when even one instruction (for example, an arithmetic instruction between register-register operands) that does not require access to the buffer memory of the operand appears, the A-L stage itself can operate as an Ap-Lp stage.

In the above embodiment, the data of the instruction block transfer is assumed to be transferred continuously, but this may be interrupted in the middle depending on the memory configuration. Further, it is obvious that the present invention can be applied to a configuration in which desired data is always transferred to the head. Although the transfer pitch is one machine cycle, the present invention can be implemented even when transferring at an arbitrary pitch, or when the data width and block size are arbitrary.

Although the stage is D-AL-E, this may be arbitrary. For example, it is also applicable to a case where D is divided into D-M and two stages (D is decoding, M is operand address calculation) and is shifted by two stages from the next instruction.

〔The invention's effect〕

As described above, according to the present invention, prefetching of instructions is
The buffer memory is accessed through a gap so as not to disturb the memory access of the operand of the preceding instruction, and when the instruction is not in the buffer memory, block transfer is activated or invalidated depending on whether the preceding instruction is processed. By dividing the case, the preceding instruction is being processed,
Even if the buffer access by the preceding instruction occurs, the block transfer of the instruction prefetch is suppressed,
The control on the buffer memory and the control on the instruction system register are simplified, and a high-performance instruction reading process can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram for explaining the basic operation of the present invention, FIG. 3 is a diagram for explaining the operation of instruction block transfer processing, and FIG. 4 is a branch instruction. 5 is a diagram for explaining the operation of FIG. 5, and FIG. 5 is a diagram for explaining the operation when the operation cycle does not end in one cycle. 1 ... Main memory, 2 ... Buffer memory, 3 ... Address array, 4,5 ... Instruction buffer, 6,7 ... Instruction buffer validity indicator, 8 ... Instruction cutout circuit, 9 ... Instruction register, 10
… Instruction address register, 11… Address incrementer, 70… Indicator of successful decoding under instruction block transfer.

Claims (2)

[Claims] 1. A method for prefetching instructions in an electronic computer comprising a main memory and a buffer memory for storing a copy of part of the contents of the main memory, wherein the instruction read target instruction exists in the buffer memory. Reads the instruction from the buffer memory, and if there is no instruction read target instruction in the buffer memory, activates block transfer if an instruction preceding the instruction read target instruction is not being processed. Reading the block of the instruction from the main memory and transferring it to the buffer memory, and invalidating the reading without activating the block transfer when the instruction preceding the instruction of the instruction reading is being processed. A method for prefetching instructions in a computer. 2. An instruction destination read control method for an electronic computer according to claim 1, wherein the instruction read target instruction is a branch destination instruction which is a target instruction of a branch instruction, and the branch destination instruction is stored in a buffer memory. If not present, a block transfer is activated as an operand read process of the branch instruction, and an instruction prefetch control method for a computer is characterized.