JPH0747873Y2 - Printed wiring board with semiconductor memory mounted - Google Patents

Printed wiring board with semiconductor memory mounted

Info

Publication number
JPH0747873Y2
JPH0747873Y2 JP1986062634U JP6263486U JPH0747873Y2 JP H0747873 Y2 JPH0747873 Y2 JP H0747873Y2 JP 1986062634 U JP1986062634 U JP 1986062634U JP 6263486 U JP6263486 U JP 6263486U JP H0747873 Y2 JPH0747873 Y2 JP H0747873Y2
Authority
JP
Japan
Prior art keywords
terminal
voltage
printed wiring
semiconductor memory
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1986062634U
Other languages
Japanese (ja)
Other versions
JPS62174351U (en
Inventor
泰弘 鳥山
千彦 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toppan Inc
Original Assignee
Toppan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toppan Inc filed Critical Toppan Inc
Priority to JP1986062634U priority Critical patent/JPH0747873Y2/en
Publication of JPS62174351U publication Critical patent/JPS62174351U/ja
Application granted granted Critical
Publication of JPH0747873Y2 publication Critical patent/JPH0747873Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Semiconductor Memories (AREA)

Description

【考案の詳細な説明】 (産業上の利用分野) 本考案は、外部へデータを端子より読み出せる半導体メ
モリーをマウントしたプリント配線板のうち、少なくと
も一つの端子が二値状態の高電圧より高い一定の電圧以
上になると別の動作をするメモリーを含むプリント配線
板に係わる。
[Detailed Description of the Invention] (Industrial field of application) The present invention discloses that at least one terminal of a printed wiring board mounted with a semiconductor memory capable of reading out data from the terminal is higher than a high voltage in a binary state. The present invention relates to a printed wiring board including a memory that operates differently when a voltage exceeds a certain level.

(従来の技術) 従来の半導体メモリーをマウントしたプリント配線板に
つき、図面を用いて説明する。第3図は従来のプリント
配線板の平面図であり、第2図は同底面図である。
(Prior Art) A conventional printed wiring board on which a semiconductor memory is mounted will be described with reference to the drawings. FIG. 3 is a plan view of a conventional printed wiring board, and FIG. 2 is a bottom view of the same.

プリント配線板の表面(21)には、第3図に示すように
メモリーと外部機器との電気的接続を図るための端子列
(23)が形成されており、この実施例では多数の端子を
効率良く配置するために、カードの短辺に沿って2列に
形成されており、さらに1列目と2列目とは互いの間に
位置するように(千鳥状に)配置されている。他方、第
2図に示すようにプリント配線板の裏面(22)には半導
体メモリー(24)がマウントされており、プリント配線
パターンにワイヤーボンディング等で接続されている。
このプリント配線パターンと外部接続端子とはエスルー
ホールで接続されており、さらに、プリント配線板の表
裏面は外部接続端子(23)及びメモリーマウント部を除
いて、絶縁及び保護を目的としてエポキシ樹脂が全面に
塗布されている。
On the surface (21) of the printed wiring board, as shown in FIG. 3, a terminal row (23) for electrical connection between the memory and an external device is formed. In this embodiment, a large number of terminals are provided. In order to arrange them efficiently, they are formed in two rows along the short side of the card, and the first row and the second row are arranged (staggered) so as to be located between each other. On the other hand, as shown in FIG. 2, a semiconductor memory (24) is mounted on the back surface (22) of the printed wiring board and is connected to the printed wiring pattern by wire bonding or the like.
The printed wiring pattern and the external connection terminals are connected by an through hole, and the front and back surfaces of the printed wiring board are made of epoxy resin for the purpose of insulation and protection except for the external connection terminals (23) and the memory mount. Is applied to the entire surface.

(考案が解決しようとする問題点) 上述の様なプリント配線板では、小さな面積に多くのプ
リント配線パターンが施されている。従って互いの配線
パターンどうしの間で結合容量が高くなり易くなる。こ
の様な結合容量が存在すると、一方の電圧が上昇すると
他方の電圧も影響を受け、引きずられる様に電圧が上昇
することとなる。一つの端子が二値状態の高電圧より更
に高い一定の電圧以上になると半導体メモリーが二値状
態の高電圧のときは別の動作をする機能を持っている端
子(以下三値端子と呼ぶ)と、一般に二値端子との間に
結合容量がある場合がある。そのとき、三値端子が中電
圧であり、二値端子が低電圧より高電圧へ変わったと
き、二値端子の高電圧化にひきずられて、三値端子の電
圧が中電圧より少し電圧が引き上がる。この現像が頭著
であることがあり、この様な場合二値状態の高電圧であ
る中電圧より更に高い一定の高電圧になったと半導体メ
モリーが判断し、三値目の動作をし、該読出が発生する
こととなる。
(Problems to be Solved by the Invention) In the printed wiring board as described above, many printed wiring patterns are provided in a small area. Therefore, the coupling capacitance between the wiring patterns tends to be high. In the presence of such coupling capacitance, when one voltage rises, the other voltage is also affected and the voltage rises in a dragged manner. A terminal that has the function of performing another operation when the semiconductor memory is at a high voltage in the binary state when one terminal becomes higher than a certain voltage that is higher than the high voltage in the binary state (hereinafter referred to as a ternary value terminal). In general, there may be a coupling capacitance between the binary terminal and the binary terminal. At that time, when the ternary terminal has a medium voltage and the binary terminal changes from a low voltage to a high voltage, the voltage of the ternary terminal is slightly higher than the medium voltage due to the increase in the voltage of the binary terminal. Pull up. This development is sometimes remarkable, and in such a case, the semiconductor memory judges that the constant high voltage, which is higher than the medium voltage which is the high voltage in the binary state, is reached, and the third value operation is performed. Reading will occur.

(問題を解決するための手段) 上記の様な問題点を解決する為に、三値端子と、二値状
態の高電圧もしくは低電圧を規定する端子との間に、結
合容量を補償しうる範囲内でかつ高抵抗である印刷抵抗
を施す。
(Means for Solving the Problem) In order to solve the above problems, it is possible to compensate the coupling capacitance between the ternary terminal and the terminal that defines the high voltage or the low voltage of the binary state. The printing resistance is applied within the range and having high resistance.

(作用) 本考案によるプリント配線板は、三値端子の電圧が二値
状態の高電圧である中電圧であり、かつこの端子との間
で結合容量を持つ二値端子が高電圧になったとき、三値
端子は結合容量により高電圧になろうとする。そこでこ
の端子は結合容量を補償しうる範囲内でかつ高抵抗であ
る印刷抵抗により二値状態の高電圧もしくは低電圧を規
定する端子とつながっている為に、その抵抗を通って電
流が流れ、その結合容量により中電圧よりの持ち上るべ
き分の電圧が補償され、その分、電圧が中電圧近くまで
アクセス時間内に低下し、別の動作をするまでの時間に
ならないうちに、中電圧帯まで電圧が引き下がる。
(Operation) In the printed wiring board according to the present invention, the voltage of the ternary terminal is the medium voltage which is the high voltage in the binary state, and the binary terminal having the coupling capacitance with this terminal becomes the high voltage At this time, the ternary terminal tries to reach a high voltage due to the coupling capacitance. Therefore, since this terminal is connected to the terminal that defines the high voltage or low voltage of the binary state by the printing resistance that is high resistance within the range that can compensate the coupling capacitance, current flows through the resistance, The coupling capacitance compensates for the voltage that should be raised above the medium voltage, and the voltage drops to near the medium voltage within the access time, and before the time to perform another operation, the medium voltage band Voltage drops to.

(実施例) 本考案による半導体メモリーをマウントしたプリント配
線板につき、図面を用いて詳細に説明を加える。第1図
は本考案のプリント配線板の平面図である。
(Example) A printed wiring board mounted with a semiconductor memory according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a plan view of the printed wiring board of the present invention.

プリント配線板の表面(21)には、第1図に示すように
従来例と同様にメモリーと外部機器との電気的接続を図
るための端子列(23)が形成されており、他方、裏面
(22)には半導体メモリー(24)がマウントされてお
り、プリント配線パターンにワイヤーボンディング等で
接続されており、さらに、プリント配線板の表裏面は外
部接続端子列(23)及びメモリーマウント部を除いて、
絶縁及び保護を目的としてエポキシ樹脂が全面に塗布さ
れている。なお、ここで述べられている外部接続端子の
中の特定の端子に二値状態の高電圧以上のある一定の高
電圧がかかるとシリコンシグネチャーという別な動作を
半導体メモリーが行なう働きをもつ三値端子があるとこ
ろで、この三値端子は、あるい特定二値端子との間に結
合容量が発生することがあり、例えば本例ではA9端子
(11)と呼ばれる端子がA8端子(12)と呼ばれる端子と
の結合容量が30pF以上ある。もちろん、他の端子におい
ては、A11、CE、A0、A5と呼ばれる端子でもこういう現
象が現れる。そうすると、アクセスタイムになっても、
実際に測定した値にて2.6Vもの電圧が残る。本例の場合
は二値状態の高電圧である中電圧が5Vであり、シリコン
シグネチャー電圧である高電圧が7.5Vがある為に、単に
A8端子(12)を高電圧にしようとしたときA9端子(11)
がすでに中電圧であれば、同じ電圧であっても三値端子
であるA9端子(11)はシリコンシグネチャー動作をす
る。それを防止する為に、シリコンシグネチャー動作を
する端子を二値状態の高電圧もしくは低電圧と抵抗を介
して接続している。本例では、低電圧を示すGND端子(1
3)との間に印刷抵抗(14)を施してある。なお、端子
と端子の間の不導体部の幅は1.04±0.2mmであるが、印
刷のバラツキ、ずれ、導電インキの進展などを考慮し
て、0.4mm程度の幅で各々の端子から印刷パターンをの
ばし、中央部分で接合させている。なお、各々の端子よ
りGND端子(13)への接合部分の印刷パターンは、端子
間電圧を均等にする様に回路長に従って1mmより0.4mm程
度まで印刷パターンの幅を1mm〜0.4mmの間で換えてあ
る。なお、ここで用いられた導電インクは求める抵抗値
により配合は変わるが本例では、フェノールが約30重量
%、カーボンが約70重量%、他に用材としてシンナーが
含まれているものを使った。この様な導電インクを用い
てスクリーン印刷をプリント配線板上に施して印刷抵抗
を設けた。
As shown in FIG. 1, on the front surface (21) of the printed wiring board, a terminal row (23) for electrical connection between the memory and an external device is formed as in the conventional example, while the back surface is formed. The semiconductor memory (24) is mounted on (22) and is connected to the printed wiring pattern by wire bonding or the like. Furthermore, the front and back surfaces of the printed wiring board include the external connection terminal row (23) and the memory mount section. Except,
An epoxy resin is applied to the entire surface for the purpose of insulation and protection. In addition, when a certain high voltage above the high voltage of the binary state is applied to a specific terminal among the external connection terminals described here, a three-valued semiconductor memory that performs another operation called a silicon signature Where there is a terminal, a coupling capacitance may occur between this ternary terminal and a specific binary terminal. For example, in this example, the terminal called A9 terminal (11) is called A8 terminal (12). The coupling capacitance with the terminal is 30pF or more. Of course, in other terminals, such a phenomenon also appears in terminals called A11, CE, A0, and A5. Then, even if it becomes access time,
A voltage of 2.6V remains in the actually measured value. In the case of this example, the medium voltage, which is a high voltage in the binary state, is 5V, and the high voltage, which is the silicon signature voltage, is 7.5V.
When trying to make the A8 terminal (12) high voltage A9 terminal (11)
If is already a medium voltage, the A9 terminal (11), which is a ternary terminal, performs a silicon signature operation even if the voltage is the same. In order to prevent this, a terminal that operates as a silicon signature is connected to a high voltage or low voltage in a binary state through a resistor. In this example, the GND terminal (1
There is a printing resistor (14) between it and 3). The width of the non-conductor part between terminals is 1.04 ± 0.2 mm, but in consideration of printing variations, misalignment, development of conductive ink, etc., print pattern from each terminal with a width of about 0.4 mm. Is extended and joined at the central part. The printed pattern of the joint from each terminal to the GND terminal (13) should be 1mm to 0.4mm depending on the circuit length so that the voltage between terminals is equal. It has been changed. Note that the conductive ink used here has a different composition depending on the resistance value sought, but in this example, we used about 30% by weight of phenol, about 70% by weight of carbon, and thinner as another material. . Screen printing was performed on the printed wiring board using such a conductive ink to provide a printing resistor.

この様に印刷路を施すと、A9端子とGND端子の間の抵抗
は約25KΩとなり、アクセス時間以内にシグネチャー電
圧にならない155ns以下の早い動作時間内に6V程度に電
圧が下がる。なお、この抵抗値をこれ以上下げすぎる
と、出力電流値が大きくなるが、一般に駆動CPUの出力
保証電流がサブミリアンペア単位であることが多いの
で、あまり下げすぎることはできない。
When the printed path is applied in this way, the resistance between the A9 terminal and the GND terminal is about 25 KΩ, and the voltage drops to about 6 V within the fast operation time of 155 ns or less that does not reach the signature voltage within the access time. If the resistance value is lowered too much, the output current value becomes large. However, since the output guaranteed current of the drive CPU is often in units of sub-milliamperes, it cannot be lowered too much.

従って印刷抵抗の抵抗値は10KΩから100KΩの間が適当
と思われる。この様に印刷が行なわれたプリント配線板
は、150℃に加熱して溶剤を揮発させ、次に印刷抵抗上
へフェノール樹脂等他の樹脂でも良いが本例ではエポキ
シ樹脂により印刷抵抗全体が隠れる様に印刷を施す。こ
れば、この印刷抵抗材料が耐水性が完全でなく、また皮
膜強度も充分ではないので、これを補強しようという趣
旨である。もっとも、耐水性、耐性強度性が強いものを
導電インクに使用すれば、これは省略可能なことはもち
ろんである。
Therefore, it seems appropriate that the resistance value of the printing resistor is between 10KΩ and 100KΩ. The printed wiring board printed in this way is heated to 150 ° C. to volatilize the solvent, and then another resin such as phenol resin may be used on the printing resistor, but in this example the epoxy resin hides the entire printing resistor. To print. This is because the printed resistance material is not completely waterproof and the film strength is not sufficient, so that it is intended to reinforce the material. Of course, this can be omitted if a conductive ink having high water resistance and strong resistance is used.

この様に処理を終えたプリント配線板に対して、以下の
試験を行ったが、異常は認められなかった。
The following test was performed on the printed wiring board that had been treated in this way, but no abnormality was observed.

i) ねじり試験 ±15°にて100回繰返しねじる。i) Torsion test Twist 100 times at ± 15 °.

ii) 折曲げ試験 カード長手方向に対して10mmの高さまで折曲げそれを10
0回繰返し折曲げる。
ii) Folding test Fold it up to a height of 10 mm with respect to the longitudinal direction of the card.
Bend 0 times repeatedly.

iii) 引っかき試験 筆圧試験機にて、200g(小人の筆圧)及び300g(大人の
筆圧)で引っかき試験を行う。
iii) Scratch test A scratch test is performed with a writing pressure tester at 200g (writing pressure for children) and 300g (writing pressure for adults).

iv) 高温保持 70℃90%の雰囲気中に48hr保持する。iv) Hold at high temperature Hold for 48 hours in an atmosphere of 70 ° C and 90%.

v) 熱サイクル試験 −10℃(30分)と+50℃(30分)の条件下で24サイクル
のヒートショックを与える。
v) Thermal cycle test A heat shock of 24 cycles is given under the conditions of -10 ° C (30 minutes) and + 50 ° C (30 minutes).

(考案の効果) 本考案により、半導体メモリーの一つの端子が二値状態
の高電圧より更に高い一定の電圧以上になると半導体メ
モリーが二値状態の高電圧のときとは別の動作をする機
能を持っており、その端子が二値状態の高電圧状態であ
ったとして、その端子と誤動作をするのに充分な結合容
量を持つ端子が高電圧になっても誤動作が起きなくなっ
た。
(Effects of the Invention) According to the present invention, when one terminal of the semiconductor memory becomes higher than the high voltage of the binary state by a certain voltage or more, the semiconductor memory operates differently from the high voltage of the binary state. Assuming that the terminal is in the high voltage state of the binary state, the malfunction does not occur even if the terminal having the coupling capacitance enough to malfunction with the terminal becomes the high voltage.

【図面の簡単な説明】[Brief description of drawings]

第1図は、本考案の一実施例を示す平面図、第2図は、
従来例を示す底面図、第3図は、同平面図である。 (11)……A9端子、(12)……A8端子 (13)……GND端子、(14)……印刷抵抗
FIG. 1 is a plan view showing an embodiment of the present invention, and FIG.
A bottom view showing a conventional example and FIG. 3 are plan views of the same. (11) …… A9 terminal, (12) …… A8 terminal (13) …… GND terminal, (14) …… Printing resistor

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】半導体メモリーと該半導体メモリーより引
き出した端子が設けられ、かつ該端子の内少なくとも一
つの端子が二値状態の高電圧より更に高い一定の電圧以
上になると該半導体メモリーが該二値状態の高電圧のと
きは他の動作をする機能を持っている端子であり、かつ
該他の動作をする機能を持っている端子が別の端子との
間で結合容量を持つプリント配線板において、前記他の
動作をする機能を持っている端子と二値状態の高電圧も
しくは低電圧を規定する端子との間に前記結合容量を補
償しうる範囲内の印刷抵抗が施されている事を特徴とす
る半導体メモリーをマウントしたプリント配線板。
1. A semiconductor memory and a terminal led out from the semiconductor memory are provided, and when at least one of the terminals has a certain voltage higher than a high voltage in a binary state, the semiconductor memory has the second voltage. A printed wiring board that is a terminal that has a function of performing another operation at a high voltage of a value state, and a terminal that has a function of performing another operation has a coupling capacitance with another terminal In the above item, a printing resistor within a range capable of compensating for the coupling capacitance is provided between the terminal having the function of performing the other operation and the terminal defining the high voltage or the low voltage in the binary state. A printed wiring board mounted with a semiconductor memory.
JP1986062634U 1986-04-25 1986-04-25 Printed wiring board with semiconductor memory mounted Expired - Lifetime JPH0747873Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986062634U JPH0747873Y2 (en) 1986-04-25 1986-04-25 Printed wiring board with semiconductor memory mounted

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986062634U JPH0747873Y2 (en) 1986-04-25 1986-04-25 Printed wiring board with semiconductor memory mounted

Publications (2)

Publication Number Publication Date
JPS62174351U JPS62174351U (en) 1987-11-05
JPH0747873Y2 true JPH0747873Y2 (en) 1995-11-01

Family

ID=30897092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986062634U Expired - Lifetime JPH0747873Y2 (en) 1986-04-25 1986-04-25 Printed wiring board with semiconductor memory mounted

Country Status (1)

Country Link
JP (1) JPH0747873Y2 (en)

Also Published As

Publication number Publication date
JPS62174351U (en) 1987-11-05

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